JPH04188876A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enable a process where a grounding electrode is formed to be simplified by a method wherein a high and a low concentration layer are formed on a sapphire substrate, elements are provided onto the low concentration layer, and a common grounding electrode is provided onto the high concentration layer. CONSTITUTION:An Si layer 3 of high impurity concentration is provided onto the sapphire substrate 2 of a semiconductor device, and furthermore an Si layer 4 of low impurity concentration is provided onto the layer 3 to constitute an SOS substrate. An SiO2 layer 5 is formed on the layer 4 and the exposed layer 3. MOS type transistor elements 7 are formed on the layer 5 provided onto the layer 4, contact holes 6a-6c are formed corresponding to the elements 7, and a contact hole 6d is formed on the layer 5 located on the layer 3. A G electrode 7a, an S electrode 7b, a D electrode 7c, and a common grounding electrode 7d are provided through the intermediary of the through-holes 6a, 6b, 6c, and 6d respectively. By this setup, the electrode 7d can be formed through the layer 3, whereby a MOS type transistor array can be easily manufactured.

Description

[Detailed Description of the Invention] [Summary] Regarding a semiconductor device in which a MOS type transistor array is formed on a sapphire substrate, the purpose of this invention is to easily form a common ground electrode for the transistor array on an SO8 substrate. a high concentration layer of impurities formed on the high concentration layer, a low concentration layer of impurities formed on the high concentration layer, a plurality of elements formed in an array on the low concentration layer, and a plurality of elements formed on the high concentration layer. A common ground electrode of the plurality of elements is formed.

[Industrial application field]

The present invention relates to a semiconductor device in which a MOS type transistor array is formed on a sapphire substrate.

In recent years, the use of sapphire substrates has been attracting attention due to the requirements for high speed and radiation resistance for semiconductor devices. Therefore 1. Due to the demand for higher integration of semiconductor devices, it is necessary to form transistors in an array on a sapphire substrate.

[Conventional technology]

FIG. 3 shows a manufacturing process diagram of a semiconductor device using a conventional sapphire substrate. In FIG. 3, the sapphire substrate 3
A P-type silicon (Si) layer 31 with a thickness of 1 to 2 μm is epitaxially grown on 0 (this state is
A silicon oxide (SiO=) layer 32 is formed on the P-type Si layer 31 by thermal oxidation (FIG. 3(A)).

Furthermore, the P-type Si layers 31 and 5i are etched by mesa etching.
For example, MOS (metal oxide semiconductor) in the ns layer 32
form a type transistor region (3rd IN (B))
. This mesa etching is wet etching using, for example, EPW (ethylene/pyrocatechol/water) or KOH (potassium hydroxide).

Then, in the transistor region on the layer 32,
A photoresist 33 is formed on the gate (G) region 31a by etching, and ions are implanted into the other source (S) region and drain (D) @ region to form an n+ well in each of the pWsi layers 31 (layer type 1). Figure 3 (C)). Therefore, the photoresist 33 and the 5102 layer 32 are removed, and annealing is performed to adjust the crystal alignment by ion implantation (
Figure 3 (D)). In FIG. 3(D), 31b is an S area and 31c is a D area.

Subsequently, an oxide film is formed on the Si layer 31 by CVD (chemical vapor deposition) or thermal oxidation to form a SiO* layer 34 (FIG. 3(E)) in each region 31a to 31 of the Si layer 3I.
A contact hole (not shown) is formed in 31c, and the source (S), gate (G),
Each electrode (35a to 35C) of train (D) is formed (FIG. 3(F)). A predetermined number of these are individually formed on the SO8 substrate.

In this case, it is necessary to form a ground electrode for a MOS type or 0MO3 type transistor, and the ground electrode is formed either not shown or by forming a contact hole or the like from the source (S) or drain (D) individually.

[Problem to be solved by the invention]

However, when forming a transistor array due to the demand for higher density, it is not possible to form a common ground electrode for each element, as shown in Figure 3, and a ground electrode is formed for each element individually to group them together. A ground electrode must be formed over the entire area. This poses a problem in that the manufacturing process of the semiconductor device becomes complicated.

Therefore, the present invention was made in view of the above problems, and
An object of the present invention is to provide a semiconductor device in which a common ground electrode of a transistor array on eight substrates can be easily formed.

[Means to solve the problem]

The above-mentioned problems include: a high impurity concentration layer formed on a sapphire substrate; a low impurity concentration layer formed on the high concentration layer; and a plurality of elements formed in an array on the low concentration layer.
This problem can be solved by providing a common ground electrode for the plurality of elements formed on the high concentration layer.

[Effect]

As described above, the S1 layer, which is a high impurity concentration layer and a low impurity concentration layer, is formed on the sapphire substrate. A plurality of elements are formed in an array in the low concentration layer, and a common ground electrode for the capacitive elements is formed in the high concentration layer. In other words, conventionally, only a Si layer for forming elements was formed on a sapphire substrate, so a common ground electrode for each element could not be obtained, whereas a high concentration layer formed on a sapphire substrate This makes it possible to form a common ground electrode.

This makes it possible to easily form a common ground electrode by simply adding an additional layer on the sapphire substrate without complicating the manufacturing process.

〔Example〕

FIG. 1 shows a configuration diagram of an embodiment of the present invention. In the semiconductor device I of FIG. 1, a Si layer (high concentration layer) 3 with a high concentration of impurities is formed on a sapphire substrate 2, and a Si layer (low concentration layer) with a low concentration of impurities is formed on the high concentration layer 3. A concentration layer) 4 is formed to constitute an SO8 substrate. A Si02 layer 5 is formed on the low concentration layer 4 and the exposed high concentration layer 3.

A plurality of MO3 type transistor elements 7 are formed in the 5iOz layer 5 on the low concentration layer 4, and contact holes 6a to 6c (others are omitted) corresponding to each element are formed, and the high concentration layer 3 A contact hole 6d is formed in the upper Si02 layer 5.
or formed. Here, on the Si02 layer 5, a gate (G) electrode 7a is formed through the contact hole 6a, a source (S) electrode 7b is formed through the contact hole 6b, and
A drain (D) electrode 7c is formed through 6c, and a common ground electrode 7d of each transistor is formed through 6d.
is formed. Although not shown, a sub-electrode for wiring is connected to the ground electrode 7d.

In this way, since the ground electrode 7d can be easily formed using the high concentration layer 3, a MOS type transistor array can be easily manufactured on the SO3 substrate (on the sapphire substrate 2) without complicating the manufacturing process. I can do something.

Next, FIG. 2 shows a manufacturing process diagram of the semiconductor device of the present invention. Similarly to FIG. 1, FIG. 2 representatively shows one of the formations of a MOS type transistor array and omits the others.

In FIG. 2, a p1 type Si layer (high concentration layer) 3 with a high impurity concentration (IO"an-') is formed on a sapphire substrate 2.
is formed by epitaxial growth to a thickness of 1.5 μm. Furthermore, impurities are present on the high concentration layer 3 at a low concentration (10" am-
2) p-type Si layer (low concentration layer) 4 has a thickness of l. It is formed by epitaxial growth to a thickness of 5 μm. Then, Si is deposited on the low concentration layer 4 to a thickness of 0.5 μm by thermal oxidation or CVD.
An O2 layer 1o is formed (FIG. 2(A)).

Next, the low concentration layer 4 on which the SiO2 layer 10 has been formed is selectively subjected to mesa etching by EPW and KOH wet etching as described above (FIG. 2(B)). That is, regions of the low concentration layer 4 where MOS transistors, which are a plurality of elements (7), are formed are selectively left by mesa etching.

Therefore, a photoresist 6 is applied and the source (S) region 11 of the low concentration layer 4 is etched using a mask pattern.
b and drain (D) region lIC are exposed.

Note that the portion on the low concentration layer 4 where the photoresist 6 is present indicates the gate (G) region 11a. Then, ions are implanted into the exposed portion to form an n+ well in the source (S) region 11b and train (D) region 11c (see FIG.
C)).

Subsequently, the photoresist 6 and the Si02 layer 1o are removed,
Annealing is performed (Figure 3 (D)). Annealing is performed to adjust the crystalline arrangement disturbed by ion implantation as described above, and is heated at, for example, 900'C for 10 minutes.

Next, by patterning to form contact holes 6a to 6d on each region 11a to Ilc of the low concentration layer 4 and at a predetermined position in the high concentration layer 3, other surfaces are thermally oxidized to form Si02
Layer 5 is formed (FIG. 2(E)). In this case, although not shown, the patterning is performed so as to expose a sub-electrode region where wiring such as ground electrode bonding is to be performed.

Then, aluminum electrodes 7a to 7d are formed by vapor deposition on the contact holes 6a to 6c of the low concentration layer 4 and on the contact hole 6d of the high concentration layer 3 (including the sub-electrode region) (FIG. 2(F)). .

That is, 7a is the gate (G) electrode, 7b is the source (S)
) electrode, 7c is a drain (D) electrode, and 7d is a common ground electrode. In this case, the ground electrode 7d is the source (S)
It is connected to either the electrode 7b or the train (D) electrode 7c (not shown).

〔Effect of the invention〕

As described above, according to the present invention, a high concentration layer and a low concentration layer are formed on a sapphire substrate, a plurality of elements are formed on the low concentration layer, and a common ground electrode is formed on the high concentration layer. Accordingly, the ground electrode can be formed without complicating the manufacturing process, and elements such as array-shaped MO3 type transistors can be easily manufactured.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a manufacturing process diagram of a semiconductor device of the present invention, and FIG. 3 is a manufacturing process diagram of a conventional semiconductor device using a sapphire substrate. In the figure, ■ is a semiconductor device, 2 is a sapphire substrate, 3 is a high concentration layer, 4 is a low concentration layer, 5, 1O is a 5ins layer, 7 is an element, 7a is a gate (G) electrode, 7b is a source (S) ! 7C is a drain (D) electrode, and 7d is a ground electrode. FIG. 1 is a configuration diagram of an embodiment of the present invention; FIG. 2 is a manufacturing process diagram of a semiconductor device of the present invention.
Figure (C) Figure 6 (F) is a manufacturing process diagram of a semiconductor device using a conventional sapphire substrate.

Claims (1)

[Claims] A high impurity concentration layer (3) formed on a sapphire substrate (2), and a low impurity concentration layer (4) formed on the high concentration layer (3).
), a plurality of elements (7) formed in an array on the low concentration layer (4), and a plurality of elements (7) formed on the high concentration layer (3).
A semiconductor device characterized by having a common ground electrode (7d).