JPH04188659A - Surface mounting semiconductor device - Google Patents

Surface mounting semiconductor device

Info

Publication number
JPH04188659A
JPH04188659A JP31361290A JP31361290A JPH04188659A JP H04188659 A JPH04188659 A JP H04188659A JP 31361290 A JP31361290 A JP 31361290A JP 31361290 A JP31361290 A JP 31361290A JP H04188659 A JPH04188659 A JP H04188659A
Authority
JP
Japan
Prior art keywords
semiconductor device
shaped
outer lead
area
printed board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP31361290A
Other languages
Japanese (ja)
Inventor
Atsushi Shimizu
清水　厚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Kyushu Ltd
Original Assignee
NEC Kyushu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Kyushu Ltd filed Critical NEC Kyushu Ltd
Priority to JP31361290A priority Critical patent/JPH04188659A/en
Publication of JPH04188659A publication Critical patent/JPH04188659A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To realize the reduction of mounting surface in area and to ensure the contact surface of an outer lead with a printed board by a method wherein the outer lead of a semiconductor device is formed Z-shaped. CONSTITUTION:Outer leads 12a and 12b of a resin sealed type surface mounting semiconductor device 11 are formed Z-shaped. The lower side of the Z-shaped outer lead 12a is parallel with the base of the molded package 11, so that the outer lead 12a can be enhanced in contact area with a printed board and lessened in outer shape. By this setup, two conditions, the reduction of a package in mounting area and the enlargement of contact surface between an outer lead and a printed board in area, can be satisfied.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、プリント基板上に表面実装される半導体装置
の外部リード形状に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the shape of external leads of a semiconductor device surface-mounted on a printed circuit board.

〔従来の技術〕[Conventional technology]

従来、この種の半導体装置の外部リードは、第２図のよ
うに外側に曲がっているもの、第３図のように内側にＪ
形に曲がっているものがある。Conventionally, the external leads of this type of semiconductor device have been bent outward as shown in Figure 2, or bent inward as shown in Figure 3.
Some of the shapes are curved.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の表面実装用半導体装置の外部リードの形
状は、第２．３図のようになっており、第２図のものに
ついては外部リードが外側に曲げである為、その分実装
面積か広くなる。また、第３図のものについては外部リ
ードがＪ形になっている為、外部リードとプリント基板
との接触面積か小さいという欠点がある。The shape of the external lead of the conventional surface mount semiconductor device mentioned above is as shown in Figure 2.3. In the case of the one in Figure 2, the external lead is bent outward, so the mounting area is reduced accordingly. It becomes wider. Furthermore, since the external lead of the one shown in FIG. 3 is J-shaped, there is a drawback that the contact area between the external lead and the printed circuit board is small.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の表面実装用半導体装置は外部リード形状がＺ形
をしているというものである。In the surface mounting semiconductor device of the present invention, the external lead shape is Z-shaped.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図は、本発明の一実施例の側面図である。FIG. 1 is a side view of one embodiment of the present invention.

この実施例は樹脂封止型の表面実装用半導体装置の外部
リード１２ａ、１２ｂがＺ形（厳密にはＺ形又は逆Ｚ形
）をしているというものである。In this embodiment, external leads 12a and 12b of a resin-sealed surface-mount semiconductor device are Z-shaped (strictly speaking, Z-shaped or inverted Z-shaped).

２の下辺がモールドパッケージ１１の底面と平行になっ
ているので、プリント基板との接触面積は第２図の従来
例と同じように大きくなり、外形は第３図の従来例と同
じように小さくなる。Since the lower side of 2 is parallel to the bottom surface of the molded package 11, the contact area with the printed circuit board is large as in the conventional example shown in Fig. 2, and the external size is small as in the conventional example shown in Fig. 3. Become.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、外部リード形状をＺ形に
することにより、実装面積の縮小及び外部リードとプリ
ント基板との接触面積の確保といった２つの条件を同時
に満たす表面実装用半導体装置が得られるという効果が
ある。As explained above, the present invention provides a surface mount semiconductor device that simultaneously satisfies the two conditions of reducing the mounting area and securing the contact area between the external leads and the printed circuit board by making the external lead shape Z-shaped. It has the effect of being

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例の側面図、第２図及び第３図
はそれぞれ表面実装用の半導体装置の従来例の側面図で
ある。 １１．２１．３１・・・モールドパッケージ、１２ａ、
１２ｂ、２２ａ、２２ｂ、２３ａ、２３ｂ−・−外部リ
ード。FIG. 1 is a side view of one embodiment of the present invention, and FIGS. 2 and 3 are side views of conventional examples of surface-mounted semiconductor devices, respectively. 11.21.31...Mold package, 12a,
12b, 22a, 22b, 23a, 23b--external leads.

Claims (1)

【特許請求の範囲】[Claims] 外部リードがＺ形になっていることを特徴とする表面実
装用半導体装置。A surface mount semiconductor device characterized in that external leads are Z-shaped.
JP31361290A 1990-11-19 1990-11-19 Surface mounting semiconductor device Pending JPH04188659A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31361290A JPH04188659A (en) 1990-11-19 1990-11-19 Surface mounting semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31361290A JPH04188659A (en) 1990-11-19 1990-11-19 Surface mounting semiconductor device

Publications (1)

Publication Number Publication Date
JPH04188659A true JPH04188659A (en) 1992-07-07

Family

ID=18043416

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31361290A Pending JPH04188659A (en) 1990-11-19 1990-11-19 Surface mounting semiconductor device

Country Status (1)

Country Link
JP (1) JPH04188659A (en)

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