JPH0418744A - Support for semiconductor wafer - Google Patents
Support for semiconductor waferInfo
- Publication number
- JPH0418744A JPH0418744A JP2122483A JP12248390A JPH0418744A JP H0418744 A JPH0418744 A JP H0418744A JP 2122483 A JP2122483 A JP 2122483A JP 12248390 A JP12248390 A JP 12248390A JP H0418744 A JPH0418744 A JP H0418744A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- semiconductor
- support
- semiconductor wafer
- supporting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 73
- 150000001875 compounds Chemical class 0.000 claims abstract description 34
- 238000000034 method Methods 0.000 claims abstract description 23
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 239000000470 constituent Substances 0.000 claims description 8
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 150000003377 silicon compounds Chemical class 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 235000012431 wafers Nutrition 0.000 abstract description 96
- 238000011109 contamination Methods 0.000 abstract description 20
- 239000002184 metal Substances 0.000 abstract description 15
- 238000010884 ion-beam technique Methods 0.000 abstract description 9
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 abstract description 6
- 230000006866 deterioration Effects 0.000 abstract description 4
- 238000005468 ion implantation Methods 0.000 abstract description 3
- 229910052681 coesite Inorganic materials 0.000 abstract description 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 2
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 abstract description 2
- 239000000377 silicon dioxide Substances 0.000 abstract description 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 2
- 229910052682 stishovite Inorganic materials 0.000 abstract description 2
- 229910052905 tridymite Inorganic materials 0.000 abstract description 2
- 239000011248 coating agent Substances 0.000 description 6
- 238000000576 coating method Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 230000001681 protective effect Effects 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000002542 deteriorative effect Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 241001168730 Simo Species 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000010849 ion bombardment Methods 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Landscapes
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
半導体ウェーハ処理装置における半導体つｌ〜ハ支持方
法に関し、
半導体ウェーハに形成されている絶縁膜の膜厚精度劣化
を招かないで、且つ極端なコスト増を必要としないで、
半導体ウェーハの金属汚染を少なくさせるようにするこ
とを目的とし、
半導体ウェーハに支持部材を当接して該ウェーハを支持
するに際しζ、該ウェーハ表面の前記当接箇所を含む局
部領域に該ウェーハの半導体を反応させた半導体化合物
膜を形成してから、該支持部材を当接するように構成し
、特に、前記半導体化合物）ｊ々は、前記ウェーハに前
記支持部材を当接する直前に、該化合物膜の構成元素を
含む雰囲気で、該ウェーハと該支持部材との間に、該ウ
ェーハを負側にした直流のプラズマ放電を起こさせて形
成するように構成する。[Detailed Description of the Invention] [Summary] Regarding a method for supporting a semiconductor wafer in a semiconductor wafer processing apparatus, the present invention provides a method for supporting a semiconductor wafer without deteriorating the accuracy of the thickness of an insulating film formed on a semiconductor wafer and without causing an extreme increase in cost. don't need it,
The purpose of this method is to reduce metal contamination of a semiconductor wafer, and when a support member is brought into contact with the semiconductor wafer to support the wafer, the semiconductor of the wafer is deposited on a local area including the contact point on the surface of the wafer. In particular, the semiconductor compound film is formed so as to contact the support member after forming a semiconductor compound film in which the semiconductor compound film is reacted with the wafer. A direct current plasma discharge is generated between the wafer and the supporting member in an atmosphere containing the constituent elements, with the wafer on the negative side.
本発明は、半導体ウェーハ処理装置における半導体ウェ
ーハ支持方法に関する。The present invention relates to a method for supporting a semiconductor wafer in a semiconductor wafer processing apparatus.
近年、半導体装置の微細化に伴い、その製造工程では、
半導体ウェーハ処理装置内における金属汚染の影響が益
々重要になりつつある。In recent years, with the miniaturization of semiconductor devices, in the manufacturing process,
The effects of metal contamination within semiconductor wafer processing equipment are becoming increasingly important.
即ち、ウェーハが金属で汚染されると、ｐ−ｎ接合部に
おけるリーク電流の増大、絶縁膜の耐電圧劣化、などの
悪影響が表れ、一方微細デバイスばこれらの悪影響に対
し益々敏感になっているためである。In other words, when a wafer is contaminated with metal, negative effects such as an increase in leakage current at the p-n junction and a deterioration of the withstand voltage of the insulating film appear, and on the other hand, micro devices are becoming increasingly sensitive to these negative effects. It's for a reason.
そこで、半導体ウェーハ処理装置における半導体ウェー
への支持は、ウェーハの金属汚染が少ないようムこする
ことが望まれる。Therefore, it is desirable that the support for the semiconductor wafer in the semiconductor wafer processing apparatus be made more rigid so that metal contamination of the wafer is reduced.
上記金属汚染の汚染源は、イオンビームやプラズマを利
用する半導体ウェーハ処理装置自身の構成部材である場
合が多い。そして、ウェーハの表面を汚染した金属は、
その後のイオン衝撃によって浅く （数１０〜１００人
程度の深さに）ノックオン注入されてしまう。The source of the metal contamination is often the constituent members of the semiconductor wafer processing apparatus itself, which utilizes ion beams and plasma. The metal that contaminated the wafer surface is
The ensuing ion bombardment results in a shallow knock-on injection (to a depth of about 10 to 100 people).
このよ・うな汚染を軽減するために、従来、シリコンウ
ェーハへのイオンビーム照射などにおいて番よ、予めウ
ェーハ全面を薄いシリコン酸化膜保護膜で被っておき、
ビーム照射後に、表面に何着した更には浅（ノックオン
注入された汚染金属共々この酸化膜保護膜をエツチング
除去することが行われている。In order to reduce such contamination, conventionally, when irradiating silicon wafers with ion beams, the entire surface of the wafer is covered in advance with a thin silicon oxide protective film.
After the beam irradiation, this oxide protective film is removed by etching along with any contaminant metal deposited on the surface and also shallowly implanted (knock-on implanted).
また、Ｓ Ｉ Ｍ ＯＸ （Ｓｅｐａｒａｔｉｏｎ ｂ
ｙ ＩｍｐｌａｎｔｅｄＯｘｙｇｅｎ）など特にイオン
ビーム照射量が多く汚染も多いと考えられる処理装置で
は、ビーム照射範囲の構成部材すべてに対しシリコン被
覆を施すなどの対策が取られていた。In addition, S I M OX (Separation b
In processing equipment, such as ion beam irradiation systems (Implanted Oxygen), which are considered to be particularly susceptible to high ion beam irradiation and contamination, measures have been taken, such as coating all constituent members in the beam irradiation range with silicon.
Ｃ発明が解決しようとする課題〕
しかしながら、前記酸化膜保護膜を設ける方法は、その
保護膜のエツチング除去の際に予め形成されている他の
酸化膜、例えばフィールド絶縁膜などもエツチングされ
るので、半導体デバイスの一層の微細化により酸化膜等
の厚さ精度が厳しくなると、その精度維持が困難となる
問題がある。C Problems to be Solved by the Invention] However, in the method of providing the oxide protective film, other oxide films that have been formed in advance, such as a field insulating film, are also etched when the protective film is removed by etching. There is a problem in that when the accuracy of the thickness of an oxide film or the like becomes stricter due to further miniaturization of semiconductor devices, it becomes difficult to maintain the accuracy.
また、ＳＴＭＯＸ装置のように多くの構成部材にシリコ
ン被覆することは、そのコスト、更にはｗｊ、覆膜維持
のための保守コストが非常に高くつく問題がある。Further, coating many constituent members with silicon as in the STMOX device has the problem that the cost, and furthermore, the maintenance cost for maintaining the wj and coating are extremely high.
ところで、本発明者は、多くの経験から、半導体ウェー
ハ処理装置におけるウェーハの金属汚染の汚染源が主と
してウェーハの支持部材である知見を得た。By the way, the present inventor has obtained the knowledge from a lot of experience that the source of metal contamination of wafers in semiconductor wafer processing equipment is mainly the wafer support member.
即ち、上記支持部材は、ウェーハ主面に直接当接されて
金属を付着させ、またウェーハと共にイオンビームやプ
ラズマに曝された時にスパッタされて近傍に金属を振り
まくことにより、他の構成部材よりも汚染作用が顕著で
あるためと思われる。In other words, the supporting member has metal attached to it by directly contacting the main surface of the wafer, and is sputtered when exposed to an ion beam or plasma together with the wafer, scattering metal nearby, so that it is more durable than other constituent members. This is thought to be due to the significant contamination effect.
本発明は、半導体ウェーハに形成されている絶縁膜の膜
厚精度劣化を招かないで、且つ極端なコスト増を必要と
しないで、半導体ウェーハの金属汚染を少なくさせる半
導体ウェーハ支持方法の提供を目的とする。An object of the present invention is to provide a method for supporting a semiconductor wafer that reduces metal contamination of the semiconductor wafer without deteriorating the accuracy of the thickness of the insulating film formed on the semiconductor wafer and without requiring an extreme increase in cost. shall be.
上記目的を達成するために、本発明の半導体ウェーハ支
持方法は、半導体ウェーハに支持部材を当接して該ウェ
ーハを支持するるこ際して、該ウェーハ表面の前記当接
箇所を含む局部領域に該ウェーハの半導体を反応させた
半導体化合物膜を形成してから、該支持部材を当接する
ことを特徴としている。In order to achieve the above object, the semiconductor wafer supporting method of the present invention provides a method for supporting a semiconductor wafer, in which a support member is brought into contact with a semiconductor wafer to support the wafer, and a local area including the contact point on the surface of the wafer is provided. The method is characterized in that a semiconductor compound film is formed by reacting the semiconductor of the wafer, and then the supporting member is brought into contact with the semiconductor compound film.
前記半導体化合物膜は、前記ウェーハの支持路ｊ′後に
エツチング除去するのが望ましい。Preferably, the semiconductor compound film is etched away after the wafer support path j'.
そして、前記半導体化合物膜は、前記ウェーハムこ前記
支持部材を当接する直前に、該化合物膜の構成元素を含
む雰囲気で、該ウェーハと該支持部材との間にプラズマ
放電を起こさせて形成することができる。このプラズマ
放電は、減圧中の直流放電であり、前記ウェーハを負側
とするのが望ましい。The semiconductor compound film is formed by causing plasma discharge between the wafer and the support member in an atmosphere containing constituent elements of the compound film immediately before the wafer contacts the support member. I can do it. This plasma discharge is a direct current discharge under reduced pressure, and it is desirable that the wafer be on the negative side.
また、前記半導体ウェーハがシリコンウェーハである場
合には、前記半導体化合物膜はシリコン酸化膜またはシ
リコン窒化膜であるのが望ましく、また、前記支持部材
の表面はシリコンまたは導電性のシリコン化合物である
のが望ましい。Further, when the semiconductor wafer is a silicon wafer, the semiconductor compound film is preferably a silicon oxide film or a silicon nitride film, and the surface of the support member is preferably silicon or a conductive silicon compound. is desirable.
適宜な局部領域に形成された前記半導体化合物膜は、半
導体ウェーハ上の膜厚精度が要求されている絶縁膜に重
なることがなく、然も、前記支持部材を汚染源とする汚
染の大部分を受は止めて半導体ウェーハ自体の汚染を阻
止するので、その後高温の熱工程がない場合には敢えて
除去する必要がない。このことから上記絶縁膜の膜厚精
度を損ねることがない。The semiconductor compound film formed in a suitable local area does not overlap the insulating film on the semiconductor wafer, which requires film thickness accuracy, and also receives most of the contamination from the support member. Since this prevents contamination of the semiconductor wafer itself, there is no need to remove it if there is no high-temperature thermal process to be performed afterwards. Therefore, the thickness accuracy of the insulating film is not impaired.
この半導体化合物膜を除去すれば、該化合物膜が受は止
めた」二重汚染を除去することができて一層望ましい。It is more desirable to remove this semiconductor compound film because it is possible to remove the double contamination that the compound film has prevented.
その際にも、上記局部領域以外の領域にかけるマスクを
、上記絶縁膜を損ねることなしに除去できるもの例えば
レジストなどにすることができるので、該絶縁膜の膜厚
精度劣化を招くことがない。In this case, the mask applied to areas other than the local area can be made of a material that can be removed without damaging the insulating film, such as a resist, so that the accuracy of the film thickness of the insulating film will not deteriorate. .
そして、上記プラズマ放電による上記半導体化合物膜の
形成は、放電領域により上記適宜な局部領域を自動的に
形成し、然も、ウェーハ保持の直前に行われて工程上好
都合であり、且つ、ウェーハを負側とすることが支持部
材からのスパッタ汚染を軽減する。The formation of the semiconductor compound film by the plasma discharge automatically forms the appropriate local region by the discharge region, and is convenient for the process because it is performed immediately before holding the wafer. Setting it to the negative side reduces sputter contamination from the support member.
また、半導体ウェーハがシリコンウェーハである場合、
前記半導体化合物膜をシリコン酸化膜またはシリコン窒
化膜にするとウェーハの汚染が少なく、前記支持部材の
表面をシリコンまたは導電性のシリコン化合物にすると
その汚染が更に軽減する。Also, if the semiconductor wafer is a silicon wafer,
When the semiconductor compound film is a silicon oxide film or a silicon nitride film, contamination of the wafer is reduced, and when the surface of the support member is made of silicon or a conductive silicon compound, the contamination is further reduced.
そして、先に述べたように顕著な汚染源が該支持部材に
特定されるので、ＳＩＭＯＸ装置においては、他の構成
部材のシリコン被覆が不要となり従来のような極端なコ
スト増を必要としない。And, as mentioned above, since a significant source of contamination is identified in the supporting member, the SIMOX device does not require silicon coating of other constituent members, and does not require an extreme increase in cost as in the conventional case.
以下本発明の実施例について第１図及び第２図を用いて
説明する。第１図は実施例を説明するための側断面図で
、（ａｌは半導体化合物膜形成の時点、（ｂ）はウェー
ハ支持の時点、第２図は実施例適用処理装置におけるウ
ェーハ支持部の配置を示す側断面図、である。Embodiments of the present invention will be described below with reference to FIGS. 1 and 2. FIG. 1 is a side sectional view for explaining the example, (al is at the time of semiconductor compound film formation, (b) is the time of wafer support, and FIG. 2 is the arrangement of the wafer support part in the processing apparatus to which the example is applied. FIG.
この実施例は、本発明をイオン注入装置に適用した場合
のものである。This embodiment is a case where the present invention is applied to an ion implantation device.
第１図＋ａｌ （ｂｌにおいて、同図は第２図のように
イオン注入装置１のエンドステーション２に配置される
ウェーハ支持部３を示し、４はディスク（１）、５はウ
ェーハバッド、６は支持部材、６ａは支持部材基部（Ｉ
ｆ）、６ｂは支持部材先端部（ＳｉＣまたばＳｉＣ被覆
） 、７ａ、 ７ｂは給電部材（先端部５ｉＣ）、８は
半導体化合物膜、ＷはＳｉウェーハ、Ｐはプラズマ、Ｉ
Ｂはイオンビーム、である。Figure 1+al (In BL, this figure shows the wafer support part 3 placed at the end station 2 of the ion implanter 1 as shown in Figure 2, 4 is a disk (1), 5 is a wafer pad, 6 is a The support member 6a is the support member base (I
f), 6b is the support member tip (SiC or SiC coating), 7a, 7b is the power supply member (tip 5iC), 8 is the semiconductor compound film, W is the Si wafer, P is the plasma, I
B is an ion beam.
このウェーハ支持部３は、ウェーハパット５上のウェー
ハＷに支持部材６ （支持部材先端部６ｂ）を」一方か
ら当接して該ウェーハＷを支持するものである。そして
支持部材基部６ａは、後述する電圧印加のためにディス
ク４との係合部が絶縁被覆しである。The wafer support section 3 supports the wafer W on the wafer pad 5 by bringing the support member 6 (support member tip 6b) into contact with the wafer W from one side. The support member base 6a has an insulating coating at the engagement portion with the disk 4 for applying a voltage as described later.
先ず（ａｌを参照して、ウェーハ交換によりウェーハＷ
がウェーハバッド５上に載置され、支持部材先端部６ｈ
をウェーハＷに当接する直前に、給電部材７ａ、 ７ｂ
をウェーハＷに接触させると共にエンドステーション２
内を０．１〜ｌ Ｔｏｒｒの酸素（０□）雰囲気にし、
ウェーハＷと支持部材６との間にウェーハＷを負側にし
た約ＩＫＶの直流電圧を印加してプラズマ放電を起こさ
せる。この放電により発生したプラズマＰの０４により
、ウェーハＷの表面における支持部材先端部６ｂの当接
箇所を含む局部領域が酸化されて、その局部領域に５ｉ
Ｏｚからなる半導体化合物膜８が形成される。放電時間
は約１分で、半導体化合物膜８の厚さは約１００人であ
る。First, the wafer W is replaced by wafer exchange (see al.
is placed on the wafer pad 5, and the support member tip 6h
Immediately before contacting the wafer W, the power supply members 7a, 7b
is brought into contact with the wafer W and the end station 2
Create an oxygen (0□) atmosphere of 0.1 to 1 Torr inside.
A DC voltage of about IKV with the wafer W on the negative side is applied between the wafer W and the support member 6 to cause plasma discharge. The plasma P generated by this discharge oxidizes a local area on the surface of the wafer W, including the contact area of the support member tip 6b, and 5i
A semiconductor compound film 8 made of Oz is formed. The discharge time was about 1 minute, and the thickness of the semiconductor compound film 8 was about 100 mm.
次いでｆｂ）を参照して、支持部材先端部６ｂをウェー
ハＷに当接してウェーハＷを支持し、イオンビームＴＲ
を照射して所定のイオン注入処理を行う。Then, referring to fb), the support member tip 6b is brought into contact with the wafer W to support the wafer W, and the ion beam TR is
is irradiated to perform a predetermined ion implantation process.
ウェーハＷを取り出した後は、半導体化合物膜８領域以
外の領域にレジストのマスクをかけ弗酸（ＨＦ）水溶液
に浸漬して化合物膜８を除去し、更にレジス］・のマス
クを除去して処理工程を完了する。After taking out the wafer W, the area other than the semiconductor compound film 8 is covered with a resist mask and immersed in a hydrofluoric acid (HF) aqueous solution to remove the compound film 8, and then the resist mask is removed and processed. Complete the process.
なお化合物膜８が後工程の邪魔にならない場合は、化合
物膜８を除去しないで残したままとしても良い。Note that if the compound film 8 does not interfere with subsequent steps, the compound film 8 may be left without being removed.
この実施例により本発明者は、ウェーハＷに形成されて
いる絶縁膜の膜厚精度劣化を招かないで、且つＳＩＭＯ
Ｘ装置においても極端なコスト増を必要としないで、ウ
ェーハＷの全面に前記酸化膜保護膜を形成した場合と同
等に金属汚染を少なくさせることができた。With this example, the inventor has succeeded in achieving a SIMO
In the X apparatus as well, metal contamination could be reduced to the same extent as in the case where the oxide protective film was formed on the entire surface of the wafer W without requiring an extreme increase in cost.
上記実施例では、半導体化合物膜８をＳｉＯ２にしたが
、エンドステーション２内の雰囲気を窒素（Ｎ２）にし
て半導体化合物膜８を５ｉＪ４にしても同様の結果が得
られる。また、支持部材先端部６ｂの表面をＳｉＣの代
わりにＳｉにしても好結果を得ることができる。In the above embodiment, the semiconductor compound film 8 is made of SiO2, but similar results can be obtained even if the atmosphere in the end station 2 is nitrogen (N2) and the semiconductor compound film 8 is made of 5iJ4. Also, good results can be obtained by using Si instead of SiC for the surface of the support member tip 6b.
以上説明したように本発明によれば、半導体ウェーハ処
理装置における半導体ウェーハ支持方法に関し、半導体
ウェーハに形成されている絶縁膜の膜厚精度劣化を招か
ないで、且つ極端なコメ１〜増を必要としないで、半導
体ウェーハの金属汚染を少なくさせる支持方法が提供さ
れて、半導体装置の一層の微細化に際して特性劣化の回
避を可能にさせる効果がある。As explained above, according to the present invention, the method for supporting a semiconductor wafer in a semiconductor wafer processing apparatus can be performed without causing deterioration in the accuracy of the insulating film formed on the semiconductor wafer, and without requiring an extreme increase in the thickness of the insulating film formed on the semiconductor wafer. A supporting method is provided that reduces metal contamination of a semiconductor wafer without causing the metal contamination of the semiconductor wafer, and has the effect of making it possible to avoid characteristic deterioration when semiconductor devices are further miniaturized.
第１図は実施例を説明するための側断面図で、（ａｌは
半導体化合物膜形成の時点、
ｆｂ）はウェーハ支持の時点、
第２図は実施例適用処理装置におけるウェーハ支持部の
配置を示ず側断面図、
である。図において、
１はイオン注入装置、
２はエンドステーション、
３はウェーハ支持部、
４はディスク（Ａβ）、
５はウェーハバッド、
６は支持部材、
６ａは支持部材基部（Ａ Ｎ ’）、
６ｂは支持部材先端部（表面５ｉＣ）、７ａ、 ７ｂは
給電部材（先端部５ｉＣ）、８は半導体化合物膜、
ＷはＳｉウェーハ、
Ｐはプラズマ、
ＩＢはイオンビーム、
である。FIG. 1 is a side sectional view for explaining the example, (al is the time of semiconductor compound film formation, fb is the time of wafer support, and FIG. 2 is the arrangement of the wafer support part in the processing equipment to which the example is applied. This is a side sectional view (not shown). In the figure, 1 is an ion implanter, 2 is an end station, 3 is a wafer support part, 4 is a disk (Aβ), 5 is a wafer pad, 6 is a support member, 6a is a support member base (AN'), 6b is a 7a and 7b are power feeding members (front end 5iC), 8 is a semiconductor compound film, W is a Si wafer, P is plasma, and IB is an ion beam.
Claims (1)
支持するに際して、該ウェーハ表面の前記当接箇所を含
む局部領域に該ウェーハの半導体を反応させた半導体化
合物膜を形成してから、該支持部材を当接することを特
徴とする半導体ウェーハ支持方法。 ２）前記半導体化合物膜は、前記ウェーハの支持終了後
にエッチング除去することを特徴とする請求項１記載の
半導体ウェーハ支持方法。 ３）前記半導体化合物膜は、前記ウェーハに前記支持部
材を当接する直前に、該化合物膜の構成元素を含む雰囲
気で、該ウェーハと該支持部材との間にプラズマ放電を
起こさせて形成することを特徴とする請求項１または２
記載の半導体ウェーハ支持方法。 ４）前記プラズマ放電は、減圧中の直流放電であり、前
記ウェーハを負側とすることを特徴とする請求項３記載
の半導体ウェーハ支持方法。 ５）前記半導体ウェーハはシリコンウェーハであり、前
記半導体化合物膜はシリコン酸化膜またはシリコン窒化
膜であることを特徴とする請求項１、２、３または４記
載の半導体ウェーハ支持方法。 ６）前記支持部材の表面は、シリコンまたは導電性のシ
リコン化合物であることを特徴とする請求項５記載の半
導体ウェーハ支持方法。[Claims] 1) When a supporting member is brought into contact with a semiconductor wafer to support the wafer, a semiconductor compound film made by reacting the semiconductor of the wafer is formed in a local region of the wafer surface including the contact point. A method for supporting a semiconductor wafer, comprising: then abutting the supporting member. 2) The semiconductor wafer supporting method according to claim 1, wherein the semiconductor compound film is removed by etching after the wafer is supported. 3) The semiconductor compound film is formed by causing plasma discharge between the wafer and the support member in an atmosphere containing constituent elements of the compound film immediately before the support member is brought into contact with the wafer. Claim 1 or 2 characterized by
The semiconductor wafer support method described. 4) The method for supporting a semiconductor wafer according to claim 3, wherein the plasma discharge is a direct current discharge under reduced pressure, and the wafer is on the negative side. 5) The semiconductor wafer supporting method according to claim 1, 2, 3, or 4, wherein the semiconductor wafer is a silicon wafer, and the semiconductor compound film is a silicon oxide film or a silicon nitride film. 6) The semiconductor wafer supporting method according to claim 5, wherein the surface of the supporting member is made of silicon or a conductive silicon compound.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2122483A JPH0418744A (en) | 1990-05-11 | 1990-05-11 | Support for semiconductor wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2122483A JPH0418744A (en) | 1990-05-11 | 1990-05-11 | Support for semiconductor wafer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0418744A true JPH0418744A (en) | 1992-01-22 |
Family
ID=14836968
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2122483A Pending JPH0418744A (en) | 1990-05-11 | 1990-05-11 | Support for semiconductor wafer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0418744A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100233995B1 (en) * | 1996-12-11 | 1999-12-15 | 전주범 | Thin film actuated mirror array and its fabrication method |
-
1990
- 1990-05-11 JP JP2122483A patent/JPH0418744A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100233995B1 (en) * | 1996-12-11 | 1999-12-15 | 전주범 | Thin film actuated mirror array and its fabrication method |
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