JPH04179311A - Level conversion circuit - Google Patents
Level conversion circuitInfo
- Publication number
- JPH04179311A JPH04179311A JP2307656A JP30765690A JPH04179311A JP H04179311 A JPH04179311 A JP H04179311A JP 2307656 A JP2307656 A JP 2307656A JP 30765690 A JP30765690 A JP 30765690A JP H04179311 A JPH04179311 A JP H04179311A
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- power supply
- whose
- resistor
- output terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000006243 chemical reaction Methods 0.000 title claims description 26
- 239000003990 capacitor Substances 0.000 claims abstract description 39
- 101100286980 Daucus carota INV2 gene Proteins 0.000 abstract description 9
- 101100397045 Xenopus laevis invs-b gene Proteins 0.000 abstract description 9
- 238000010586 diagram Methods 0.000 description 5
- VNDWQCSOSCCWIP-UHFFFAOYSA-N 2-tert-butyl-9-fluoro-1,6-dihydrobenzo[h]imidazo[4,5-f]isoquinolin-7-one Chemical compound C1=2C=CNC(=O)C=2C2=CC(F)=CC=C2C2=C1NC(C(C)(C)C)=N2 VNDWQCSOSCCWIP-UHFFFAOYSA-N 0.000 description 2
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はレベル変換回路に関し、特にパルス状の信号に
よりＦＥＴ等を駆動するために必要な入力振幅を越える
駆動振幅を得るレベル変換回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a level conversion circuit, and more particularly to a level conversion circuit that obtains a driving amplitude that exceeds the input amplitude necessary for driving an FET or the like using a pulsed signal.
第５図は従来のレベル変換回路の一例を示す回路図であ
る。本例はアクティブロー入力、アクティブハイ出力の
場合を示しており、第１の直流電源３１と、インバータ
３２と、レベル変換回路３３と、プルアップ抵抗３４と
、第２の直流電源３５とから構成されている。FIG. 5 is a circuit diagram showing an example of a conventional level conversion circuit. This example shows the case of active low input and active high output, and is composed of a first DC power supply 31, an inverter 32, a level conversion circuit 33, a pull-up resistor 34, and a second DC power supply 35. has been done.
上述した従来のレベル変換回路では、インバータ３２用
の直流電源３１の電圧を■１．レベル変換回路３３用の
直流電源３５の電圧をＶ２とすると、ＶｌくＶ２でなけ
ればならない。In the conventional level conversion circuit described above, the voltage of the DC power supply 31 for the inverter 32 is changed to 1. If the voltage of the DC power supply 35 for the level conversion circuit 33 is V2, it must be V1 minus V2.
すなわち、レベル変換回路３３用の大電圧の直流電源３
５（例えばＶ２ ＝ ３ Ｖｔ ）が、第１の直流電源
３１とは別に必要となるという欠点がある。That is, the high voltage DC power supply 3 for the level conversion circuit 33
5 (for example, V2 = 3 Vt) is required separately from the first DC power supply 31.
第１の発明のレベル変換回路は、パルス状のアクティブ
ロー入力を受けて入力振幅を越えるアクティブハイ出力
振幅を得るレベル変換回路において、直流電源と、正極
電源端子が前記直流電源の正極端子に接続され且つ負極
電源端子が前記直流電源の負極端子に接続されたインバ
ータと、一端か前記直流電源の正極端子に接続され且つ
他端が前記インバータの入力端子に接続された第１の抵
抗と、アノードが前記直流電源の正極端子に接続された
第１のダイオードと、正極端子が前記第１のダイオード
のカソードに接続され且つ負極端子が前記インバータの
出力端子に接続された第１のコンデンサと、正極電源端
子が前記直流電源の正極端子に接続され且つ負［ｉ電源
端子が前記直流電源の負極端子に接続されたコンパレー
タと、一端が前記第１のコンデンサの正極端子に接続さ
れ且つ他端が前記コンパレータの反転入力端子に接続さ
れた第２の抵抗と、一端が前記コンパレータの反転入力
端子に接続され且つ他端が前記直流電源の負極端子に接
続された第３の抵抗と、一端が前記直流電源の正極端子
に接続され且つ他端が前記コンパレータの非反転入力端
子に接続された第４の抵抗と、一端が前記コンパレータ
の非反転入力端子に接続され且つ他端が前記直流電源の
負極端子に接続された第５の抵抗と、正極端子が前記コ
ンパレータの出力端子に接続された第２のコンデンサと
、アノードが前記第２のコンデンサの負極端子に接続さ
れ且つカソードが前記直流電源の負極端子に接続された
第２のダイオードと、エミッタか前記第１のコンデンサ
の正極端子に接続されたＰＮＰトランジスタと、一端が
前記コンパレータの出力端子に接続され且つ他端が前記
ＰＮＰ トランジスタのベースに接続された第６の抵抗
と、一端が前記ＰＮＰトランジスタのコレクタに接続さ
れ且つ他端が出力端子に接続された第７の抵抗と、エミ
ッタが前記直流電源の負極端子に接続された第１のＮＰ
Ｎトランジスタと、一端が前記コンパレータの出力端子
に接続され且っ他端が前記第１のＮＰＮトランジスタの
ベースに接続された第８の抵抗と、一端が前記出力端子
に接続され且つ他端が前記第１のＮＰＮトランジスタの
コレクタに接続された第９の抵抗と、コレクタが出力端
子（基準）に接続され且つエミッタが前記第２のコンデ
ンサの負極端子に接続された第２のＮＰＮトランジスタ
と、一端が前記インバータの出力端子に接続され且つ他
端が前記第２のＮＰＮＩ−ランジスタのベースに接続さ
れた第１０の抵抗と、コレクタが前記出力端子（基準）
に接続され且つエミッタが前記直流電源の負極端子に接
続された第３のＮＰＮトランジスタと、一端が前記コン
パレータの出力端子に接続され且つ他端が前記第３のＮ
ＰＮトランジスタのベースに接続された第１１の抵抗と
から構成されることを特徴とする。A level conversion circuit according to a first aspect of the present invention is a level conversion circuit that receives a pulsed active low input and obtains an active high output amplitude that exceeds the input amplitude. an inverter having a negative power terminal connected to the negative terminal of the DC power supply; a first resistor having one end connected to the positive terminal of the DC power supply and the other end connected to the input terminal of the inverter; and an anode. a first diode whose positive terminal is connected to the positive terminal of the DC power source; a first capacitor whose positive terminal is connected to the cathode of the first diode and whose negative terminal is connected to the output terminal of the inverter; a comparator having a power supply terminal connected to the positive terminal of the DC power supply and a negative terminal connected to the negative terminal of the DC power supply; a second resistor connected to the inverting input terminal of the comparator; a third resistor having one end connected to the inverting input terminal of the comparator and the other end connected to the negative terminal of the DC power supply; a fourth resistor connected to the positive terminal of the power supply and whose other end is connected to the non-inverting input terminal of the comparator; and a fourth resistor whose one end is connected to the non-inverting input terminal of the comparator and whose other end is the negative terminal of the DC power supply. a second capacitor having a positive terminal connected to the output terminal of the comparator; an anode connected to the negative terminal of the second capacitor and a cathode connected to the negative terminal of the DC power supply; a PNP transistor whose emitter is connected to the positive terminal of the first capacitor, one end of which is connected to the output terminal of the comparator, and the other end of which is connected to the base of the PNP transistor. a seventh resistor having one end connected to the collector of the PNP transistor and the other end connected to the output terminal; and a first NP transistor having an emitter connected to the negative terminal of the DC power supply.
an eighth resistor having one end connected to the output terminal of the comparator and the other end connected to the base of the first NPN transistor; one end connected to the output terminal and the other end connected to the base of the first NPN transistor; a ninth resistor connected to the collector of the first NPN transistor; a second NPN transistor whose collector is connected to the output terminal (reference) and whose emitter is connected to the negative terminal of the second capacitor; is connected to the output terminal of the inverter, and the other end is connected to the base of the second NPNI transistor, and the collector is connected to the output terminal (reference).
a third NPN transistor whose emitter is connected to the negative terminal of the DC power source, and whose one end is connected to the output terminal of the comparator and whose other end is connected to the third NPN transistor
and an eleventh resistor connected to the base of the PN transistor.
また、第２の発明のレベル変換回路は、パルス状のアク
ティブロー入力を受けて入力振幅を越えるアクティブハ
イ出力振幅を得るレベル変換回路において、直流電源と
、正極電源端子が前記直流電源の正極端子に接続され且
つ負極電源端子が前記直流電源の負極端子に接続された
インバータと、一端が前記直流電源の正極端子に接続さ
れ且つ他端が前記インバータの入力端子に接続された第
１の抵抗と、アノードが前記直流電源の正極端子に接続
された第１のダイオードと、正極端子が前記第１のダイ
オードのカソードに接続され且つ負極端子が前記インバ
ータの出力端子に接続された第１のコンデンサと、正極
電源端子が前記直流電源の正極端子に接続され且つ負８
ｉｉ電源端子が前記直流電源の負極端子に接続され且つ
反転入力端子が前記インバータの出力端子に接続された
コンパレータと、一端が前記直流電源の正極端子に接続
され且つ他端が前記コンパレータの非反転入力端子に接
続された第２の抵抗と、一端が前記コンパレータの非反
転入力端子に接続され且つ他端が前記直流電源の負極端
子に接続された第３の抵抗と、正極端子が前記コンパレ
ータの出力端子に接続された第２のコンデンサと、アノ
ードが前記第２のコンデンサの負極端子に接続され且つ
カソードが前記直流電源の負極端子に接続された第２の
ダイオードと、エミッタが前記第１のコンデンサの正極
端子に接続されたＰＮＰ トランジスタと、一端が前記
コンパレータの出力端子に接続され且つ他端が前記ＰＮ
Ｐ トランジスタのベースに接続された第４の抵抗と、
一端か前記ＰＮＰ トランジスタのコレクタに接続され
且つ他端が出力端子に接続された第５の抵抗と、エミッ
タが前記直流電源の負極端子に接続された第１のＮＰＮ
トランジスタと、一端が前記コンパレータの出力端子に
接続され且つ他端が前記第１のＮＰＮトランジスタのベ
ースに接続された第６の抵抗と、一端が前記出力端子に
接続され且つ他端が前記第１のＮＰＮトランジスタのコ
レクタに接続された第７の抵抗と、コレクタが出力端子
（基準）に接続され且つエミッタが前記第２のコンデン
サの負極端子に接続された第２のＮＰＮトランジスタと
、一端が前記インバータの出力端子に接続され且つ他端
が前記第２のＮＰＮトランジスタのベースに接続された
第８の抵抗と、コレクタが前記出力端子（基準）に接続
され且つエミッタが前記直流電源の負極端子に接続され
た第３のＮＰＮトランジスタと、−端が前記コンパレー
タの出力端子に接続され且つ他端が前記第３のＮＰＮト
ランジスタのベースに接続された第９の抵抗とから構成
されることを特徴とする。A level conversion circuit according to a second aspect of the invention is a level conversion circuit that receives a pulsed active low input and obtains an active high output amplitude exceeding the input amplitude, wherein a DC power source and a positive power terminal are connected to the positive terminal of the DC power source. and a first resistor having one end connected to the positive terminal of the DC power supply and the other end connected to the input terminal of the inverter. , a first diode whose anode is connected to the positive terminal of the DC power supply, and a first capacitor whose positive terminal is connected to the cathode of the first diode and whose negative terminal is connected to the output terminal of the inverter. , the positive power terminal is connected to the positive terminal of the DC power supply, and the negative 8
ii a comparator having a power supply terminal connected to the negative terminal of the DC power supply and an inverting input terminal connected to the output terminal of the inverter; and a comparator having one end connected to the positive terminal of the DC power supply and the other end of the comparator a second resistor connected to the input terminal; a third resistor having one end connected to the non-inverting input terminal of the comparator and the other end connected to the negative terminal of the DC power supply; and a third resistor having a positive terminal connected to the non-inverting input terminal of the comparator. a second capacitor connected to the output terminal; a second diode having an anode connected to the negative terminal of the second capacitor and a cathode connected to the negative terminal of the DC power supply; A PNP transistor connected to the positive terminal of the capacitor, one end connected to the output terminal of the comparator, and the other end connected to the PN transistor.
a fourth resistor connected to the base of the P transistor;
a fifth resistor having one end connected to the collector of the PNP transistor and the other end connected to the output terminal; and a first NPN resistor having an emitter connected to the negative terminal of the DC power supply.
a sixth resistor having one end connected to the output terminal of the comparator and the other end connected to the base of the first NPN transistor; one end connected to the output terminal and the other end connected to the first NPN transistor; a second NPN transistor whose collector is connected to the output terminal (reference) and whose emitter is connected to the negative terminal of the second capacitor; an eighth resistor connected to the output terminal of the inverter and the other end connected to the base of the second NPN transistor; a collector connected to the output terminal (reference) and an emitter connected to the negative terminal of the DC power supply; and a ninth resistor whose negative end is connected to the output terminal of the comparator and whose other end is connected to the base of the third NPN transistor. do.
さらに、第３の発明のレベル変換回路は、パルス状のア
クティブロー入力を受けて入力振幅を越えるアクティブ
ハイ出力振幅を得るレベル変換回路において、直流電源
と、正極電源端子が前記直流電源の正極端子に接続され
且つ負極電源端子か前記直流電源の負極端子に接続され
た第１のインバータと、一端が前記直流電源の正極端子
に接続され且つ他端が前記第１のインバータの入力端子
に接続された第１の抵抗と、アノードが前記直流電源の
正極端子に接続された第１のダイオードと、正極端子が
前記第１のダイオードのカソードに接続され且つ負極端
子が前記第１のインバータの出力端子に接続された第１
のコンデンサと、正極電源端子が前記直流電源の正極端
子に接続され且つ負極電源端子が前記直流電源の負極端
子に接続され且つ入力端子が前記第１のインバータの出
力端子に接続された第２のインバータと、正極端子が前
記第２のインバータの出力端子に接続された第２のコン
デンサと、アノードが前記第２のコンデンサの負極端子
に接続され且つカソードが前記直流電源の負極端子に接
続された第２のダイオードと、エミッタが前記第１のコ
ンデンサの正極端子に接続されたＰＮＰトランジスタと
、一端か前記第２のインバータの出力端子に接続され且
つ他端が前記ＰＮＰトランジスタのベースに接続された
第２の抵抗と、一端が前記ＰＮＰ トランジスタのコレ
クタに接続され且つ他端か出力端子に接続された第３の
抵抗と、エミッタが前記直流電源の負極端子に接続され
た第１のＮＰＮＩ−ランシスタと、一端が前記第２のイ
ンバータの出力端子に接続され且つ他端が前記第１のＮ
ＰＮトランジスタのベースに接続された第４の抵抗と、
一端が前記出力端子に接続され且つ他端が前記第１のＮ
ＰＮトランジスタのコレクタに接続された第５の抵抗と
、コレクタが出力端子（基準）に接続され且つエミッタ
が前記第２のコンデンサの負極端子に接続された第２の
ＮＰＮトランジスタと、−端が前記第１のインバータの
出力端子に接続され且つ他端が前記第２のＮＰＮトラン
ジスタのベースに接続された第６の抵抗と、コレクタが
前記出力端子（基準）に接続され且つエミッタが前記直
流電源の負極端子に接続された第３のＮＰＮトランジス
タと、一端が前記第２のインバータの出力端子に接続さ
れ且つ他端が前記第３のＮＰＮトランジスタのベースに
接続された第７の抵抗とから構成されることを特徴とす
る。Furthermore, a level conversion circuit according to a third aspect of the present invention is a level conversion circuit that receives a pulsed active low input and obtains an active high output amplitude that exceeds the input amplitude. and a first inverter connected to a negative power terminal or a negative terminal of the DC power supply, and a first inverter having one end connected to the positive terminal of the DC power supply and the other end connected to an input terminal of the first inverter. a first diode whose anode is connected to the positive terminal of the DC power supply; a positive terminal whose positive terminal is connected to the cathode of the first diode and whose negative terminal is connected to the output terminal of the first inverter; the first connected to
a second capacitor whose positive power supply terminal is connected to the positive terminal of the DC power supply, whose negative power supply terminal is connected to the negative terminal of the DC power supply, and whose input terminal is connected to the output terminal of the first inverter. an inverter, a second capacitor having a positive terminal connected to the output terminal of the second inverter, an anode connected to the negative terminal of the second capacitor, and a cathode connected to the negative terminal of the DC power supply. a second diode, a PNP transistor whose emitter is connected to the positive terminal of the first capacitor, and one end connected to the output terminal of the second inverter and the other end connected to the base of the PNP transistor. a second resistor, a third resistor whose one end is connected to the collector of the PNP transistor and whose other end is connected to the output terminal; and a first NPNI-Ransistor whose emitter is connected to the negative terminal of the DC power supply. , one end is connected to the output terminal of the second inverter, and the other end is connected to the first N inverter.
a fourth resistor connected to the base of the PN transistor;
one end is connected to the output terminal, and the other end is connected to the first N
a fifth resistor connected to the collector of the PN transistor; a second NPN transistor whose collector is connected to the output terminal (reference) and whose emitter is connected to the negative terminal of the second capacitor; a sixth resistor connected to the output terminal of the first inverter and the other end connected to the base of the second NPN transistor; a sixth resistor having a collector connected to the output terminal (reference) and an emitter connected to the DC power source; a third NPN transistor connected to a negative terminal; and a seventh resistor, one end of which is connected to the output terminal of the second inverter, and the other end of which is connected to the base of the third NPN transistor. It is characterized by
次に、本発明について第１図〜第４図を参照して説明す
る。Next, the present invention will be explained with reference to FIGS. 1 to 4.
第１図、第２図、第３図はそれぞれ第１．第２゜第３の
発明のレベル変換回路の一実施例を示す回路図、第４図
（ａ＞、（ｂ）はそれぞれ第１図〜第３図における入力
端子が“ハイ″、“ロー′°の場合の回路動作概要を説
明するための等価回路図である。Figures 1, 2 and 3 are respectively 1. 2. A circuit diagram showing an embodiment of the level conversion circuit of the third invention, FIG. 4 (a>, (b)) shows that the input terminals in FIGS. 3 is an equivalent circuit diagram for explaining an outline of circuit operation in the case of .degree.; FIG.
第１図に示す第１の発明の一実施例のレベル変換回路は
、直流電源（以下Ｅ）１と、正極電源端子がＥｌの正極
端子に接続され且つ負極電源端子がＥｌのｊｌ極端子に
接続されたインバータ（以下ＩＮＶ）２と、一端がＥｌ
の正極端子に接続され且つ他端がＩＮＶ２の入力端子に
接続された第１の抵抗（以下ＲＡ）３と、アノードがＥ
ｌの正極端子に接続された第１のダイオード（以下ＤＡ
＞４と、正極端子（＋）がＤＡ４のカソードに接続され
且つ負極端子がＩＮＶ２の出力端子に接続された第１の
コンデンサ（以下ＣＡ）５と、正極電源端子がＥｌの正
極端子に接続され且つ負極電源端子がＥｌの負極端子に
接続されたコンパレータ（以下ＣＭＰ）６と、一端がＣ
Ａ５の正極端子（＋）に接続され且つ他端がＣＭＰ６の
反転入力端子（−）に接続された第２の抵抗く以下ＲＢ
）７と、一端がＣＭＰ６の反転入力端子（−）に接続さ
れ且つ他端がＥｌの負極端子に接続された第３の抵抗（
以下Ｒｃ）８と、一端がＥｌの正極端子に接続され且つ
他端がコンパレータ６の非反転入力端子（＋）に接続さ
れた第４の抵抗（以下Ｒｏ）９と、一端がＣＭ Ｐ ６
の非反転入力端子（＋）に接続され且つ他端がＥｌの負
極端子に接続された第５の抵抗（以下ＲＥ）１０と、正
極端子がＣＭＰ６の出力端子に接続された第２のコンデ
ンサ〈以下ＣＢ＞１１と、アノードがＣＢ１１の負極端
子に接続され且つカソードがＥｌの負極端子に接続され
た第２のダイオード〈以下ＤＢ）１２と、エミッタがＣ
Ａ５の正極端子（＋）に接続されたＰＮＰトランジスタ
（以下Ｑｐ）１３と、一端かＣＭＰ６の出力端子に接続
され且っ他端かＱｐ１３のベースに接続された第６の抵
抗（以下Ｒｐ）１４と、一端がＱｐ１３のコレクタに接
続され且つ他端が出力端子１５に接続された第７の抵抗
（以下Ｒ６）１６と、エミッタがＥｌの負極端子に接続
された第１のＮＰＮトランジスタ（以下ＱＮＡ）１７と
、一端がＣＭＰ６の出力端子に接続され且つ他端がＱＮ
Ａ１７のベースに接続された第８の抵抗（以下Ｒ）り１
８と、一端が出力端子１５に接続され且っ他端がＱＮＡ
１７のコレクタに接続された第９の抵抗（以下Ｒ＋）１
９と、コレクタが出力端子（基準）２０に接続され且つ
エミッタがＣＢＩＩの負極端子に接続された第２のＮＰ
Ｎトランジスタ（以下ＱＮＢ）２１と、一端かＩＮＶ２
の出力端子に接続され且つ他端がＱＮＢ２１のベースに
接続された第１０の抵抗（以下ＲＪ）２２と、コレクタ
が出力端子（基準ン２０に接続され且つエミッタがＥｌ
の負極端子に接続された第３のＮＰＮトランジスタ（以
下ＱＮＣ）２３と、一端がＣＭＰ６の出力端子に接続さ
れ且つ他端がＱＮＣ２３のベースに接続された第１１の
抵抗（以下Ｒｘ）２４とから構成される。The level conversion circuit according to the embodiment of the first invention shown in FIG. 1 includes a DC power supply (hereinafter referred to as E) 1, a positive power supply terminal connected to the positive terminal of El, and a negative power supply terminal connected to the jl terminal of El. Connected inverter (hereinafter referred to as INV) 2 and one end connected to El
A first resistor (hereinafter referred to as RA) 3 connected to the positive terminal of INV2 and the other end connected to the input terminal of INV2, and an anode of E
The first diode (hereinafter referred to as DA) connected to the positive terminal of
>4, a first capacitor (hereinafter referred to as CA) 5 whose positive terminal (+) is connected to the cathode of DA4 and whose negative terminal is connected to the output terminal of INV2, and whose positive power supply terminal is connected to the positive terminal of El. In addition, a comparator (hereinafter referred to as CMP) 6 whose negative power supply terminal is connected to the negative terminal of El, and one end connected to CMP
The second resistor RB is connected to the positive terminal (+) of A5 and the other end is connected to the inverting input terminal (-) of CMP6.
) 7, and a third resistor (
A fourth resistor (hereinafter referred to as Ro) 9 whose one end is connected to the positive terminal of El and whose other end is connected to the non-inverting input terminal (+) of the comparator 6;
A fifth resistor (hereinafter referred to as RE) 10 whose other end is connected to the non-inverting input terminal (+) of El and whose other end is connected to the negative terminal of El, and a second capacitor < whose positive terminal is connected to the output terminal of CMP6. Hereinafter, CB>11, a second diode (hereinafter referred to as DB) 12 whose anode is connected to the negative terminal of CB11 and whose cathode is connected to the negative terminal of El, and an emitter of C
A PNP transistor (hereinafter referred to as Qp) 13 connected to the positive terminal (+) of A5, and a sixth resistor (hereinafter referred to as Rp) 14 connected at one end to the output terminal of CMP6 and at the other end to the base of Qp13. , a seventh resistor (hereinafter R6) 16 whose one end is connected to the collector of Qp13 and the other end is connected to the output terminal 15, and a first NPN transistor (hereinafter referred to as QNA) whose emitter is connected to the negative terminal of El. )17, one end is connected to the output terminal of CMP6, and the other end is connected to QN.
The eighth resistor (hereinafter referred to as R) connected to the base of A17
8, one end is connected to the output terminal 15, and the other end is connected to the QNA
The ninth resistor (hereinafter referred to as R+) connected to the collector of 17
9 and a second NP whose collector is connected to the output terminal (reference) 20 and whose emitter is connected to the negative terminal of CBII.
N transistor (hereinafter referred to as QNB) 21 and one end or INV2
A tenth resistor (RJ) 22 whose collector is connected to the output terminal (reference terminal 20) and whose other end is connected to the base of QNB 21 and whose emitter is connected to El
A third NPN transistor (hereinafter referred to as QNC) 23 connected to the negative terminal of the CMP 6, and an eleventh resistor (hereinafter referred to as Rx) 24 whose one end is connected to the output terminal of the CMP 6 and the other end is connected to the base of the QNC 23. configured.
次に、本実施例の動作について説明する。Next, the operation of this embodiment will be explained.
第４図（ａ）、（ｂ）に示されたスイッチ２Ａ１６Ａ、
１３Ａ、１７Ａ、２１Ａ、２３Ａはそれぞれ便宜上第１
図におけるＩＮＶ２．ＣＭＰ６の出力部、 Ｑｐ １３
． ＱｓＡｌ ７． ＱＮＢ２１ 、 ＱＮＣ２３を等
価的に！き換えたものである。Switch 2A16A shown in FIGS. 4(a) and (b),
13A, 17A, 21A, and 23A are number 1 for convenience.
INV2 in the figure. CMP6 output section, Qp 13
．． QsAl7. QNB21 and QNC23 are equivalent! It has been replaced.
まず第４図（ａ）の場合（第１図における入力端子２５
が“ハイ′°の場合に対応）を考えると、出力端子１５
及び出力端子（基準＞２０にはいずれも入力端子２６と
同電位か出力される。すなわちこのとき出力端子１５は
出力端子（基準）２０に対し同電位となる。なおこのと
きＣＡ５とＣＢ１１はＥｌの電圧（＝Ｖ、）に充電され
る。ただし、ＤＡ４とＤＢ１２での順方向電圧降下等の
損失を無視するものとする。First, in the case of FIG. 4(a) (input terminal 25 in FIG.
is “high”), the output terminal 15
and the output terminal (reference > 20) are both output at the same potential as the input terminal 26. That is, at this time, the output terminal 15 is at the same potential as the output terminal (reference) 20. At this time, CA5 and CB11 are at El is charged to a voltage (=V).However, losses such as forward voltage drop at DA4 and DB12 are ignored.
次に、第４図（ｂ）の場合（第１図における入力端子２
５が゛″ローの場合に対応）を考えると、出力端子１５
には出力端子（基準）２０を基準としたとき、Ｃａ１ｌ
の電圧（−Ｖ＋）とＥｌの電圧（”ｖｔ）とＣＡうの電
圧（−ｖｌ）の和としての電圧＜”３Ｖ＋ ）が出力さ
れる。ただしＤＡ４とＤＢ１２の逆方向リーク電流等に
よるＣＡ５とＣａ１ｌの放電等の損失を無視するものと
する。Next, in the case of FIG. 4(b) (input terminal 2 in FIG.
5 is "low"), output terminal 15
When the output terminal (reference) 20 is used as a reference, Ca1l
A voltage (<3V+) as the sum of the voltage (-V+), the voltage (vt) of El, and the voltage (-vl) of CA is output. However, losses such as discharge of CA5 and Ca1l due to reverse leakage current of DA4 and DB12 are ignored.
以上の動作によりアクティブローのパルス状の入力信号
が第１図の入力端子２５に入−力された場合、出力端子
１５には出力端子（基準）２０に対してＩＮＶ２及びＣ
ＭＰ６の電源電圧（”Ｖ＋）の３倍の振幅を有するパル
ス電圧が単一電源により実現可能となる。With the above operation, when an active low pulse input signal is input to the input terminal 25 in FIG. 1, the output terminal 15 has INV2 and C
A pulse voltage having an amplitude three times that of the MP6 power supply voltage (V+) can be realized by a single power supply.
次に、第２の発明の一実施例を示した第２図において、
第１の発明の一実施例と同じ構成要件には第１図と同じ
符号を付しである。すなわち本実施例のレベル変換回路
は第１図に示した実施例からＲｅ７およびＲ６８を削除
し、ＣＭＰ６の反転入力端子（−）をＣＡ５の負極端子
に接続した点か第１の発明の一実施例と異なっており、
他の構成は同じである。従って第２の発明の一実施例は
第４図＜ａ）、（ｂ）によって説明した第１の発明の一
実施例と同じ動作を行い、同等の効果を有する。Next, in FIG. 2 showing an embodiment of the second invention,
Components that are the same as those in the embodiment of the first invention are given the same reference numerals as in FIG. That is, the level conversion circuit of this embodiment is an implementation of the first invention in that Re7 and R68 are removed from the embodiment shown in FIG. 1, and the inverting input terminal (-) of CMP6 is connected to the negative terminal of CA5. It is different from the example,
Other configurations are the same. Therefore, the embodiment of the second invention performs the same operation as the embodiment of the first invention explained with reference to FIGS. 4(a) and 4(b), and has the same effect.
次に、第３の発明の一実施例を示した第３図において、
第１の発明の一実施例と同じ構成要件には第１図と同じ
符号を付しである。すなわち本実施例のレベル変換回路
は第１図に示した実施例がらＲＢ ７．Ｒｅ ８．Ｒｏ
９．ＲＥ １０を削除するとともにＣＭＰ６をＩＮＶ
６６に置き換え、ＩＮＶ６６の入力端子をＣＡ５の負極
端子に接続した点が第１の発明の一実施例との相違点で
ある。従って、第４図（ａ）、（ｂ）におけるスイッチ
２Ａ、６Ａ、１３Ａ、１７Ａ、２１Ａ。Next, in FIG. 3 showing an embodiment of the third invention,
Components that are the same as those in the embodiment of the first invention are given the same reference numerals as in FIG. That is, the level conversion circuit of this embodiment is different from the embodiment shown in FIG. Re 8. Ro
9. Delete RE 10 and INV CMP6
The difference from the embodiment of the first invention is that the input terminal of INV66 is connected to the negative terminal of CA5. Therefore, the switches 2A, 6A, 13A, 17A, 21A in FIGS. 4(a) and 4(b).
２３Ａはそれぞれ便宜上第３図におけるＩＮＶ２゜６６
の出力部、 Ｑｐ １ Ｂ 、 ＱＮＡＩ ７ 、 Ｑ
ＮＢ２１ 。23A is INV2゜66 in Fig. 3 for convenience.
The output part of Qp 1 B , QNAI 7 , Q
NB21.
ＱＮＣ２３を等価的に置き換えたものとすれば、第３の
発明の一実施例は第４図（ａ）、（ｂ）によって説明し
た第１の発明の一実施例と同じ動作を行い、同等の効果
を有する。If the QNC23 is equivalently replaced, an embodiment of the third invention performs the same operation as an embodiment of the first invention explained using FIGS. 4(a) and (b), and has the same have an effect.
以上説明したように第１．第２の発明はインバータ、コ
ンパレータ、ダイオードを介して、また第３の発明はイ
ンハ゛−タ、ダイオードを介して充電されるコンデンサ
等を用いることにより、単一直流電源を用いてその電圧
の３倍の振幅を有するパルス出力が得られるという効果
がある。As explained above, the first. The second invention uses an inverter, a comparator, and a diode, and the third invention uses a capacitor, etc. that is charged via an inverter and a diode. This has the effect that a pulse output having an amplitude of .
第１図、第２図、第３図はそれぞれ第１．第２゜第３の
発明のレベル変換回路の一実施例を示す回路図、第４図
（ａ）、（ｂ）はそれぞれ第１図〜第３図における入力
端子が゛″ハイパ“ロー″の場合の回路動作概要を説明
するための等価回路図、第５図は従来のレベル変換回路
の一例を示す回路図である。
１・・・直流電源（Ｅ）、２．６６・・・インバータ（
ＩＮＶ）、３，７，８，９，１０，１４，１６゜１８．
１９．２２．２４・・・抵抗（ＲＡ、ＲＢ。
Ｒｅ、Ｒｏ、Ｒｔ、ＲＦ、ＲＧ、ＲＨ，Ｒ＋ 。
ＲＪ 、Ｒに）、４．１２・・・ダイオード（ＤＡ。
Ｄｓ）５．１１・・・コンデンサ（ＣＡ 、 Ｃａ ）
、６、・・コンパレータ（ＣＭＰ）、１Ｂ・・・ＰＮ
Ｐ トランジスタ（Ｑｐ ） 、１７，２１．２３・・
・ＮＰＮトランジスタ（ＱＮ＾、 ＱＮＢ、 ＱＮＣ）
、１５−出力端子、２０・・・出力端子（基準）、２
５・・・入力端子、２６・・・入力端子（基準）。Figures 1, 2 and 3 are respectively 1. 4(a) and 4(b) are circuit diagrams showing an embodiment of the level conversion circuit of the second and third inventions, respectively, in which the input terminals in FIGS. 1 to 3 are "hyper" and "low". FIG. 5 is a circuit diagram showing an example of a conventional level conversion circuit. 1... DC power supply (E), 2.66... Inverter (
INV), 3, 7, 8, 9, 10, 14, 16°18.
19.22.24...Resistance (RA, RB. Re, Ro, Rt, RF, RG, RH, R+. RJ, R), 4.12... Diode (DA. Ds) 5.11.・Capacitor (CA, Ca)
, 6,... Comparator (CMP), 1B...PN
P transistor (Qp), 17, 21.23...
・NPN transistor (QN^, QNB, QNC)
, 15-output terminal, 20...output terminal (reference), 2
5... Input terminal, 26... Input terminal (reference).
Claims (1)
越えるアクティブハイ出力振幅を得るレベル変換回路に
おいて、直流電源と、正極電源端子が前記直流電源の正
極端子に接続され且つ負極電源端子が前記直流電源の負
極端子に接続されたインバータと、一端が前記直流電源
の正極端子に接続され且つ他端が前記インバータの入力
端子に接続された第１の抵抗と、アノードが前記直流電
源の正極端子に接続された第１のダイオードと、正極端
子が前記第１のダイオードのカソードに接続され且つ負
極端子が前記インバータの出力端子に接続された第１の
コンデンサと、正極電源端子が前記直流電源の正極端子
に接続され且つ負極電源端子が前記直流電源の負極端子
に接続されたコンパレータと、一端が前記第１のコンデ
ンサの正極端子に接続され且つ他端が前記コンパレータ
の反転入力端子に接続された第２の抵抗と、一端が前記
コンパレータの反転入力端子に接続され且つ他端が前記
直流電源の負極端子に接続された第３の抵抗と、一端が
前記直流電源の正極端子に接続され且つ他端が前記コン
パレータの非反転入力端子に接続された第４の抵抗と、
一端が前記コンパレータの非反転入力端子に接続され且
つ他端が前記直流電源の負極端子に接続された第５の抵
抗と、正極端子が前記コンパレータの出力端子に接続さ
れた第２のコンデンサと、アノードが前記第２のコンデ
ンサの負極端子に接続され且つカソードが前記直流電源
の負極端子に接続された第２のダイオードと、エミッタ
が前記第１のコンデンサの正極端子に接続されたＰＮＰ
トランジスタと、一端が前記コンパレータの出力端子に
接続され且つ他端が前記ＰＮＰトランジスタのベースに
接続された第６の抵抗と、一端が前記ＰＮＰトランジス
タのコレクタに接続され且つ他端が出力端子に接続され
た第７の抵抗と、エミッタが前記直流電源の負極端子に
接続された第１のＮＰＮトランジスタと、一端が前記コ
ンパレータの出力端子に接続され且つ他端が前記第１の
ＮＰＮトランジスタのベースに接続された第８の抵抗と
、一端が前記出力端子に接続され且つ他端が前記第１の
ＮＰＮトランジスタのコレクタに接続された第９の抵抗
と、コレクタが出力端子（基準）に接続され且つエミッ
タが前記第２のコンデンサの負極端子に接続された第２
のＮＰＮトランジスタと、一端が前記インバータの出力
端子に接続され且つ他端が前記第２のＮＰＮトランジス
タのベースに接続された第１０の抵抗と、コレクタが前
記出力端子（基準）に接続され且つエミッタが前記直流
電源の負極端子に接続された第３のＮＰＮトランジスタ
と、一端が前記コンパレータの出力端子に接続され且つ
他端が前記第３のＮＰＮトランジスタのベースに接続さ
れた第１１の抵抗とから構成されることを特徴とするレ
ベル変換回路。 ２、パルス状のアクティブロー入力を受けて入力振幅を
越えるアクティブハイ出力振幅を得るレベル変換回路に
おいて、直流電源と、正極電源端子が前記直流電源の正
極端子に接続され且つ負極電源端子が前記直流電源の負
極端子に接続されたインバータと、一端が前記直流電源
の正極端子に接続され且つ他端が前記インバータの入力
端子に接続された第１の抵抗と、アノードが前記直流電
源の正極端子に接続された第１のダイオードと、正極端
子が前記第１のダイオードのカソードに接続され且つ負
極端子が前記インバータの出力端子に接続された第１の
コンデンサと、正極電源端子が前記直流電源の正極端子
に接続され且つ負極電源端子が前記直流電源の負極端子
に接続され且つ反転入力端子が前記インバータの出力端
子に接続されたコンパレータと、一端が前記直流電源の
正極端子に接続され且つ他端が前記コンパレータの非反
転入力端子に接続された第２の抵抗と、一端が前記コン
パレータの非反転入力端子に接続され且つ他端が前記直
流電源の負極端子に接続された第３の抵抗と、正極端子
が前記コンパレータの出力端子に接続された第２のコン
デンサと、アノードが前記第２のコンデンサの負極端子
に接続され且つカソードが前記直流電源の負極端子に接
続された第２のダイオードと、エミッタが前記第１のコ
ンデンサの正極端子に接続されたＰＮＰトランジスタと
、一端が前記コンパレータの出力端子に接続され且つ他
端が前記ＰＮＰトランジスタのベースに接続された第４
の抵抗と、一端が前記ＰＮＰトランジスタのコレクタに
接続され且つ他端が出力端子に接続された第５の抵抗と
、エミッタが前記直流電源の負極端子に接続された第１
のＮＰＮトランジスタと、一端が前記コンパレータの出
力端子に接続され且つ他端が前記第１のＮＰＮトランジ
スタのベースに接続された第６の抵抗と、一端が前記出
力端子に接続され且つ他端が前記第１のＮＰＮトランジ
スタのコレクタに接続された第７の抵抗と、コレクタが
出力端子（基準）に接続され且つエミッタが前記第２の
コンデンサの負極端子に接続された第２のＮＰＮトラン
ジスタと、一端が前記インバータの出力端子に接続され
且つ他端が前記第２のＮＰＮトランジスタのベースに接
続された第８の抵抗と、コレクタが前記出力端子（基準
）に接続され且つエミッタが前記直流電源の負極端子に
接続された第３のＮＰＮトランジスタと、一端が前記コ
ンパレータの出力端子に接続され且つ他端が前記第３の
ＮＰＮトランジスタのベースに接続された第９の抵抗と
から構成されることを特徴とするレベル変換回路。 ３、パルス状のアクティブロー入力を受けて入力振幅を
越えるアクティブハイ出力振幅を得るレベル変換回路に
おいて、直流電源と、正極電源端子が前記直流電源の正
極端子に接続され且つ負極電源端子が前記直流電源の負
極端子に接続された第１のインバータと、一端が前記直
流電源の正極端子に接続され且つ他端が前記第１のイン
バータの入力端子に接続された第１の抵抗と、アノード
が前記直流電源の正極端子に接続された第１のダイオー
ドと、正極端子が前記第１のダイオードのカソードに接
続され且つ負極端子が前記第１のインバータの出力端子
に接続された第１のコンデンサと、正極電源端子が前記
直流電源の正極端子に接続され且つ負極電源端子が前記
直流電源の負極端子に接続され且つ入力端子が前記第１
のインバータの出力端子に接続された第２のインバータ
と、正極端子が前記第２のインバータの出力端子に接続
された第２のコンデンサと、アノードが前記第２のコン
デンサの負極端子に接続され且つカソードが前記直流電
源の負極端子に接続された第２のダイオードと、エミッ
タが前記第１のコンデンサの正極端子に接続されたＰＮ
Ｐトランジスタと、一端が前記第２のインバータの出力
端子に接続され且つ他端が前記ＰＮＰトランジスタのベ
ースに接続された第２の抵抗と、一端が前記ＰＮＰトラ
ンジスタのコレクタに接続され且つ他端が出力端子に接
続された第３の抵抗と、エミッタが前記直流電源の負極
端子に接続された第１のＮＰＮトランジスタと、一端が
前記第２のインバータの出力端子に接続され且つ他端が
前記第１のＮＰＮトランジスタのベースに接続された第
４の抵抗と、一端が前記出力端子に接続され且つ他端が
前記第１のＮＰＮトランジスタのコレクタに接続された
第５の抵抗と、コレクタが出力端子（基準）に接続され
且つエミッタが前記第２のコンデンサの負極端子に接続
された第２のＮＰＮトランジスタと、一端が前記第１の
インバータの出力端子に接続され且つ他端が前記第２の
ＮＰＮトランジスタのベースに接続された第６の抵抗と
、コレクタが前記出力端子（基準）に接続され且つエミ
ッタが前記直流電源の負極端子に接続された第３のＮＰ
Ｎトランジスタと、一端が前記第２のインバータの出力
端子に接続され且つ他端が前記第３のＮＰＮトランジス
タのベースに接続された第７の抵抗とから構成されるこ
とを特徴とするレベル変換回路。[Claims] 1. In a level conversion circuit that receives a pulsed active low input and obtains an active high output amplitude exceeding the input amplitude, a DC power supply and a positive power supply terminal are connected to the positive terminal of the DC power supply, and an inverter having a negative power terminal connected to the negative terminal of the DC power supply; a first resistor having one end connected to the positive terminal of the DC power supply and the other end connected to the input terminal of the inverter; a first diode connected to a positive terminal of a DC power supply; a first capacitor having a positive terminal connected to the cathode of the first diode and a negative terminal connected to the output terminal of the inverter; and a positive power supply terminal. is connected to the positive terminal of the DC power supply, and the negative power supply terminal is connected to the negative terminal of the DC power supply, and the comparator has one end connected to the positive terminal of the first capacitor and the other end the inverting input of the comparator. a second resistor connected to the terminal; a third resistor having one end connected to the inverting input terminal of the comparator and the other end connected to the negative terminal of the DC power supply; and a third resistor having one end connected to the positive terminal of the DC power supply. a fourth resistor, the other end of which is connected to the non-inverting input terminal of the comparator;
a fifth resistor whose one end is connected to the non-inverting input terminal of the comparator and whose other end is connected to the negative terminal of the DC power supply; and a second capacitor whose positive terminal is connected to the output terminal of the comparator; a second diode whose anode is connected to the negative terminal of the second capacitor and whose cathode is connected to the negative terminal of the DC power supply; and a PNP whose emitter is connected to the positive terminal of the first capacitor.
a sixth resistor having one end connected to the output terminal of the comparator and the other end connected to the base of the PNP transistor; one end connected to the collector of the PNP transistor and the other end connected to the output terminal. a first NPN transistor whose emitter is connected to the negative terminal of the DC power supply, one end of which is connected to the output terminal of the comparator, and the other end of which is connected to the base of the first NPN transistor. a ninth resistor whose one end is connected to the output terminal and whose other end is connected to the collector of the first NPN transistor; the collector is connected to the output terminal (reference); a second capacitor whose emitter is connected to the negative terminal of the second capacitor;
a tenth resistor having one end connected to the output terminal of the inverter and the other end connected to the base of the second NPN transistor, a collector connected to the output terminal (reference) and an emitter. from a third NPN transistor connected to the negative terminal of the DC power supply, and an eleventh resistor whose one end is connected to the output terminal of the comparator and the other end is connected to the base of the third NPN transistor. A level conversion circuit comprising: 2. In a level conversion circuit that receives a pulsed active low input and obtains an active high output amplitude exceeding the input amplitude, a DC power supply, a positive power supply terminal is connected to the positive terminal of the DC power supply, and a negative power supply terminal is connected to the DC power supply. an inverter connected to the negative terminal of the power source; a first resistor having one end connected to the positive terminal of the DC power source and the other end connected to the input terminal of the inverter; and an anode connected to the positive terminal of the DC power source. a first diode connected, a first capacitor whose positive terminal is connected to the cathode of the first diode and whose negative terminal is connected to the output terminal of the inverter, and whose positive power terminal is connected to the positive terminal of the DC power supply. a comparator connected to the inverter terminal and having a negative power terminal connected to the negative terminal of the DC power supply and an inverting input terminal connected to the output terminal of the inverter; a second resistor connected to the non-inverting input terminal of the comparator; a third resistor having one end connected to the non-inverting input terminal of the comparator and the other end connected to the negative terminal of the DC power supply; a second capacitor whose terminal is connected to the output terminal of the comparator; a second diode whose anode is connected to the negative terminal of the second capacitor and whose cathode is connected to the negative terminal of the DC power supply; and an emitter. is a PNP transistor connected to the positive terminal of the first capacitor, and a fourth transistor whose one end is connected to the output terminal of the comparator and whose other end is connected to the base of the PNP transistor.
a fifth resistor whose one end is connected to the collector of the PNP transistor and whose other end is connected to the output terminal; and a first resistor whose emitter is connected to the negative terminal of the DC power supply.
a sixth resistor having one end connected to the output terminal of the comparator and the other end connected to the base of the first NPN transistor; and a sixth resistor having one end connected to the output terminal and the other end connected to the first NPN transistor. a seventh resistor connected to the collector of the first NPN transistor; a second NPN transistor whose collector is connected to the output terminal (reference) and whose emitter is connected to the negative terminal of the second capacitor; an eighth resistor connected to the output terminal of the inverter and the other end connected to the base of the second NPN transistor; a collector connected to the output terminal (reference) and an emitter connected to the negative terminal of the DC power supply; a third NPN transistor connected to the terminal; and a ninth resistor, one end of which is connected to the output terminal of the comparator, and the other end of which is connected to the base of the third NPN transistor. level conversion circuit. 3. In a level conversion circuit that receives a pulsed active low input and obtains an active high output amplitude exceeding the input amplitude, a DC power supply, a positive power supply terminal is connected to the positive terminal of the DC power supply, and a negative power supply terminal is connected to the DC power supply. a first inverter connected to the negative terminal of the power source; a first resistor having one end connected to the positive terminal of the DC power source and the other end connected to the input terminal of the first inverter; a first diode connected to a positive terminal of a DC power source; a first capacitor whose positive terminal is connected to the cathode of the first diode and whose negative terminal is connected to the output terminal of the first inverter; A positive power supply terminal is connected to the positive terminal of the DC power supply, a negative power supply terminal is connected to the negative terminal of the DC power supply, and the input terminal is connected to the first
a second inverter connected to the output terminal of the inverter; a second capacitor having a positive terminal connected to the output terminal of the second inverter; an anode connected to the negative terminal of the second capacitor; a second diode whose cathode is connected to the negative terminal of the DC power source; and a PN whose emitter is connected to the positive terminal of the first capacitor.
a P transistor; a second resistor having one end connected to the output terminal of the second inverter and the other end connected to the base of the PNP transistor; one end connected to the collector of the PNP transistor and the other end connected to the base of the PNP transistor; a third resistor connected to an output terminal; a first NPN transistor whose emitter is connected to the negative terminal of the DC power supply; and one end connected to the output terminal of the second inverter and the other end connected to the second inverter. a fourth resistor connected to the base of the first NPN transistor; a fifth resistor having one end connected to the output terminal and the other end connected to the collector of the first NPN transistor; and a fifth resistor having a collector connected to the output terminal. (reference) and whose emitter is connected to the negative terminal of the second capacitor; and one end is connected to the output terminal of the first inverter and the other end is the second NPN transistor. a sixth resistor connected to the base of the transistor; and a third NP whose collector is connected to the output terminal (reference) and whose emitter is connected to the negative terminal of the DC power supply.
A level conversion circuit comprising: an NPN transistor; and a seventh resistor, one end of which is connected to the output terminal of the second inverter, and the other end of which is connected to the base of the third NPN transistor. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2307656A JP2982293B2 (en) | 1990-11-14 | 1990-11-14 | Level conversion circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2307656A JP2982293B2 (en) | 1990-11-14 | 1990-11-14 | Level conversion circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04179311A true JPH04179311A (en) | 1992-06-26 |
| JP2982293B2 JP2982293B2 (en) | 1999-11-22 |
Family
ID=17971672
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2307656A Expired - Lifetime JP2982293B2 (en) | 1990-11-14 | 1990-11-14 | Level conversion circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2982293B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0786909A (en) * | 1993-06-30 | 1995-03-31 | Nec Corp | Output circuit for semiconductor integrated circuit |
| US7049876B2 (en) | 2004-10-25 | 2006-05-23 | Delphi Technologies, Inc. | Level shift circuits and related methods |
-
1990
- 1990-11-14 JP JP2307656A patent/JP2982293B2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0786909A (en) * | 1993-06-30 | 1995-03-31 | Nec Corp | Output circuit for semiconductor integrated circuit |
| US7049876B2 (en) | 2004-10-25 | 2006-05-23 | Delphi Technologies, Inc. | Level shift circuits and related methods |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2982293B2 (en) | 1999-11-22 |
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