JPS6020836B2 - decoder circuit - Google Patents

Description

[Detailed description of the invention] {11 Field of application of the invention The present invention relates to a high-speed decoder circuit.

'21 From the background of the prior art, as a relatively low power consumption and high speed decoder circuit, the transistor or diode shown in Fig. 1 (the Marchemitter transistor shown in Fig. 1 may be directly replaced with the same number of diodes as the number of emitters) is used. Decoder circuits are known and are used in memory LSIs and the like.

In this decoder circuit part 11, all the current that flows through the decoder circuit part 11 flows through only one buffer part. Compared to a decoder circuit that flows current, it requires less current when the speed is the same, and can be expected to be faster when the same amount of current consumption flows. In the conventional decoder circuit shown in FIG. 1, the delay time tpdf at the fall of the output waveform is certainly very fast. It is the collector load line 12 or 13 of the buffer
This is because it is discharged by the large current IB of the buffer circuit. On the other hand, at startup, it is necessary to charge the load line with one resistor Ro. The current flowing through the resistor Ro is N18/2
N or less, N=5 and 0.1561B to 0.09
418 or less (as the voltage on the load line increases, the charging current decreases). On the other hand, since a 2N/2 emitter is connected to the load line, the rise time of the waveform becomes long, and as a result, the fall delay time 〇dr becomes slow. '3' OBJECT OF THE INVENTION An object of the present invention is to provide a transistor or diode decoder circuit with a quick response at rise.

[4] General description of the invention In order to speed up the rise time of the load line, the present invention uses a mechanism that rapidly charges the load line at the time of rise.

Therefore, the output rise time is approximately R. and decoder transistor Q. It is determined by the product of the stray capacitances of the collector and base of , resulting in very high speed RDR. Wind Examples Hereinafter, the present invention will be explained in detail with reference to Examples.

FIG. 2 is a circuit diagram of one embodiment of the present invention.

In this embodiment, a charging circuit 23 is added to the circuit of FIG. 1 in accordance with the preconceptions of the present invention. The charging circuit of this embodiment is composed of ordinary current switches, and one charging circuit is provided for each buffer circuit. Since this current switch charges the load line via the emitter follower, the current lcH can be obtained at a sufficiently high speed at a rate of L/1 of the current IB of the buffer circuit, so the overall increase in power consumption is negligible. . Also, R8 is a leak resistance to determine the high level of the load line.
Since it has nothing to do with speed, a large value is sufficient, and the power consumed thereby can be ignored. In the circuit shown in FIG. 2, since charging at the time of the rise of the load line is performed by the emitter follower QEF, the rise is extremely fast.

On the other hand, at the time of rising, it is discharged at 18 and QEF becomes low level and is cut off, so tpdr is the same as the circuit shown in FIG. FIG. 3 shows tpdr experimental results for the conventional circuit shown in FIG. 1 and the circuit according to the embodiment of the present invention shown in FIG.

In this experiment, the present invention was able to reduce tpdr to about 1/2. Although this result is for N=5, if the number of decoders increases further, the difference between the present invention and the conventional neighbor will further widen. Although the present invention has been described above in connection with specific embodiments, the charging circuit of the circuit of the present invention may be any circuit as long as it forcibly raises the voltage of the load line corresponding to the rising edge of the output signal. But the good thing is that
It will be clear to those skilled in the art.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a conventional decoder circuit, FIG. 2 is a circuit diagram of an embodiment of the present invention, and FIG. 3 is a waveform diagram showing the effects of the present invention. XI team 2 vs. 3

Claims (1)

[Claims] 1. A plurality of first switch means each connecting a signal line to a first power supply according to an input terminal, and a plurality of first switch means each connecting a cathode to the signal line through a common resistor. In a decoder circuit comprising a plurality of rectifiers whose anodes are connected to a second power source, the anodes of the rectifiers serve as output terminals, the input signal is inputted, and when the first switch means is OFF, the decoder circuit A decoder circuit comprising a second switch that connects a signal line and a third power source and turns off the connection between the signal line and the third power source when the first switch means is ON. . 2. The plurality of rectifiers are a plurality of emitter transistors having a base and a collector connected to each other as the anode, and a plurality of emitters as the plurality of cathodes, and the first power source is a pair of the first The decoder circuit according to claim 1, wherein the decoder circuit is a current source provided in common to the switching means, and the second and third power supplies are voltage sources provided separately. . 3. The first switch means is a transistor whose emitter is connected to the first power supply, whose collector is connected to the signal line, and whose base is applied with the input signal,
The second switching means comprises an inverter for inverting the input signal, and a transistor having a collector connected to the third power supply, an emitter connected to the signal line, and a base to which the output of the inverter is applied. A decoder circuit according to claim 1, characterized in that: 4. The second switch means has means for holding the corresponding signal line at a predetermined voltage when the first switch means corresponding to the corresponding signal is off. A decoder circuit according to range 1. 5. Each of the plurality of signal lines is a pair of signal lines, the switch means connects one of the pair of signal lines to the first power source according to the input signal, and the rectifier means connects one of the pair of signal lines to the first power source according to the input signal. The group selectively connects one of the plurality of pairs of signals to the cathode, and there are a plurality of rectifying means groups having different combinations of signal lines connected to the cathode, and the third switch Claim 1, characterized in that the means inputs the input signal and connects the signal line of the pair of signal lines that is not connected to the first power source to the third power source. Decoder circuit described in section.