JPH04177881A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the crystallinity of an InGaAs and the conditions of the interface between the InGaAs layer and an InP layer by specifying the growth conditions of the InGaAs layer. CONSTITUTION:An InP first semiconductor layer 21, an InGaAs second semiconductor layer 22 the lattice of which is commensurate with an InP single-crystal substrate 20, and an InP third semiconductor layer 23 are successively grown by crystal growth on the substrate 20. The second semiconductor layer 22 is grown at a crystal growth speed not higher than 2.5mum/hr and a molar ratio not higher than 2.5X10<-3> in the gas phase of the compound material of As. Thereby the crystallinity of the InGaAs layer 22 and the conditions of the interface between the InP layer 21 and the InGaAs layer 22 can be improved, the dark current of an APD and a PIN photodiode can be reduced by their multiplier action, and a high-efficiency semiconductor laser device can be obtained.

Description

[Detailed Description of the Invention] [Summary] Regarding a method for manufacturing a compound semiconductor, particularly an InP-based epitaxial wafer, by a metal organic vapor phase epitaxy (MOVPE) method, the crystallinity of an InGaAs (or InGaAsP) layer, and the relationship between the core layer and InP By improving the interface condition with the layer,
With the aim of manufacturing a semiconductor device with good electrical characteristics such as dark current and differential efficiency, a first semiconductor layer of InP crystal-grown on an InP single crystal substrate, and a first semiconductor layer of InGaAs lattice-matched to the substrate are formed. When growing the second semiconductor layer of the second semiconductor layer and the third semiconductor layer of InP, the crystal growth rate is 2.5 μva/Hr or less, and the mole of As compound raw material in the gas phase is The method includes a step of growing at a ratio of 2.5×10 −3 or less. Further, the second semiconductor layer is made of As.
The growth is performed with the ratio of the molar ratio of the compound raw material in the gas phase to the molar ratio of the group II compound raw material in the gas phase under 16 pI.

[Industrial application field]

The present invention relates to a method for manufacturing a compound semiconductor, particularly an InP-based epitaxial wafer, by the MOVPE method.

For example, light-emitting elements and light-receiving elements are used in optical communication using optical fibers, and compound semiconductors, particularly InP-based epitaxial wafers, are used for these light-emitting elements and light-receiving elements. Conventionally, a liquid phase epitaxy (LPE) method has been used to manufacture epitaxial wafers, but recently MOVPE has been put into practical use due to the need for uniformity in film thickness and large area.

Therefore, is it necessary to obtain device characteristics equivalent to or better than when using Uenox manufactured by the LPE method even when using UNO/S manufactured by the MOVPE method?
When Ueno 1 manufactured by the VPE method is used as a light receiving element, the dark current is large as will be described later, and a sufficient output current cannot be obtained when receiving weak light. On the other hand, when used in a light emitting device, sufficient differential efficiency cannot be obtained. Therefore, it is necessary to manufacture epitaxial wafers with small dark current and sufficient differential efficiency using the MOVPE method.

[Conventional technology]

For example, an avalanche photodiode (A
MOV the epitaxial wafer used for PD)
When manufacturing using the PE method, trimethylindium (TMI
),) ethyl gallium (TEG), arsine (As
H2), phosphine (PH3) respectively In, Ga, As
, as a raw material for P, and the growth temperature was set at 590°C to 650°C.
'C, growth pressure is 50 torr to 100 torr. Under these conditions, InP is deposited on the InP substrate.
Buffer layer, InGaAs layer lattice matched to the substrate, In
A GaAsP buffer layer and an InP layer are grown to produce a double heterostructure wafer.

In particular, the crystal growth rate (Rg) of the InGaAs layer is 4 μ
m/)Ir ~6 μm/Hr, As in gas phase
The molar ratio of H3 is 4X10"2 to 6X10". When an avalanche photodiode is constructed using an epitaxial wafer manufactured under such growth conditions, the dark current when a voltage of 90% of the breakdown voltage is applied is more than 100 nA.

On the other hand, when manufacturing an epitaxial wafer used in a PIN photodiode, which is a light receiving element, by the MOVPE method, the same raw materials as in the case of APD are used, the growth temperature and growth pressure are also the same as in the case of APD, and an InP buffer layer is formed on an InP substrate. , InGaAs layer lattice matched to the substrate, InGa
A double heterostructure wafer is manufactured by growing an AsP buffer layer and an InP layer. In particular, the Rg of the InGaAs layer is 4 μm/Hr to 6 μm/Hr, which is the same as that of APD.
Hr, the molar ratio of A s Hs in the gas phase is 4X10-”~
It is 6×10−3. When a PIN photodiode is constructed using an epitaxial wafer manufactured under such growth conditions, the dark current is 2 nA when a 5 V reverse voltage is applied.

[Invention or problem to be solved]

In the conventional device, the growth rate and growth pressure of the InGaAs layer are set to the conditions described above, so the dark current of the APD is 100-odd nA (preferably 10 nA or less),
The dark current of the PIN photodiode is 2 nA (preferably less than 0.1 nA), which is considerably larger than that when epitaxial wafers are manufactured using the LPE method, and the dark current is sufficient, especially when exposed to weak light. However, there was a problem that it was difficult to put it into practical use.

Furthermore, since epitaxial wafers used in semiconductor lasers are manufactured using the same growth conditions as described above, there is a problem in that it is difficult to obtain sufficient differential efficiency.

The reason why such a problem occurs is not clear, as will be explained in detail later, but when growth is performed using the above-mentioned growth conditions, the crystallinity of the InGaAs (or InGaAsP) layer and the acid layer and InP This is thought to be due to deterioration of the interface condition with the layer.

The present invention provides a method for manufacturing a semiconductor device with good electrical characteristics such as dark current and differential efficiency by improving the crystallinity of the InGaAs (or InGaAsP) layer and the interface state between the acid layer and the InP layer. The purpose is to

[Means to solve the problem]

FIG. 1 shows a diagram of the principle of the present invention. The figure (A) is a characteristic diagram showing the relationship between the crystal growth rate, the molar ratio of the As compound raw material in the gas phase, and the dark current, and the figure (B) is the structure of a semiconductor device manufactured by the method of the present invention. It is a diagram. The above-mentioned problem is as shown in FIG.
At least a first semiconductor layer 21 of InP. an InGaAs semiconductor layer 22 lattice-matched to the substrate 20; In a method for manufacturing a semiconductor device with a double heterostructure by continuously growing crystals of a third semiconductor layer 23 of TnP by metal-organic vapor phase epitaxy, the second semiconductor layer 22 is formed as shown in FIG. , the crystal growth rate is 2.5 μm/Hr or less, and A
The problem is solved by a method for manufacturing a semiconductor device, which includes a step of growing a compound raw material of s at a molar ratio of 2.5×10 −3 or less in the gas phase. Further, in this case, the second semiconductor layer 22 is grown with the ratio of the molar ratio of the As compound raw material in the gas phase to the molar ratio of the Group 2 compound raw material in the gas phase to 16 or less.

[Effect]

If the molar ratio is set as described above, the growth will be similar to that of InGaAs.
from the second semiconductor layer 22 of InP to the third semiconductor layer 23 of InP.
When switching to , an intermediate layer such as In-A s t P + A (which is thick depending on the amount of As remaining or attached to the reaction tube, etc., and the lattice irregularity is thought to be large) is not formed at the interface. It is also believed that setting the crystal growth rate as described above improves crystallinity. In addition, since the ratio of the molar ratio in the gas phase of the AS compound raw material to the molar ratio in the gas phase of the group ■ compound raw material was set as described above, defects such as vacancies in the group ■ compound raw material can be reduced. According to the present invention, the crystallinity of the second semiconductor layer 22 and the interface state between the second semiconductor layer 22 and the third semiconductor layer 23 can be improved, so due to the synergistic effect of these, the dark current can be reduced to 10 nA in the case of an APD. Hereinafter, in the case of a PIN photodiode, the dark current can be reduced to 0.1 nA or less. In addition, in the case of semiconductor lasers, the differential efficiency is 2
It can be improved by about 5%.

〔Example〕

FIG. 2 shows a block diagram of a PIN photodiode manufactured by the method of the present invention. In Figure 2, l is an n-InP substrate, 2 is an n-1nP buffer layer, and 3 is n--InGaAs.
4 is an n-InP cap layer, 5 is a silicon nitride film, 6 is a P''-InP layer formed by Zn diffusion, 7 is a p electrode, and 8 is an n-type layer.
It is a t-pole and constitutes a PTN photodiode. In addition,
The structure is the same as the conventional one. Here, a negative voltage was applied to the p-electrode 7, and a positive voltage was applied to the nE electrode, and the results of measuring the dark current with respect to the growth conditions are shown in FIGS. 3 and 4.

Figure 3 shows the relationship between the growth rate (Rg) and the dark current (Id) of the InGaAs layer 3 based on the molar ratio of A s H2 in the gas phase (X
A, , Iff) is plotted as a parameter,
Figure 4 shows the molar ratio of ASH2 (XA3.I2) and the dark current (
Id) and the growth rate (Rg) of the InGaAs layer 3
is plotted as a parameter. It is said that it is desirable for the dark current of a PIN photodiode to be 0.1 nA or less due to its performance, and in order to obtain such a desirable value, as is clear from Figs. 3 and 4,
When the Rg of the GaAs layer 3 is 2.5 μm/Hr or less, the AsH3(7) molar ratio (X A,...) is 2.5X
]0-3 or less or required.

Therefore, in the present invention, as a growth condition when manufacturing an epitaxial webber by the MOVPE method, the InGaAs layer 3
The Rg of the compound is 2.5 μm /Hr or less, and the molar ratio of the As compound raw material in the gas phase is 2.5×10 −3 or less. Note that the growth pressure is 76 torr and the growth temperature is 630°C. In this case, although the reason is not clear, if the molar ratio of As H2 (X The As attached to the I will detach again and grow.
When switching from nGaAs layer 3 to InP layer 4, the intermediate layer (
I n A S The interface condition is improved by not making it larger than necessary and by setting it to 2.5 x 10-+ or less to avoid forming an intermediate layer at the interface between the InGaAs layer 3 and the InP cap layer 4. On the other hand, if Rg If it is larger than necessary, InGaAs
Since the crystallinity of layer 3 deteriorates, in the present invention, Rg is set to 2.5μ.
m/Hr or less. At this time, the molar ratio of AsHs in the gas phase (X As, 3) and the group II compound raw materials (In and Ga
) to X[) (XA3□, / , XAsH3/X- is made as small as 14 within a range that does not cause defects due to so-called As omission from the growth surface.

In this way, in the present invention, the Rg of the InGaAs layer 3 is set to 2.
5 μm/Hr or less and the molar ratio of the As compound raw material in the gas phase to 2.5×10 −3 or less, the crystallinity of the InGaAs layer 3 and the interface between the InGaAs layer 3 and InP layer 4 are improved. Since the condition can be improved, the synergistic effect of these makes it possible to reduce the dark current to 0.1 nA or less, and to extract a sufficient output current even when receiving weak light.

The above example is a case of a PIN photodiode, but
PIN also for avalanche photodiode (APD)
The same concept as in the case of a photodiode may be used. FIG. 5 shows a configuration diagram of an APD manufactured by the method of the present invention,
In the figure, the same components as those in FIG. 2 are given the same numbers and their explanations will be omitted. In FIG. 5, 4a is an InGaAsP buffer layer for preventing pile-up, and 4b is an n''-In
P layer, 4c is n-1nP multiplication layer, 6a is guard ring,
9 is a non-reflection coat and constitutes an APD. Note that the structure is the same as the conventional one.

When manufacturing this APD epitaxial wafer, the growth pressure was 76 torr, the growth temperature was 630°C, and
sH3 is used, the impurity is St doped, and InG
Rg of aAs layer 3 is 211m/Hr, xAsH3 is 1.25X 10"2.
The epitaxial wafer is grown by setting 14. As a result, A
The dark current (1d) of the PD is 10 nA, which is significantly smaller than that of the conventional example described above (more than 100 nA), and a sufficient output current can be extracted even when receiving weak light. APD
In the case of , if growth is performed under conventional growth conditions, InGa
In between the As layer 3 and the InGaAsP buffer layer 4a
)'Ga++-y+ ASXP ++-x+ (A
An intermediate layer containing a large amount of S
It is believed that this intermediate layer is not formed under the growth conditions of the present invention, and that the crystallinity of the InGaAs layer 3 can be improved. In this case, Rg and X A 8 H3
By reducing each to 1/2 of the above value, the dark current can be further reduced.

As yet another embodiment, there is a semiconductor laser shown in FIG. 6, and the manufacturing of an epitaxial wafer in this case may be carried out in the same manner as in the above-mentioned embodiment. In Figure 6, IO
is a p-1nP substrate, 11 is a p-1nP buffer layer, 12
1 is an InGaAsP active layer, and 13 is an n-InP cladding layer, which is structurally the same as the conventional one. During its manufacture, InGaAsP active layer 12 (wavelength: 1.3 μm)
Growth temperature: 630℃, growth pressure cuff: 6 torr
, Rg”1.5 μm/Hr, XAs++2=5
．． The growth was performed under the following conditions: 9×10−′, XA5H2/X[=8.3, and after the grown wafer was mesa-etched in stripes, it was buried by the LPE method as in the conventional method, and then devices were formed. The differential efficiency of the semiconductor laser manufactured in this way is improved by about 25% compared to the conventional example, and is 0.2 mW.
/ mA was obtained. In this way, when grown under growth conditions based on the same concept as each of the above-mentioned examples,
(2) This is thought to be because the state of the interface between the nGaAsP layer 12 and the InP layer 1 is improved as in the previous embodiment, and the power loss at this interface is reduced.

In addition, tertiary butylaluminum (T) is used as an As compound.
BA) will increase the decomposition rate, so A s H2
This TEA may be used instead of. By using TEA, it is possible to further lower the molar ratio XTl1A in the gas phase,
It is possible to further reduce the dark current.

〔Effect of the invention〕

As explained above, according to the present invention, the InGaAs layer is grown at Rg of 2.5 μm/Hr or less and at a molar ratio of As compound raw material in the gas phase of 2.5×10 −2 or less. As a result, the crystallinity of InGaAs and the interface state between these two layers can be improved, and the synergistic effect of these two layers improves A.
With PD and PIN photodiodes, dark current can be made smaller than in conventional examples, and with semiconductor lasers, it is possible to obtain higher efficiency than in conventional examples.

[Brief explanation of the drawing]

FIG. 1 is a diagram of the principle of the present invention. FIG. 2 is a configuration diagram of a PIN photodiode manufactured according to the present invention. FIG. 3 is a diagram of the Rg versus current characteristic of the PIN photodiode. FIG. 4 is a diagram of the XA of the PIN photodiode. , , Dark current characteristic diagram, FIG. 5 is a block diagram of an APD manufactured by the present invention, and FIG. 6 is a block diagram of a semiconductor laser manufactured by the present invention. In the figure, 1, 1O is the InP substrate, 2.11 is the InP buffer layer, 3 is the InGaAs layer, 4 is the InP cap layer, 4a is the InGaAsP buffer layer, 4b, 4C, 6, 11, 13 are the InP layers, and 5 is the InP layer. Silicon nitride film, 7 is a p-electrode, 8 is an n-electrode, 9 is an anti-reflective coating, 12 is an InGaAsP active layer, 20 is an InP single crystal substrate, 21 is an InP first semiconductor layer, 22 is an InGa, As first semiconductor layer 2 semiconductor layer, 23 is InP
The third semiconductor layer of FIG.

Claims (3)

[Claims] (1) At least InP on the InP single crystal substrate (20)
A first semiconductor layer (21) of P, a second semiconductor layer (22) of InGaAs lattice-matched to the substrate (20), and a second semiconductor layer (22) of InP
In a method for manufacturing a double heterostructure semiconductor device by successively growing crystals of the third semiconductor layer (23) using metal-organic vapor phase epitaxy, the second semiconductor layer (22) is grown at a crystal growth rate of is 2.5
A method for manufacturing a semiconductor device, comprising the step of growing at a rate of μm/Hr or less and at a molar ratio of As compound raw material in a gas phase of 2.5×10^-^3 or less. (2) The method for manufacturing a semiconductor device according to claim 1, characterized in that the second semiconductor layer (22) is formed using a group III compound raw material in a molar ratio of a compound raw material of As in the gas phase. (3) The method for manufacturing a semiconductor device according to claim 1, wherein the second semiconductor layer (22) is a layer containing P.