JPH04177325A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To enlarge inrush current so as to enlarge current margin by connecting the output of a complementary thin film transistor to a picture element. CONSTITUTION:The gate of PTFT 21 and that of NTFT 11 are connected with each other, which is connected to a line VGG22 or VGG'23 in the direction of Y axis, while the common output of C/TFT is connected to a liquid crystal 12. When the input of PTFT is connected to lines VDD18, VDD'18' in the direction of X axis, while the input of NTFT is grounded to earths 19, 19', if VDD18, VDD'22 are '1', a liquid crystal electric potential 10 becomes '0', and when VDD18 is '1' and VGG22 is '0', the liquid crystal potential 10 will be '1'. When the picture element of the liquid crystal 12 is '1' compared with an electric potential 13 of a counter electrode, the liquid crystal is turned ON, and when the liquid crystal electric potential 10 is '0', the liquid crystal is turned OFF. The liquid crystal electric potential 10 is thus not floated. A current margin can thus be enlarged.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Application of the Invention The present invention relates to an active liquid crystal display device.
In particular, each pixel is provided with two complementary thin film type insulated gate field effect transistors (hereinafter referred to as TPT).

"Prior Art" Active type liquid crystal display devices using TPT have been known in the past. In this case, an amorphous or polycrystalline semiconductor is used for the TPT, and a TPT of only one conductivity type, P or N type, is used for one pixel. That is, generally, N-channel type TPTs (referred to as NTFTs) are connected in series to the pixels ζ.

A typical example is shown in FIG.

In FIG. 1, it has a liquid crystal (12) and is connected in series with an NTFT (11). This is arranged in a matrix. Generally 640x480
Or, it is often 1260 x 960, but in this drawing, it has the same meaning as a simple 2 x 2 matrix arrangement. For each pixel, a peripheral circuit (16),
(17) A voltage was applied to selectively turn on predetermined pixels and turn off other pixels. Then this TPT turns on,
If the off-state characteristics are generally good, a liquid crystal display device with high contrast can be produced. However, when actually manufacturing such a liquid crystal display device, the voltage VL of the output of the TPT, that is, the input to the liquid crystal (referred to as liquid crystal potential)
C(10) often does not become "I" (High) when it should be "1" (High), and conversely, it becomes "0" (
It may not become "O" (Low) when it should be "O" (Low). The liquid crystal (12) is inherently insulating in its operation, and when the TPT is off, the liquid crystal potential (VLc)
becomes floating. Since this liquid crystal (12) is isometrically a capacitor, V L c is determined by the charge accumulated there. This charge is generated when the liquid crystal has a relatively small resistance in RLC, leaks due to the presence of dust or ionic impurities, or when Ras (15) is generated due to a pinhole in the gate insulating film of TPT. Leakage ■.

ends up in a halfway state. For this reason, a high yield cannot be achieved in a liquid crystal display device having 200,000 to 5,000,000 pixels in one panel.

In particular, as the liquid crystal (12), a TN (twisted nematic) liquid crystal is generally used. To align the liquid crystal, a rubbed alignment film is provided on each electrode. The static electricity generated due to this rubbing process causes a weak dielectric breakdown, resulting in leakage between adjacent pixels or adjacent conductive lines, or weak gate insulating films, resulting in leakage.

In active type liquid crystal display devices, the liquid crystal potential is set to 1
It is very important that the predetermined level is constantly maintained at the same initial value during the frame. However, in reality, many of them are defective, and the reality is that they are not always successful.

Furthermore, if the material is a liquid crystal material or a ferroelectric liquid crystal, a large injection current is required. For this purpose, the TPT must be made large to ensure a large current margin, which is a drawback.

``Object of the Invention'' The present invention solves these problems, increases the current margin, that is, increases the response speed, and improves the V LC.
1" and "0" with sufficient stability to prevent the level from drifting during one frame.

"Structure of the Invention" In the present invention, an output terminal of a complementary TPT is connected to one electrode of a transparent conductive film of each pixel arranged in a matrix. That is, a P-channel type TPT (hereinafter referred to as PTFT) and an NTFT are connected to all pixels arranged in a matrix as a complementary type (hereinafter referred to as C/TFT).

Typical examples thereof are shown as circuits in FIGS. 2 and 3.

Further, an example of an actual pattern layout (arrangement diagram) is shown in FIG.

That is, in the 2×2 matrix example of FIG.
A line V in the Y-axis direction connects the gates of FT and NTFT to each other. . (22), or V, , (23). Also, the common output of C/TPT is connected to the liquid crystal (12). Connect the PTFT input (Vss side) to the X-axis line VDD (18), V oo, (18°), and connect the NTFT input (V, , side) to ground (19), (1
9') Then Vbo (18).

When VC, (22) is “1”, the liquid crystal potential (lO) is “0”
”, and Voo (18) is “1”, V, , (2
2) is "0", the liquid crystal potential (10) becomes "1". The liquid crystal pixel (12) turns on when it becomes "1" compared to the opposite electrode potential (13) (generally ground potential). Conversely, when the liquid crystal potential (10) is 0'', the liquid crystal is turned off.

Since the liquid crystal potential (10) is fixed to either VDD (18), ground, or V, (19), it does not float.

In the example of FIG. 3, the wiring (18) in the X-axis direction.

(18'), ground terminal (19), (19')
Also wired in the X-axis direction. Then, (19
), (19') are used in common to obtain Vss (19). When trying to construct a 2×2 matrix, Vs
s(19) is a common wiring between the pixel above it and the pixel below it.

In this case, the liquid crystal potential VLC is either V DD or V s
It can be fixed in any direction. PTFT(21), N
Since it is complementary to the TFT (11), there is no problem even if there is dust or ionic leakage in the RLC (14).

In addition, even if there is a slight leakage between adjacent wirings, VLC is constantly supplied with charge from Voo (18) or Vss (19), so the level within the frame is constant instead of floating. I can do it.

The present invention will be illustrated below based on Examples.

"Example 1" This example is illustrated using FIGS. 2, 3, 5, and 6.

The manufacturing process for making C/TPT on a glass substrate is shown in FIG.

In Figure 6, a silicon oxide film (3) is deposited as a blocking layer on glass such as AN glass or Pyrex glass that can withstand heat treatment at about 600°C using magnetron RF (radio frequency) sputtering. It was made thick.

Process conditions are 100% oxygen atmosphere, film formation temperature 150°
C1 output was 400 to 800 W1 pressure was 0.5 Pa. The film formation rate using quartz or single crystal silicon as a target was 30 to 100 people/min.

Furthermore, a silicon film was formed on this by LPGVD (low pressure vapor phase) method, sputtering method, or plasma CVD method.

When formed by a reduced pressure vapor phase method, the temperature is 100 to
Disilane (SiJg) or trisilane (SjsHs) is heated to 200°C lower at 450-550°C, e.g. 530°C.
A film was formed by supplying it to a VD apparatus. The pressure inside the reactor is 30~3
It was set to 00Pa. The film forming rate was 50 to 250 people/min. Threshold voltage (V
th), boron may be added during film formation using diborane at a concentration of IXIO'' to IX1017cm-''.

When using the sputtering method, the back pressure before sputtering is 1X 10
-'Pa or less, target single crystal silicon,
The experiment was carried out in an atmosphere containing 20 to 80% hydrogen in argon. For example, 20% argon and 80% hydrogen were used. The film forming temperature was 150° C., the frequency was 13.56 MHz, and the sputtering power was 400 to 800 W. The pressure was 0.5 Pa.

When a silicon film is manufactured by plasma CVD, the temperature is, for example, 300° C., and monosilane (SiHa) or disilane (Si2Hg) is used. PCV these
It was introduced into apparatus D, and a film was formed by applying high frequency power of 13.56 MHz.

The films formed by these methods contain 7
10"cm-" or less, preferably I x 10'"
It is preferable that the concentration is less than 8cm-cm. This is because it can promote the degree of crystallization when typical crystallization is carried out.For example, oxygen or X 10'”Cm-3
, carbon 3 x 10"cm-" was obtained. Also, hydrogen is 4
X 102102O", silicon 4 XIO"cm-
”, it was 1 atomic %.

In this way, the silicon film in the amorphous state is
After fabrication to a thickness of 0, for example 1500, 450 to 7
Medium temperature heat treatment was carried out in a non-oxide atmosphere at a temperature of 00°C for 12 to 70 hours. For example, the temperature was maintained at 600° C. in a nitrogen or hydrogen atmosphere.

Since an amorphous silicon oxide film is formed on the surface of the substrate under this silicon film, no specific nuclei are present in this heat treatment, and the whole is uniformly heated and annealed. That is, when the film is formed, it has an amorphous structure, and hydrogen is simply mixed therein.

By this annealing, the silicon film changes from an amorphous structure to a highly ordered state, and a part of the silicon film exhibits a crystalline state.

In particular, during silicon film formation, regions with relatively high order tend to crystallize and become crystalline. However, since the silicon existing between these regions forms bonds with each other, the silicon elements attract each other. When measured by laser Raman spectroscopy as a crystal, peak 5 of single crystal silicon is observed.
A peak shifted to the lower frequency side than 22 cm" is observed. The apparent particle size is calculated from the half-width of 5.
0 to 500 people, and it looks like a microcrystal, but in reality there are many highly crystalline regions that have a cluster structure, and each cluster is made up of semi-containing particles that are bonded (anchored) to each other by silicon. A film with an amorphous structure could be formed.

As a result, this coating has virtually no grain boundaries (
It can be said that there is no GB). Since carriers can easily move between each cluster through the anchored locations, the carrier mobility is higher than in polycrystalline silicon where so-called GB is clearly present. That is, Hall mobility (μh) = 10 to 200 cm”/Vse
c, electron mobility (μe) = 15 to 300 cm”/
Vsec is obtained.

On the other hand, instead of annealing at medium temperature as described above,
When the film is made polycrystalline by high-temperature annealing at a temperature of 1200°C, impurities in the film segregate due to solid phase growth from the nuclei, and impurities such as oxygen, carbon, and nitrogen increase in GB, resulting in crystallization. Although the mobility inside is high, it creates a barrier at the GB and inhibits the movement of carriers there. As a result, the actual situation is that it is difficult to obtain a mobility of 10 cm''/Vsec or more.

That is, in the embodiments of the present invention, a silicon semiconductor having a semi-amorphous or semi-crystalline structure is used.

In FIG. 6(A), this silicon film is photo-etched using the first photomask ① to create a PTFT region (21) on the right side of the drawing and an NTFT region (11) on the left side. did.

Moreover, a silicon oxide film is placed on top of this as a gate insulating film with a thickness of 5 mm.
00 to 2000 people, for example 1000 people. These conditions were the same as those for producing a silicon oxide film as a blocking layer. A small amount of fluorine may be added during this film formation.

Furthermore, after this, 1 to 5 x 1020 cm of phosphorus is added to the upper side of this.
A silicon film with a concentration of ``'' or molybdenum (MO) and tungsten (W) on this silicon film.

A multilayer film of either MoSi2 or WSi2 was formed. This was patterned using a second photomask (2). Then, a gate electrode (4) for PTFT and a gate electrode (4°) for NTFT were formed. For example, channel length 10 μm,
As a gate electrode, phosphorus-doped silicon was formed to a thickness of 0.2 μm, and molybdenum was formed thereon to a thickness of 0.3 μm.

In FIG. 2(C), a photoresist (31") is formed using a photomask ■, and a source for PTFT (5") is formed using a photomask.
), boron I Xl015c for the drain (6)
A dose of F2 was added by ion implantation.

Next, as shown in FIG. 6(D), a photoresist (31) was formed using a photomask (2).Then, phosphorus was used as the source (5') and drain (6'') for the NTFT.
The amount of I5Cm-'' was added by ion implantation.

These were performed through the gate insulating film (3). However, in FIG. 6B, the silicon oxide on the silicon film may be removed using the gate electrodes (4), (4°) as a mask, and then boron and phosphorus ions may be directly implanted into the silicon film.

Next, heat annealing was performed again at 600° C. for 10 to 50 hours. And the source (5) and drain (6) of PTFT.
).

The source (5°) and drain (6°) of the NTFT were fabricated as P''' and N2 by activating impurities.

Furthermore, channel forming regions (7), (7') are formed as semi-amorphous semiconductors under the gate electrodes (4), (4').

In this way, even though it is a self-line system, the 70
C/T without adding any temperature above 0°C
You can make a PT. Therefore, as a substrate material,
This process does not require the use of expensive substrates such as quartz, and is extremely suitable for the large pixel liquid crystal display device of the present invention.

Thermal annealing was performed twice in FIGS. 6(A) and (D). However, the annealing shown in FIG. 6(A) may be omitted depending on the desired characteristics, and both may be performed by the annealing shown in FIG. 6(D) in order to shorten the manufacturing time. In FIG. 6(E), the glabellar insulator (8) was formed as a silicon oxide film by the sputtering method described above. This silicon oxide film is formed using LPCV.
D method and photo-CVD method may be used. For example, 0.2 to 0.
It was formed to have a thickness of 4 μm. Thereafter, a window (32) for an electrode was formed using a photomask (3).

Furthermore, aluminum is formed on all of these by sputtering, leading to leads (9), (9°) and contacts (2).
9) and (29') were produced using a photomask ■.

Furthermore, as shown in Figure 6(F), in order to make the two TPTs complementary and to connect their output ends to one transparent electrode of the liquid crystal device, ITO (indium tin oxide film) was formed by sputtering. . This was etched using a photomask (3) to form an electrode (33). This ITO
The film was formed at room temperature to 150°C, and annealing was performed at 200 to 400°C in oxygen or air.

In this way, PTFT (21) and NTFT (11)
and the transparent conductive film electrode (33) on the same glass substrate (1).
made above.

The characteristics of such TPT will be abbreviated.

Mobility (μcm”/Vs) V th (V) PTFT
20 -3NTFT 30
+3 By using such a semiconductor, it was possible to create a large mobility in TPT, which was generally considered impossible. Therefore, for the first time, it was possible to construct a complementary TPT for a liquid crystal display device as shown in FIGS. 3 and 5.

“Example 2J FIG. 5(A) shows an embodiment corresponding to FIG. 3.

Voo (18), Vss (19), V, D in the X-axis direction
'(18") in the X-axis direction (J), also referred to as lower X-ray).
, y cco (23) A wiring in the Y-axis direction (hereinafter also referred to as Y line) was formed.

Drawing (A) is a plan view, or its longitudinal cross-sectional view along AA' is shown in FIG. 5(B). Further, a vertical cross-sectional view along line BB' is shown in FIG. 5(C).

M7': PTPT (21) is provided at the intersection of X-ray VDD (18) and Y-line V, , (22), and VDD (18) and V
,,' There is also a PTPT for other pixels at the intersection with (23).
(21°) or similar. Also, NTFT(1
1) is Vs, (19) and ■. , (22). Vsl+(19) and V. NTFT (11") for other pixels is provided below the intersection with G (22). It has a matrix configuration using C/TPT. These PTFTs are connected to the source (5). or connected to the X-ray VDD (18) via a contact (32);
The gate (4) is a multi-layered Y line VGc (22)
is connected to. The drain (6) is connected to the contact (29
) is connected to the electrode (33) of the transparent conductive film.

On the other hand, the source (5') of the NTFT is the contact (32)
' Connect to X-ray Vss (+9) through gate (
4°) The drain (6°) is connected to the Y line Vcc (22) and the transparent conductive film (33) via the contact (29”). , (19), a transparent conductive film and C/TPT constitute one pixel between (on the inside).By repeating this structure horizontally and vertically, an example of a 2×2 matrix construction is created. or enlarged to 640 x 480.1280
It became possible to create liquid crystal display devices with large pixels such as the X960.

The feature here is that one pixel is provided with two TPTs in a complementary configuration, and the electrode (33) constitutes the liquid crystal potential vLo, which means that the PTFT is on and the NTFT is off. , or PTFT is off and NTF
T is to be fixed at any level, whether it is on or not.

The operation will be briefly described using FIG.

In a pair of electrodes (33) and (34) sandwiching the liquid crystal (12), the other electrode (34) is set to the ground potential (13),
On the other hand, if VDD (19) is +7V, VS, (
For example, if 18) is -7V, VL-(10) is +7V
Or it will be fixed at -7v. That is, in contrast to the conventional liquid crystal device using only NTFTs as shown in FIG. 1, VLc is not floating but has a constant potential. That is, it is possible to set three types of potentials: VDDSVSS and ground, and it can be seen that the number of control elements has increased by one.

Therefore, even if either the PTFT (2) or the NTFT (11) in Fig. 4 becomes unnecessary and is in an open state or has a tendency to leak, even if it is destroyed with a laser and placed in an oven state, the damage will be halved or a certain amount will be lost. It has the feature of being able to drive the liquid crystal (12).

Furthermore, as is clear from Fig. 5, even if the control element Vss is newly increased, the aperture ratio of the liquid crystal device (the ratio of the area (33) of the liquid crystal actually displayed to the total area (34)) remains the same as before. TPT with only one conductivity type in Figure 1
This is exactly the same as when connecting each pixel to each pixel, and there is no disadvantage.

In addition, in Figure 5, if we consider the wiring of V, , (22), there is an aluminum wiring (4I) as an overline wiring (upper wiring), an underline wiring (43) made of the same material as the gate electrode (lower wiring), and an underline wiring (43) made of the same material as the gate electrode. By using wires) and their contacts (42), there is no need to increase the number of new photomasks for multilayer wiring at the intersection of X-rays and Y-lines.

In addition, in order to make the pair of electrodes (33) and (34) of the liquid crystal (12) more parallel and flat, aluminum wiring is applied in the step of FIG. 6(F), and then an organic resin such as polyimide is applied. What is necessary is just to form a flat plane using it, and to form a transparent conductive film on it. Furthermore, a transparent conductive film (3
Openings for contacts (3) are made using an additional photomask, and used to make contacts (29), , (29'
).

In FIG. 5, an alignment film and an alignment treatment are applied to these transparent conductive films, and a certain distance is left between this substrate and the other substrate having liquid crystal electrodes (FIG. 4 (34)). They were arranged with each other using the method described above.

During that time, the liquid crystal was injected and completed.

If TN liquid crystal is used as the liquid crystal material, the spacing should be approximately 10
It is necessary to form an alignment film on both sides of the transparent conductive film by rubbing.

When FLC (ferroelectric) liquid crystal is used as the liquid crystal material, the operating voltage is ±20V, and the cell spacing is 1.5V.
~3.5 .mu.m, for example 2.3 .mu.m, and the alignment film may be provided only on the opposite electrode (FIG. 4) (34) by rubbing treatment.

When using a dispersed liquid crystal or a polymer liquid crystal, an alignment film is not required, and in order to increase the switching speed, the operating voltage is ±10 to ±15V, and the cell spacing is 1 to 1Oμ.
I made it as thin as m.

In particular, when a dispersed liquid crystal is used, a polarizing plate is not required, so the amount of light can be increased whether it is a reflective type or a transmissive type. Since the liquid crystal does not have a threshold, using a C/TFT type with a clearly defined threshold voltage, as shown in the C/TPT of the present invention, increases contrast and prevents crosstalk (adverse interference with neighboring pixels). I was able to remove it.

In this embodiment 2, there is a PTF on the VDD side in the C/TPT.
NTFT was formed on the Vss side. Then, since the output produces VDD or Vss, a clear level can be determined. But vo. For this, VLC becomes an inverter.

This vo. This shows the case where V LC and V LC are in phase (electrodes in the same direction).

"Example 3" This example is C/TPT Nioiite, v0 side + knee N
TFT and PTFT were connected to the Vss side. Then, its outputs v and c become in phase with v6o, and its output potential is given by Vca Vth. Thus V. .

Although there is a drawback that VDD must be made larger than vDD, it has the advantage that there is no need to worry too much even if there is some leakage between the gate electrode and VLC.

In such a case, in FIG. 3, FTFT (21) and NT
What is necessary is just to provide it mutually oppositely to FT (11). That is, in FIG. 5 as well, the PTFT and NTFT may be provided oppositely to each other. Therefore, the manufacturing process and aperture ratio in Example 2 and FIG. 5 can be made to have exactly the same values.

"Effects of the Invention" By connecting complementary TPTs to each matrixed pixel, the present invention achieves the following: 1) Clarification of threshold value 2) Increase in switching speed 3) Expansion of operating margin 4) Elimination of defective TPTs 5) The number of photomasks required for fabrication is larger than that of the conventional example using only NTFT, as shown in Figure 6 (C) and (D).
6) As a pattern, even if two TPTs are attached to a pixel, the aperture ratio hardly decreases.

Therefore, compared to conventional active TPT liquid crystal devices, it has become possible to achieve several steps higher manufacturing yield and screen clarity.

In the present invention, semi-amorphous or semi-crystal was used as the semiconductor for the C/TPT. However, semiconductors with other crystal structures may be used for the same purpose if possible. Also, self-line type C/TP
High-speed processing was performed by using T. However, it goes without saying that the TPT may be made by a non-self-line method without using the ion implantation method.

[Brief explanation of the drawing]

FIG. 1 shows a crystal device using a conventional active type TPT (thin film transistor). 2 and 3 show circuit diagrams of an active liquid crystal device using a complementary TPT according to the present invention. FIG. 4 is a diagram showing the operation of the complementary TPT. FIG. 5 shows a plan view (A), longitudinal sectional view (B), and (C) of one substrate of a liquid crystal display device corresponding to FIG. 3. FIG. 6 shows a method for manufacturing a complementary TPT used in the liquid crystal device of the present invention. (1)...Glass substrate (2), (2'')...Silicon semiconductor (3)...
Gate insulating film (3°)...Blocking layer (4), (4°)...Gate electrode (5), (5'')...Source (6), (6°)...Drain (7) , (7°)...Channel formation region (10)...
...Liquid crystal potential (V,.) (11)...N-channel thin film transistor (NT
FT) (12)...Liquid crystal (14), (15) ・Resistance that causes leakage (16)
), (17) ・Peripheral circuit (18), (18°)-VS, (one of the X-rays) (19
), (19°)・VD, (〃)(21)...P-channel thin film transistor (PTFT) (22), (2
3) -VG,,VG,' (Y line) (33), (34)
・Transparent electrode

Claims (1)

[Claims] 1. In a liquid crystal display device having a matrix configuration,
A liquid crystal display device characterized in that each pixel is provided with a P-channel thin film transistor and an N-channel thin film transistor in a complementary configuration, and the output of the complementary thin film transistor is connected to the pixel. 2. In a liquid crystal display device having a matrix configuration,
Each pixel is provided with a P-channel thin film transistor and an N-channel thin film transistor in a complementary configuration, the output of the complementary thin film transistor is connected to the pixel, and the complementary transistor has a P-channel thin film transistor on the positive power supply voltage side. A liquid crystal display device characterized in that the source of an N-channel thin film transistor is provided on the ground side or the negative power supply voltage side.