JPH04176116A - Semiconductor crystal and manufacture thereof - Google Patents
Semiconductor crystal and manufacture thereofInfo
- Publication number
- JPH04176116A JPH04176116A JP30328390A JP30328390A JPH04176116A JP H04176116 A JPH04176116 A JP H04176116A JP 30328390 A JP30328390 A JP 30328390A JP 30328390 A JP30328390 A JP 30328390A JP H04176116 A JPH04176116 A JP H04176116A
- Authority
- JP
- Japan
- Prior art keywords
- compound semiconductor
- semiconductor
- layer
- compound
- crystal according
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 94
- 239000013078 crystal Substances 0.000 title claims abstract description 44
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 7
- 150000001875 compounds Chemical class 0.000 claims abstract description 63
- 238000000034 method Methods 0.000 claims abstract description 11
- 238000003776 cleavage reaction Methods 0.000 claims abstract description 4
- 230000007017 scission Effects 0.000 claims abstract description 4
- 238000005530 etching Methods 0.000 claims description 17
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 8
- 238000010438 heat treatment Methods 0.000 abstract description 5
- 229910052681 coesite Inorganic materials 0.000 abstract description 4
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 4
- 239000000377 silicon dioxide Substances 0.000 abstract description 4
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 4
- 229910052682 stishovite Inorganic materials 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 abstract description 4
- 229910052905 tridymite Inorganic materials 0.000 abstract description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 abstract description 3
- 230000000694 effects Effects 0.000 abstract description 3
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 230000001105 regulatory effect Effects 0.000 description 2
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229940125904 compound 1 Drugs 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010494 dissociation reaction Methods 0.000 description 1
- 230000005593 dissociations Effects 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 125000005842 heteroatom Chemical group 0.000 description 1
- KHFKVZRCWXCDMY-UHFFFAOYSA-N hydrogen peroxide hydrochloride hydrofluoride Chemical compound OO.F.Cl KHFKVZRCWXCDMY-UHFFFAOYSA-N 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 238000010301 surface-oxidation reaction Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は量子細線を有する半導体結晶の構造およびその
製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a structure of a semiconductor crystal having quantum wires and a method for manufacturing the same.
（従来の技術）
電子、正孔をド・ブロイ波長以下の空間に閉じ込めると
、量子学的な振舞いを示すようになる。(Prior art) When electrons and holes are confined in a space below the de Broglie wavelength, they begin to exhibit quantum behavior.
また、化合物半導体においてはエピタキシャル成長によ
り、膜厚方向での組成を変えて、電位障壁を作ることが
容易である。そのため、膜厚方向で電子、正孔を閉じ込
め量子井戸レーザ等の素子が実現されている。これに加
えて、面内方向でも閉じ込めができれば、電子、正孔は
２次元で量子化され、量子細線となる。従来の量子細線
は収束イオンビームによるバターニング（応物予稿集、
９〇−春−３，３１ａ−ｄ−１０） 、電子ヒーム露光
によるバターニング（応物予稿集、９〇−春一３．３１
ａ−ｄ−１１） 、−１１−ピタキシャル成長時のファ
セット面を用いる方法（応用物理、Ｖｏ ｌ。Further, in compound semiconductors, it is easy to create a potential barrier by changing the composition in the film thickness direction by epitaxial growth. Therefore, devices such as quantum well lasers have been realized in which electrons and holes are confined in the film thickness direction. In addition to this, if confinement can be achieved in the in-plane direction, electrons and holes will be quantized in two dimensions and become quantum wires. Conventional quantum wires are patterned using a focused ion beam (Obori Proceedings,
90-Spring-3, 31a-d-10), Buttering by electronic beam exposure (Obutsu Proceedings, 90-Haruichi 3.31)
ad-11), -11-Method using facets during pitaxial growth (Applied Physics, Vol.
５８、Ｎｏ、９．１９８９）等により作成されている。58, No. 9.1989).
しかし、」１記従来の技術には以下のような問題点があ
る。すなわち、バターニングにより横方向の閉じ込め構
造を作成する方法では、リソグラフィーや、サイドエツ
チングの制御性が十分でないため、室温で量子細線動作
をおこなうための１−〇ｎｍ程度の線幅を実現すること
が困難である。また、ファセット面を利用する方法にお
いては、選択エピタキシャル成長によるファセット形成
の難しさに加えて、縦方向の閉じ込めが不十分であると
いう問題がある。これはへテロ界面に形成される三角ポ
テンシャル中に電子を閉じ込めており、本来の矩形の量
子井戸構造とは異なり、表面電位によりポテンシャルの
深さが容易に失われてしまうためである。However, the conventional technology described in Section 1 has the following problems. In other words, the method of creating a lateral confinement structure by patterning does not provide sufficient controllability of lithography and side etching, so it is difficult to achieve a line width of about 1-0 nm for quantum wire operation at room temperature. is difficult. Further, in the method using facet planes, there is a problem that not only is it difficult to form facets by selective epitaxial growth, but also that vertical confinement is insufficient. This is because electrons are confined in the triangular potential formed at the hetero interface, and unlike the original rectangular quantum well structure, the depth of the potential is easily lost due to the surface potential.
（発明が解決しようとする課８）
本発明においては、２次元のいずれの方向にも十分な閉
じ込め効果を持つ量子細線を作製上の困難なく実現する
ことを目的とするものである。(Issue 8 to be solved by the invention) The present invention aims to realize a quantum wire having a sufficient confinement effect in any two-dimensional direction without any difficulties in manufacturing.
（課題を解決するための手段）
本発明によれば、上記問題点は、混晶化合物半導体の側
面に、これと混晶比の異なる化合物半導体からなる量子
細線を設けることで解決された。(Means for Solving the Problems) According to the present invention, the above problems are solved by providing quantum wires made of a compound semiconductor having a different mixed crystal ratio on the side surface of a mixed crystal compound semiconductor.
すなわち、本発明は、第１の化合物半導体と第２の化合
物半導体の混晶からなる第３の化合物半導体の側面に、
表面と平行に、該第２の化合物半導体からなる量子細線
か設けられていることを特徴とする半導体結晶を提供す
るものである。That is, in the present invention, on the side surface of a third compound semiconductor made of a mixed crystal of a first compound semiconductor and a second compound semiconductor,
The present invention provides a semiconductor crystal characterized in that a quantum wire made of the second compound semiconductor is provided parallel to the surface.
さらに、本発明は、半導体上に、エピタキシャル成長に
より該第１の化合物半導体と該第２の化合物半導体を、
該第２の化合物半導体の厚さか該第２の化合物半導体に
おける電子、正孔のド・ブロイ波長以下であり、該第２
の化合物半導体の上下両面が該第１の化合物半導体で挟
まれるように積層構造に形成する工程と、
次ぎに、該積層構造の上面に絶縁膜を形成する工程と、
全体を劈開して側面を露出させる工程と、この側面にお
いて該第１の化合物半導体を該第２の化合物半導体に対
し、選択的にエツチングする工程と、
全体を熱処理して該第２の化合物半導体において上記選
択エツチングにより残された部分の一部を除いて、該第
１の化合物半導体と該第２の化合物半導体を無秩序化す
ることで該第３の化合物半導体を形成する工程と、
を含むことを特徴とする半導体結晶の製造方法を提供す
るものである。Furthermore, the present invention provides the first compound semiconductor and the second compound semiconductor by epitaxial growth on the semiconductor,
The thickness of the second compound semiconductor is equal to or less than the de Broglie wavelength of electrons and holes in the second compound semiconductor, and
forming a stacked structure such that the upper and lower surfaces of the compound semiconductor are sandwiched between the first compound semiconductor; next, forming an insulating film on the upper surface of the stacked structure; and cleaving the entire structure to separate the side surfaces. exposing the first compound semiconductor, selectively etching the first compound semiconductor with respect to the second compound semiconductor on this side surface, and heat-treating the whole to remove the etching remaining in the second compound semiconductor by the selective etching. forming the third compound semiconductor by disordering the first compound semiconductor and the second compound semiconductor, excluding a part of the semiconductor crystal. A manufacturing method is provided.
（作用）
本発明の量子細線構造は、エピタキシャル成長により膜
厚方向に量子化した量子井戸構造を基にし、この上に絶
縁膜を形成した後、劈開によって側面を露出させ、この
側面において井戸部分を残し、障壁部分を取り去る選択
エツチングを施した後、全体を熱処理することで実現さ
れている。(Function) The quantum wire structure of the present invention is based on a quantum well structure quantized in the film thickness direction by epitaxial growth. After forming an insulating film thereon, the side surface is exposed by cleavage, and the well portion is formed on this side surface. This is achieved by performing selective etching to remove the remaining barrier parts, and then heat treating the entire structure.
絶縁膜を残したまま熱処理することで、量子井戸構造が
無秩序化されるが、絶縁膜で覆われていない部分、つま
り、選択エツチングで残された井戸部分だけは、無秩序
化されないので、量子細線として残る。したがって、エ
ピタキシャル成長の膜厚が量子細線の厚みを選択エツチ
ングのエツチング深さが量子細線の横幅を決めることに
なる。By heat-treating with the insulating film left in place, the quantum well structure becomes disordered, but only the part not covered by the insulating film, that is, the well part left by selective etching, is not disordered, so the quantum well structure becomes disordered. remains as. Therefore, the thickness of the epitaxially grown film determines the thickness of the quantum wire, and the etching depth of the etching determines the width of the quantum wire.
（実施例） 以下、本発明を図示の実施例を参照して説明する。(Example) Hereinafter, the present invention will be explained with reference to illustrated embodiments.
第１図は本発明による半導体結晶の断面図であって、Ｇ
ａＡｓ基板１上の実質的にＡ Ｉ Ｇ ａ １−ＸＡ
ｓからなる層２の側面にＧａＡｓからなる量子細線３が
設けられている。この量子細線３は後述の方法により厚
さが１０±１− ｎ ｍ 、幅は１０−１、５ ｎ ｍ
と極めて良く制御されている。なお、最上層の５ＩＯ２
層４は取り去られていてもよい。FIG. 1 is a cross-sectional view of a semiconductor crystal according to the present invention, in which G
Substantially A I Ga 1-XA on aAs substrate 1
A quantum wire 3 made of GaAs is provided on the side surface of the layer 2 made of s. This quantum wire 3 has a thickness of 10±1-nm and a width of 10-1.5 nm by the method described below.
and is extremely well controlled. In addition, the top layer 5IO2
Layer 4 may also be removed.
第２図は上記構造を得るための製造方法を示す。FIG. 2 shows a manufacturing method for obtaining the above structure.
ＭＢＥ法により、第２図（ａ）に示す量子井戸を作成す
る。このときＡＩ Ｇａ Ａｓ層の混晶Ｘ
］−Ｘ
比、Ｘを０．３とした。さらに下層のＡＩ Ｇａ１−
ｘＡｓＡｓ層５さを１μｍ、ＧａＡｓｊｉｔ子井戸層３
ａの厚みを１．Ｏｎｍ、Ｊ１層のＡ Ｉ Ｇ ａ 、
。A quantum well shown in FIG. 2(a) is created by the MBE method. At this time, the mixed crystal X of the AI Ga As layer
]-X ratio, X was set to 0.3. Even lower layer AI Ga1-
xAsAs layer 5 with a thickness of 1 μm, GaAsjit well layer 3
The thickness of a is 1. Onm, A I Ga of J1 layer,
.
Ａｓ層６の厚さを０．１μｍとした。基板はく１００〉
方向のＧａＡｓを用い、また上部の５ｉＯ２４はＣＶＤ
法で形成し、その膜厚を２００ｎｍとした。つぎに第２
図（ｂ）に示すように、劈開により端面７を形成したの
ち、塩酸−ふっ酸−過酸化水素系のエツチング液により
、 ＧａＡｓ層３ａに対し、ＡＩ Ｇａ Ａｓ層
５．６の端面 ＬＸ
を選択的にエツチングした。エツチング深さは１５ｎｍ
とした。これにより、ＧａＡｓ層３ａの突出部８が形成
される。これだけでは、ＧａＡｓ突出部８中のキャリア
は、図の左方向への移動が自由なため、量子細線とはな
っていない。したがって、この後Ｓ ｉＯ２層４をつけ
たまま、全体を水素ガス中で熱処理をする。この熱処理
において水素ガス流量３−５ρ／分、温度は６００−８
００℃とした。端面７からのＡｓの解離を防ぐため、ウ
ェハの上下および周囲を別のＧａＡｓウェハ（図示しな
い）で囲んだ。The thickness of the As layer 6 was set to 0.1 μm. Substrate foil 100>
5iO24 on the top is CVD
The film thickness was set to 200 nm. Then the second
As shown in Figure (b), after forming the end face 7 by cleavage, the end face LX of the AI GaAs layer 5.6 is selected from the GaAs layer 3a using a hydrochloric acid-hydrofluoric acid-hydrogen peroxide etching solution. It was etched. Etching depth is 15nm
And so. As a result, protrusions 8 of the GaAs layer 3a are formed. With this alone, the carriers in the GaAs protrusion 8 are free to move to the left in the figure, and therefore do not form a quantum wire. Therefore, after this, the entire structure is heat-treated in hydrogen gas with the SiO2 layer 4 still attached. In this heat treatment, the hydrogen gas flow rate was 3-5ρ/min, and the temperature was 600-8
The temperature was 00°C. In order to prevent dissociation of As from the end face 7, the wafer was surrounded above and below and around it with another GaAs wafer (not shown).
上述の熱処理を施すと、Ｓ ｉ ０２層４の応力のため
に、ＧａＡｓ層３ａと、ＡＩ Ｇａ ＡｓＸ
ＬＫ
層５．６との間で無秩序化が進み、第２図（ｂ）に示す
ように、この部分のＧａＡｓ層３ａが消滅して全体がＡ
Ｉ ｒ Ｇ ａ ｔ Ａ ｓ層３ｂになる。When the above-mentioned heat treatment is performed, due to the stress in the SiO2 layer 4, the GaAs layer 3a and the AI GaAsX
The disorder progresses between the GaAs layer 5.6 and the GaAs layer 3a in this part, as shown in FIG. 2(b), and the entire GaAs layer 3a disappears.
This becomes the IrGatAs layer 3b.
ｘ ｌ−ｘ
このとき、ＧａＡｓ層３ａはＡＩ Ｇａ ＡＸ
１−Ｘ
８層５．６に比べ圧倒的に薄いので、無秩序化の後の組
成Ｘ′はＸに極めて近いものとなり、これら層全体の混
晶比は表面から垂直方向に変化しているがＡＩ Ｇａ
Ａｓと見做すことができる。x l-x At this time, the GaAs layer 3a is AI Ga AX
Since the 1-X 8 layer is overwhelmingly thinner than the 5.6 layer, the composition X' after disordering is extremely close to X, and the mixed crystal ratio of these layers as a whole changes in the vertical direction from the surface. AI Ga
It can be regarded as As.
ｌｘ
このとき、Ｃ；ａＡｓ突出部（量子細線）８は応力の影
響を受けないので、無秩序化を免れ、熱処理後もＧａＡ
ｓのままとなり、量子細線３が形成される。このように
して第１図に示す量子細線３を有する半導体結晶構造を
作成することができる。lx At this time, since the C;aAs protrusion (quantum wire) 8 is not affected by stress, it escapes from disordering and remains GaA even after heat treatment.
s remains, and a quantum wire 3 is formed. In this way, a semiconductor crystal structure having the quantum wire 3 shown in FIG. 1 can be created.
この構造においてはＧａＡｓｆｔ子細線３の右側は空間
、左側はよりバンドギャップの大きいＡｌｒＧａ
ＪＡＳ層３ｂであるため、キャリアーＸ ］−１
はほぼ完全に閉じ込められ、量子力学的振舞いをするよ
うになる。In this structure, the right side of the GaAsft thin wire 3 is space, and the left side is AlrGa with a larger band gap.
Since it is the JAS layer 3b, the carriers X]-1 are almost completely confined and behave quantum mechanically.
以上のようにして、量子細線の導伝型か、これと隣接す
る化合物半導体層と異なり、また量子細線のキャリア濃
度かそれと隣接する化合物半導体層のものと異なるもの
を得ることかできる。なお、突出部（量子細線）８はＡ
ｌｘ′Ｇａ ＋ＡｓＸ ＬＸ
層３ｂより小さい混晶比ｘ″を持つ、ＡＩ 、Ｇａ、
、、Ａｓ層であってもよい。 初めの量子井戸構造をＩ
ｎＰとＩｎ ＋Ｇａ 、Ａｓ 、Ｐｘ
Ｌｘ ｙ１□、で形成すれば同様に
してＩｎ Ｇａ ＡｓＸ １ｘ
ｙＰｌｙに基づく量子細線が得られる。このとき−］］
−
の端面の選択エツチングには塩酸系のエツチング液を用
いた。In the manner described above, it is possible to obtain a conduction type of the quantum wire that is different from that of the compound semiconductor layer adjacent thereto, and a carrier concentration of the quantum wire that is different from that of the compound semiconductor layer adjacent thereto. Note that the protrusion (quantum wire) 8 is A
lx'Ga + AsX LX AI, Ga, with a smaller mixed crystal ratio x'' than layer 3b,
, , an As layer. The first quantum well structure is I
nP and In+Ga, As, Px
If formed with Lx y1□, a quantum wire based on InGaAsX 1x yPly can be obtained in the same manner. At this time-]]
- A hydrochloric acid-based etching solution was used for selective etching of the edge faces.
本発明の第２の実施例を第３図を用いて説明する。第３
図は半導体結晶の断面図であって、Ａ１Ｇａ Ａｓ
層２の側面にＧａＡｓからなる多Ｘ Ｉ−Ｘ
重量子細線３が形成されている。この作り方は、エピタ
キシャル成長の際に多重量子井戸構造を形成しておくこ
とを除けば最初の実施例のものと同様の工程で製造する
ことかできる。なお、本図中、第１図と同一部分につい
ては同一符号を付すことにより、その説明を省略する。A second embodiment of the present invention will be described using FIG. Third
The figure is a cross-sectional view of a semiconductor crystal, A1GaAs
A multi-X I-X quantum thin wire 3 made of GaAs is formed on the side surface of the layer 2 . This method can be manufactured using the same steps as in the first embodiment except that a multiple quantum well structure is formed during epitaxial growth. In this figure, the same parts as in FIG. 1 are given the same reference numerals, and their explanation will be omitted.
本発明の第３の実施例を第４図に示す。これは、第１図
の構造の状態から、さらに端面にＡ、ＩＧａｌ−ｙ Ａ
Ｓ層９をエピタキシャル成長させて得られる。その他
については第１図の場合と同じである。この構造ではＧ
ａＡｓ１ｔ子細線３が、ＡｌｘＧａ Ａｓ層２およ
びＡｔ Ｇａ ＡｓＳ層］−Ｘ
Ｙ ］−Ｙに完全に埋め込まれるため、表面
酸化や表面電荷の影響を受けに＜＜、安定な量子細線が
得られる。A third embodiment of the invention is shown in FIG. This is because, from the state of the structure shown in Fig. 1, A and IGal-y A are added to the end face.
It is obtained by epitaxially growing the S layer 9. Other details are the same as in the case of FIG. In this structure, G
The aAs1t thin wire 3 is an AlxGaAs layer 2 and an AtGaAsS layer]-X
Since it is completely embedded in Y]-Y, a stable quantum wire can be obtained without being affected by surface oxidation or surface charge.
また、ＡＩ Ｇａ Ａｓ層２およびＡＩ Ｇａ
Ｘ ＬＸ ｙ＝ １２ ＝
ｌ−ｙ Ａ Ｓ層９の導伝型を逆にしておくと、この量
子細線３を活性層とする量子細線レーザにも応用できる
。In addition, the AI Ga As layer 2 and the AI Ga
X LX y= 12 = ly A If the conductivity type of the S layer 9 is reversed, it can also be applied to a quantum wire laser using the quantum wire 3 as an active layer.
つぎに本発明の第４の実施例を第５図に示す。Next, a fourth embodiment of the present invention is shown in FIG.
第５図も同じく半導体結晶の断面図であり、第１図と同
様に両側に量子細線３があるが、図では見えない向こう
側と、こちら側にも破線で示すごとく量子細線３が同様
に設けである。つまり、ＡｌＧａ Ａｓ層２の結晶
全体を取り巻くようにｘ ｌ−ｘ
量子細線３からなるリングが形成されている。この実施
例の構造のものは、エピタキシャル結晶の周囲全てを壁
間したのち、先に述べた選択エツチングと熱処理によっ
て形成される。その他の点については第１図の例と同一
である。この周囲を第４図に示すように、さらに別の結
晶で埋め込んでもよい。FIG. 5 is also a cross-sectional view of the semiconductor crystal, and there are quantum wires 3 on both sides as in FIG. It is a provision. That is, a ring made of x l-x quantum wires 3 is formed so as to surround the entire crystal of the AlGaAs layer 2 . The structure of this embodiment is formed by forming walls around the epitaxial crystal and then performing the selective etching and heat treatment described above. The other points are the same as the example shown in FIG. The surrounding area may be filled with another crystal as shown in FIG.
（発明の効果）
以」二詳述したように、本発明によれば、混晶化合物半
導体の側面に、これと混晶比の異なる化合物゛１と導体
からなる量子細線を設けるようにしたか＝ １３−
ら、エピタキシャル成長の膜厚により量子細線の厚みを
規制し、選択エツチングのエツチング深さにより量子細
線の横幅を規制するようにしたから、量子細線の厚み、
幅を極めて良好に制御することが可能となった。(Effects of the Invention) As described in detail below, according to the present invention, a quantum wire made of a conductor and a compound 1 having a different mixed crystal ratio from the mixed crystal compound semiconductor is provided on the side surface of the mixed crystal compound semiconductor. = 13- Since the thickness of the quantum wire is regulated by the film thickness of epitaxial growth, and the width of the quantum wire is regulated by the etching depth of selective etching, the thickness of the quantum wire,
It became possible to control the width extremely well.
第１図は本発明に係わる半導体結晶の側面図、第２図（
ａ）および第２図（ｂ）は第１図の半導体結晶を得るた
めの工程を説明するための側面図、第３図ないし第５図
は本発明の他の実施例に係わる半導体結晶の側面図であ
る。
図中、１・・・ＧａＡＳ基板、２−−−ＡＩＸＧａ
Ａｓ層、３・・・ＧａＡｓ層、３ａφ・−ｘ
ｔＧａＡｓ層、３ｂ・１Ａ１ 、Ｇａ 、ＡＸ
ＬＸ
Ｓ層、４・・・ＳｉＯ層、５．６−−−ＡＩＸＧａ
Ａｓ層、８・・・ＧａＡＳ突出部（量子］−Ｘ
細線）、９・・・ＡＩ Ｇａ Ａｓ層。
ｂｙ
第１図
第２図（ａ）
第 ２図（ｂ）
第３図Figure 1 is a side view of a semiconductor crystal according to the present invention, and Figure 2 (
a) and FIG. 2(b) are side views for explaining the process for obtaining the semiconductor crystal of FIG. 1, and FIGS. 3 to 5 are side views of semiconductor crystals according to other embodiments of the present invention. It is a diagram. In the figure, 1...GaAS substrate, 2---AIXGa
As layer, 3...GaAs layer, 3aφ・-xtGaAs layer, 3b・1A1, Ga, AX
LX S layer, 4...SiO layer, 5.6---AIXGa
As layer, 8...GaAS protrusion (quantum)-X thin line, 9...AI GaAs layer. by Figure 1 Figure 2 (a) Figure 2 (b) Figure 3
Claims (13)
からなる第３の化合物半導体の側面に、表面と平行に、
該第２の化合物半導体からなる量子細線が設けられてい
ることを特徴とする半導体結晶。(1) On the side surface of a third compound semiconductor made of a mixed crystal of a first compound semiconductor and a second compound semiconductor, parallel to the surface,
A semiconductor crystal characterized in that a quantum wire made of the second compound semiconductor is provided.
導体が少なくとも該第３の化合物半導体の側面に設けら
れていることを特徴とする請求項１記載の半導体結晶。(2) The semiconductor crystal according to claim 1, wherein a fourth compound semiconductor is provided at least on a side surface of the third compound semiconductor so as to embed the quantum wire.
て他の半導体上に設けられていることを特徴とする半導
体結晶。(3) A semiconductor crystal, characterized in that the semiconductor crystal according to claim 1 or 2 is provided as a whole on another semiconductor.
方向で変化していることを特徴とする請求項１ないし３
のいづれかに記載の半導体結晶。(4) Claims 1 to 3 characterized in that the mixed crystal ratio of the third compound semiconductor changes in a direction perpendicular to the surface.
The semiconductor crystal according to any one of.
と接する部分の該第３の化合物半導体のバンドギャップ
より小さいことを特徴とする請求項１ないし４のいづれ
かに記載の半導体結晶。(5) The semiconductor crystal according to any one of claims 1 to 4, wherein the bandgap of the second compound semiconductor is smaller than the bandgap of the third compound semiconductor in a portion in contact with the second compound semiconductor.
部分の該第３の化合物半導体の導伝型と異なることを特
徴とする請求項１ないし５のいづれかに記載の半導体結
晶。(6) The semiconductor crystal according to any one of claims 1 to 5, wherein the conductivity type of the second compound semiconductor is different from the conductivity type of the third compound semiconductor in a portion in contact with the second compound semiconductor.
接する部分の該第３の化合物半導体のキャリア濃度と異
なることを特徴とする請求項１ないし６のいづれかに記
載の半導体結晶。(7) The semiconductor crystal according to any one of claims 1 to 6, wherein the carrier concentration of the second compound semiconductor is different from the carrier concentration of the third compound semiconductor in a portion in contact with the second compound semiconductor.
設けられていることを特徴とする請求項１ないし７のい
づれかに記載の半導体結晶。(8) The semiconductor crystal according to any one of claims 1 to 7, characterized in that a plurality of quantum wires are provided spaced apart from each other in the vertical direction.
されたものであることを特徴とする請求項１ないし８の
いづれかに記載の半導体結晶。(9) The semiconductor crystal according to any one of claims 1 to 8, wherein the side surface of the third compound semiconductor is formed by cleavage.
の側面に該量子細線が設けられていることを特徴とする
請求項１ないし９のいづれかに記載の半導体結晶。(10) The semiconductor crystal according to any one of claims 1 to 9, wherein the quantum wire is provided on all sides around the surface of the third compound semiconductor.
＿−＿ｘ＿′Ａｓ、該第２の化合物半導体がＡｌ＿ｘ＿
′Ｇａ＿１＿−＿ｘ＿′Ａｓよりも小さい混晶比ｘ″を
持つＡｌ＿ｘ＿″Ｇａ＿１＿−＿ｘ＿″ＡｓあるいはＧ
ａＡｓであることを特徴とする請求項１ないし１０のい
づれかに記載の半導体結晶。(11) The third compound semiconductor is Al_x_'Ga_1
_-_x_'As, the second compound semiconductor is Al_x_
'Ga_1_-_x_'As or G with a smaller mixed crystal ratio x'' than 'Ga_1_-_x_'As
11. The semiconductor crystal according to claim 1, wherein the semiconductor crystal is aAs.
＿ｘＡｓ＿ｙＰ＿１＿−＿ｙ、該第２の化合物半導体が
Ｉｎ＿ｘ＿′Ｇａ＿１＿−＿ｘ＿′Ａｓ＿ｙ＿′Ｐ＿１
＿−＿ｙ＿′であり、ｘ′がｘよりも大きく、ｙ′がｙ
よりも大きいことを特徴とする請求項１ないし１０のい
づれかに記載の半導体結晶。(12) The third compound semiconductor is In_xGa_1_-
_xAs_yP_1_-_y, the second compound semiconductor is In_x_'Ga_1_-_x_'As_y_'P_1
＿−＿y＿′, x′ is greater than x, and y′ is y
11. The semiconductor crystal according to claim 1, wherein the semiconductor crystal is larger than .
の化合物半導体と該第２の化合物半導体を、該第２の化
合物半導体の厚さが該第２の化合物半導体における電子
、正孔のド・ブロイ波長以下であり、該第２の化合物半
導体の上下両面が該第１の化合物半導体で挟まれるよう
に積層構造に形成する工程と、 次ぎに、該積層構造の上面に絶縁膜を形成する工程と、 全体を劈開して側面を露出させる工程と、 この側面において該第１の化合物半導体を該第２の化合
物半導体に対し、選択的にエッチングする工程と、 全体を熱処理して該第２の化合物半導体において上記選
択エッチングにより残された部分の一部を除いて、該第
１の化合物半導体と該第２の化合物半導体を無秩序化す
ることで該第３の化合物半導体を形成する工程と、 を含むことを特徴とする請求項１ないし１２のいづれか
に記載の半導体結晶の製造方法。(13) The first layer is grown on the semiconductor by epitaxial growth.
and the second compound semiconductor, the thickness of the second compound semiconductor is equal to or less than the de Broglie wavelength of electrons and holes in the second compound semiconductor, and forming a stacked structure such that both sides are sandwiched by the first compound semiconductor; next, forming an insulating film on the top surface of the stacked structure; cleaving the entire structure to expose the side surfaces; In this aspect, a step of selectively etching the first compound semiconductor with respect to the second compound semiconductor, and heat-treating the whole, and a part of the second compound semiconductor remaining by the selective etching. and forming the third compound semiconductor by disordering the first compound semiconductor and the second compound semiconductor, except for the step of forming the third compound semiconductor. A method for manufacturing the semiconductor crystal described above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30328390A JPH04176116A (en) | 1990-11-08 | 1990-11-08 | Semiconductor crystal and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30328390A JPH04176116A (en) | 1990-11-08 | 1990-11-08 | Semiconductor crystal and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04176116A true JPH04176116A (en) | 1992-06-23 |
Family
ID=17919096
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30328390A Pending JPH04176116A (en) | 1990-11-08 | 1990-11-08 | Semiconductor crystal and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04176116A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6294450B1 (en) * | 2000-03-01 | 2001-09-25 | Hewlett-Packard Company | Nanoscale patterning for the formation of extensive wires |
-
1990
- 1990-11-08 JP JP30328390A patent/JPH04176116A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6294450B1 (en) * | 2000-03-01 | 2001-09-25 | Hewlett-Packard Company | Nanoscale patterning for the formation of extensive wires |
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