JPH04175676A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To make it unnecessary to use a selector circuit during test operation by providing means for writing the output signal of a programmable logic array for test patterns on a RAM and for reading out to the external the output signal written on the RAM. CONSTITUTION:An LSI 101 has a PLA 121 and the RAM 106 installed therein. The test operation of the PLA 121 is controlled by a test control signal 33. PLA test input patterns are written on the RAM 106. Next the PLA test input patterns are read out from the RAM 106 and latched in a data latch 131. A selector 111 selects one PLA test input pattern. The PLA 121 outputs a PLA output 21 for the PLA test input pattern selected. The PLA output 21 is latched in a data latch 141 and written on the RAM 106. All of the PLA output data stored on the RAM 106 is analyzed and the PLA 121 is tested.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit in which a built-in programmable logic array can be tested.

[Conventional technology]

Conventionally, when testing a programmable logic array (hereinafter referred to as PLA) built in a semiconductor integrated circuit (hereinafter referred to as LSI), as shown in FIG.
Inside 101a, there is a normal P that is the PLA input during normal operation.
LA input 11, 12゜13 and input terminal 2 during test operation
selectors 111, 112, 113 for selecting one of the test human inputs 41 inputted from the input signal, and the normal output signal 15 and PLA 121 that are output to the output terminal 103 during normal operation.
．． 122, 123, PLA output 21.22.
A selector 114 for selecting one of the 23 is required.

During normal operation, the normal input signal 14 is input to the input terminal 102 . Selectors 111, 112, and 113 select normal PLA inputs 11, 12, and 13, respectively. The selector 114 selects the normal output signal 15,
A normal output signal 15 is output to the output terminal 103.

During the test operation, the test human power 41 is sequentially input to the input terminal 102. Selector 111゜112.11
3, the test control signal 31 causes the normal PLA input 11,
12.13 and test input 41 respectively test human power 41
is selected. The test human power 41 is input to the PLA 121, 122, 123, and the PLA outputs 21, 22, 23 are pressurized.

The PLA pressure 2L 22, 23 and the normal output signal 15 are input to the selector 114, and the PLA pressure is input by the test control signal 32.
Select one of the LA outputs 21, 22, and 23. The pressure terminal 103 has P selected by the selector 14.
LA output is output.

The PLA was tested by repeating this operation.

FIG. 16 shows the timing of the PLA test input signal 41 and the PLA output signals 21, 22, and 23.

The PLA test input signal 41 is determined by the rising edge of the system clock, and the PLA test input signal 41 is determined by the rising edge of the system clock.
23 samples the PLA test input signal during the active period of the system clock.

The PLA output signals 21, 22, 23 are delayed from the rising edge of the system clock. AAAA, BEBB, and CCCC of the PLA test input signal 42 are each PL.
A output signals 21, 22, 23 aaaa, bbbb, c
Compatible with ccc.

[Problem to be solved by the invention]

In the conventional semiconductor integrated circuit described above, when testing the built-in PLA, the normal output terminal is used during the test operation, so the PL during the test operation of the output signal during normal operation is
A selector is required as means for selecting the A output signal according to each operation. In addition, the output signal during normal operation passes through the selector and is output from the output terminal, which has the disadvantage of degrading performance.

An object of the present invention is to provide an LS system that eliminates the need for means for selecting an output signal during normal operation and a PLA pressure signal during test operation according to each operation, and does not deteriorate the performance of the pressure circuit during normal operation.
The object of the present invention is to provide a semiconductor integrated circuit that can be tested.

[Means to solve the problem]

The semiconductor integrated circuit of the present invention is a semiconductor that tests the programmable logic array by switching from a normal PLA input signal and inputting a test input to one or more built-in programmable logic arrays through a selector controlled by a test control signal. In an integrated circuit, means for generating a test input pattern for testing the programmable logic array, a RAM for writing an output signal of the programmable thick array in response to the test input pattern, and a means for generating the pressure signal written by the RAM. and the means for reading out to the outside.

Further, the semiconductor integrated circuit of the present invention includes one or more programmable logic arrays and a built-in RAM, and includes means for externally writing a test input pattern for testing the four-gram logic array into the RAM; means for reading a pattern from the RAM and inputting it into the programmable logic array; means for writing an output signal of the programmable array in response to the test input pattern into the RAM; means for outputting the output signal to the outside; and normal operation and testing. The test operation is set to the test operation by the switching means, and the programmer full-cossock array is tested.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an LSI according to a first embodiment of the present invention,
FIG. 2 is a diagram showing the structure of the address space of the RAM shown in FIG. 1. As shown in FIG.
Selectors 111, 112° 113, and data latches 131, 13 are installed inside the LSllol that incorporates AM106.
2,133°141.142,143.

In FIG. 1, a test control signal 33 starts a PLA test operation. Which PLA is tested is controlled by a test control signal 33.

The test operation of the PLAI 21 will be explained below as an example.

The PLA test input pattern on the data bus 110 is transmitted to the internal data bus 109 via the input/output buffer 108 and the bus interface circuit 107 according to the test control signal 33.
be taken in. Built-in RAM by test control signal 33
Write signals and addresses are generated on the internal data bus 10.
The PLA test input pattern on 9 is sequentially transferred to built-in RAM10.
6 is written.

The configuration of the RAM address space of the built-in RAM 106 is shown in Figure 2, where the test input pattern storage area and PL
A output meter storage area is separated. Internal MRI
When the test input pattern has been stored in 06, it is stored in the built-in RAM 10 by the built-in RAM read signal and the address.
The test input pattern on 6 is read out to the internal bus 109 and latched into the data latch 131 by the PLA input side data latch strobe signal, which is one of the test control signals 33. The selector 111 has a regular PLA input 11.
A PLA test input pattern, which is a data latch 131af, is input, and the PLA test input pattern is selected.

The PLA 121 outputs eight PLA outputs 21 for the PLA test input pattern. The PLA output 21 is latched into the data latch 141 by the PLA output side data latch strobe signal, which is one of the test control signals 33.
It is output to internal data bus 109. Test control signal 3
3 generates the internal RAM write signal and address, and the PLA output 21 on the internal data bus 109 outputs the internal RAM write signal and address.
The data is written to the PLA output data storage area 106. By repeating this operation, the PLA specific forces 21 for all PLA test input patterns of the PLA 121 are sequentially written into the built-in RAM.

Next, the test control signal 33 generates a data output control signal from the built-in RAM 106 to the internal data bus 109, whereby the PLA output data on the PLA output data storage area of the built-in RAM 109 is sequentially transferred to the internal data bus 109.
bus interface circuit 107. It is output to the external data bus via the input/output buffer 108.

PLA can be tested by analyzing this data.

FIG. 3 shows the timing of the PLA test input pattern writing operation, FIG. 4 shows the timing of the test operation, and FIG. 5 shows the timing of the PLA output data pressing operation.

In FIG. 3, external data bus AAAA becomes internal data bus AAAA, and when the built-in RAM write signal is active, data is written to address xxxx in the built-in RAM.

In FIG. 4, when the built-in RAM call pressure signal is active, the PLA test input pattern is read from the address xxxx of the built-in RAM and becomes the internal data bus AAAA, and when the PLA input side data latch strobe signal is active, the internal data bus Latch AAAA and PLA
The input pattern becomes AAAA. The PLA outputs PLA output data aaaa. PLA ratio data aaaa is P
When the LA output side data latch strobe signal is active, it is latched and becomes the internal data bus aaaa. The internal data bus aaaa is written to the address UUUU of the built-in RAM when the write 1 signal is active.

In FIG. 5, when the built-in RAM read signal is active, PLA output data is read from the address UUUU of the built-in RAM and becomes the internal data bus aaaa, which becomes the external data bus aaaa.

FIG. 6 is a diagram showing the structure of the address space of the built-in RAM according to the second embodiment of the present invention. As shown in FIG. 6, the address space of the built-in RAM of this embodiment is not divided into a test input pattern storage area and a PLA soil force data storage area, but other components are the same as in the first embodiment. be.

In FIGS. 1 and 6, the test control signal 33
Start LA test operation. The difference between the first embodiment and the second embodiment is that in the first embodiment, the built-in RAM 1
The address space of 06 is designated as the test input pattern storage area and P
In contrast, in this embodiment, the built-in RAM 10 is used for storing test input patterns.
6 address spaces can be used, and the PLA output 21 for the PLA test input pattern is stored in the built-in RAM 106.
The point is to write to the address where the PLA test input pattern is stored. Other operations are the same as in the first embodiment.

FIG. 7 shows the timing of the PLA test input pattern writing operation, FIG. 8 shows the timing of the test operation, and FIG. 9 shows the timing of the PLA output pattern extraction operation.

This embodiment has the advantage of being able to cope with tests using a large number of test input patterns and improving test efficiency by occupying the address space of the RAM when storing test input patterns and PLA ratio data.

FIG. 10 is a block diagram of an LSI according to a third embodiment of the present invention, and FIG. 11 is a block diagram of the test pattern generator of FIG. 10. As shown in FIG. 10, this embodiment has one or more PLAs 121, 122, 123 and
A test pattern generator 200 and selectors 111, 112, 113 are installed inside the LSI 101 containing M106.
and data latches 131, 132, and 133. The test pattern generator 200 also includes a counter 201.

In FIGS. 10 and 11, the test control signal 33.3
4 starts the PLA test operation.

Which PLA is tested is controlled by a test control signal 33. The test operation of the PLA 121 will be described below as an example.

The counter 201 is reset by a reset signal 332, which is one of the test control signals 33.

Next, the counter 201 operates according to the counter clock 331, which is one of the test control signals 33, and generates the PLA test input pattern 41. Selector 111 has PLA
The test input pattern 41 and the normal PLA input 11 are input, and the PLA test input pattern 41 is selected by the test control signal 33. The PLA 121 inputs the PLA test input pattern 41 and outputs the PLA output 21.

PLA output 21 is latched by data latch 131 and output to internal data bus 109 in response to test control signal 33. The built-in RAM address and built-in RAM write signal are generated by the test control signal 34, and the internal data/Q
The PLAffl force on the bus 109 is written to internal RAM.

By repeating this operation, all P of PLA121
PLA output 21 for LA test input pattern 41 is written to built-in RAM. Similarly, PLA122,
123 PLA outputs 22°23 are written to the built-in RAM. Next, a built-in RAM call signal from the built-in RAM to the internal data bus 109 and a data output control signal to the external data bus 109 are generated by the test control signal 34.
As a result, the PLA output data on the built-in RAM is called to the internal data bus 109, and the hash interface circuit 107. It is output to the external data bus via the input/output buffer 108. PLA can be tested by analyzing this data.

FIG. 12 shows signal timing during the test operation of FIG. 10. Test force 31 AAAA, BBBE, CCCC
are respectively PLA outputs 21. It corresponds to internal data buses and external data buses aaaa, bbbb, and cccc. Also, the internal data bus aaaa, bbbb, cc
cc corresponds to addresses indicated by XXXX, YYYY, and ZZZZ, respectively, and writing and reading from the built-in RAM are performed by built-in RAM write and read signals.

FIG. 13 is a diagram showing a test pattern generator according to a fourth embodiment of the present invention. As shown in FIG. 13, the test pattern generator 200 of this embodiment includes a RAM 202. Other components are the same as in the third embodiment.

In FIGS. 10 and 13, the test control signal 33.3
4 starts the PLA test operation.

A PLA test input pattern is written in the ROM 202 in advance, and the PLA test input pattern 41 is read from the ROM 202 in response to an address 333, which is one of the test control signals 33, and a read signal 334. The subsequent operation is the same as in the third embodiment.

FIG. 14 shows signal timing during test operation. AAAA, BBBB, and CCCC of test human power 31 are PLA output 21. It corresponds to the internal data bus 109 and external data buses aaaa, bbbb, and cccc.

In addition, test personnel 31 AAAA, BBBB, CCCC
is test ROM7 dress 333 UUUU, VVVV,
WWWW, internal data bus aaaa, bbbb.

CCCC corresponds to addresses indicated by XXXX, YYYY, and ZZZZ, and writing and reading from the built-in RAM are performed by built-in RAM write and read signals.

This embodiment has a test pattern generator 200 and a ROM 202.
R only the PLA test input pattern required in advance
By writing to OM202, unnecessary PL
There is no need to test using the A test input pattern, which has the advantage of high test efficiency.

〔Effect of the invention〕

By incorporating one or more PLA and RAM into a semiconductor integrated circuit, the present invention eliminates the need for a means for selecting an output signal during normal operation and a PLA output signal during test operation according to each operation, thereby eliminating the need for normal operation. This has the effect that the performance of the output circuit does not deteriorate when the time is reached.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an LSI according to a first embodiment of the present invention,
2 is a diagram showing the structure of the address space of the built-in RAM in FIG. 1, FIG. 3 is a diagram showing the timing of the PLA test input pattern write operation in FIG. 1, and FIG. 4 is a diagram showing the test operation in FIG. 1. A diagram showing the timing, Figure 5 is the PLA of Figure 1.
A diagram showing the timing of the output data comparison operation, FIG. 6 is a diagram showing the structure of the address space of the built-in RAM of the second embodiment of the present invention, and FIG. 7 is a diagram showing the PLA test input of the embodiment of FIG. 6. Diagram showing the timing of pattern writing operation, No. 8
This figure shows the timing of the test operation in FIG. 6, FIG. 8 shows the timing of the test operation in FIG. 6, and FIG. 9 shows the timing of the PLA output data comparison operation in FIG. 6. , FIG. 10 is a block diagram of an LSI according to the third embodiment of the present invention, FIG. 11 is a diagram showing the test pattern generation circuit of FIG. 10, and FIG. 12 is a timing diagram showing the operation of the circuit of FIG. 10. , FIG. 13 is a diagram showing a test pattern generation circuit according to a fourth embodiment of the present invention, and FIG. 14 is a diagram showing a test pattern generation circuit according to a fourth embodiment of the present invention.
FIG. 15 is a timing diagram showing an example of a conventional semiconductor integrated circuit, and FIG. 16 is a timing diagram showing the operation of the circuit shown in FIG. 11.12.13... Normal PLA input, 14.
...Normal input signal, 15...Normal output signal, 21゜22.23...PLA output, 31,
32.33...Test control signal, 41...
...Test input (PLA test input pattern), 101
...LSL 102...Input terminal, 1
03... Output terminal, 104... Input buffer, 105... Output huffer, 106...
... Built-in RAM, 107 ... Bus interface circuit, 108 ... Input/output buffer, 1
09...Internal data Hass, 110...7
” -Tahas, 111°112,113,114...
...Selector, 121゜122.123...P
LA, 131,132゜133...data latch, 141,142,143...data latch,
200...Test pattern generator, 201...
...Counter, 202...ROM, 331
... Counter clock, 332 ... Reset signal, 333 ... Address, 334 ...
...Reading ratio signal. Agent Patent Attorney Shinsho Uchihara 2 System Clock -v-1--V-y--V-No-Y-l-Ya 5 Diagram/System Clock -V-1-1■-j-Hai -I
-Ha J Ka 9 PLA test person cover turn rIl-Thus mu-4J Besan 〇, I). Be, to

Claims (1)

[Claims] 1. A semiconductor that tests the programmable logic array by inputting a test input to one or more built-in programmable logic arrays by switching from a normal PLA input signal through a selector controlled by a test control signal. In an integrated circuit, means for generating a test input pattern for testing the programmable logic array, a RAM for writing an output signal of the programmable logic array in response to the test input pattern, and a means for generating a test input pattern for testing the programmable logic array; 1. A semiconductor integrated circuit, comprising: external reading means. 2. One or more programmable logic arrays and RAM are built in, and a test input pattern for testing the program logic array is externally input to the R
means for writing the test input pattern into the RAM; means for reading the test input pattern from the RAM and inputting it into the programmable logic array; means for writing the output signal of the programmable array in response to the test input pattern into the RAM; What is claimed is: 1. A semiconductor integrated circuit comprising means for outputting an output and means for switching between normal operation and test operation, the switching means setting the test operation to test the programmable logic array.