JPH04174596A - Manufacture of multilayered printed wiring board - Google Patents
Manufacture of multilayered printed wiring boardInfo
- Publication number
- JPH04174596A JPH04174596A JP30223490A JP30223490A JPH04174596A JP H04174596 A JPH04174596 A JP H04174596A JP 30223490 A JP30223490 A JP 30223490A JP 30223490 A JP30223490 A JP 30223490A JP H04174596 A JPH04174596 A JP H04174596A
- Authority
- JP
- Japan
- Prior art keywords
- film
- copper
- layer
- oxide film
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 35
- 229910052802 copper Inorganic materials 0.000 claims abstract description 30
- 239000010949 copper Substances 0.000 claims abstract description 30
- 238000000034 method Methods 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000011347 resin Substances 0.000 claims abstract description 6
- 229920005989 resin Polymers 0.000 claims abstract description 6
- 238000001259 photo etching Methods 0.000 claims abstract description 4
- 238000007747 plating Methods 0.000 abstract description 19
- 238000011282 treatment Methods 0.000 abstract description 7
- 239000011889 copper foil Substances 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 239000000126 substance Substances 0.000 abstract description 3
- 238000005530 etching Methods 0.000 abstract description 2
- 238000010030 laminating Methods 0.000 abstract 1
- 229910000831 Steel Inorganic materials 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000010959 steel Substances 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 230000007774 longterm Effects 0.000 description 2
- 230000033116 oxidation-reduction process Effects 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000012958 reprocessing Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は多層印刷配線板の製造方法に関し、特に設備の
一連化が可能な多層印刷配線板の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a multilayer printed wiring board, and more particularly to a method for manufacturing a multilayer printed wiring board that allows for serialization of equipment.
一般に、内層ピアホールを有する多層印刷配線板の製造
方法は、銅箔を片面又は両面に設けた銅張り積層板の所
定の個所に穴を穿設し、次に、化学銅めっき処理、又は
、電気銅めっき処理によりスルーホールを形成する。次
に、ホトエツチング法により回路を形成し、回路銅めっ
き層の表面に酸化被膜を形成する。In general, the manufacturing method for multilayer printed wiring boards having inner layer peer holes involves drilling holes at predetermined locations in a copper-clad laminate with copper foil provided on one or both sides, and then applying chemical copper plating or electrolytic copper plating. Through holes are formed by copper plating. Next, a circuit is formed by photoetching, and an oxide film is formed on the surface of the circuit copper plating layer.
以上の方法により作成した複数の内層用基板をプリプレ
グを介して、銀箔、又は、片面又は両面の外層用回路基
板と重ね合わせ加圧、加熱して多層印刷配線板を形成す
る。A plurality of inner layer substrates produced by the above method are laminated with silver foil or one or both surfaces of outer layer circuit boards via prepreg, pressurized, and heated to form a multilayer printed wiring board.
上述した従来の多層印刷配線板の製造方法は、銅めっき
処理工程と回路銅めっき層の表面に酸化被膜を形成する
工程との中間に回路形成工程が入るのて、設備を一連化
てきすに分割されているため、工程間の搬送に人手を介
入させなければならず、取り扱いにより基板の折れや損
傷が発生し不良の原因となるという問題点があった。In the conventional method for manufacturing multilayer printed wiring boards described above, the circuit forming process is inserted between the copper plating process and the process of forming an oxide film on the surface of the circuit copper plating layer, so the equipment can be integrated into a series. Since the board is divided, manual intervention is required to transport it between processes, which poses a problem in that the board may be bent or damaged during handling, leading to defects.
また、回8釧めっき層の表面に酸化被膜を形成する事に
より、表面積を増加し、微細な構造の酸化物を形成する
ため樹脂との密着力を得ているが、次のプリプレグを介
して加圧、加熱して多層印刷配線板を形成する工程まで
の間長時間放置すると、回路銅めっき層の表面状態が変
質し、長期放置した場合、再度同じ処理をする必要があ
るという問題点があった。In addition, by forming an oxide film on the surface of the 8th plating layer, the surface area is increased and an oxide with a fine structure is formed to obtain adhesion with the resin. If left for a long time before the process of applying pressure and heating to form a multilayer printed wiring board, the surface condition of the circuit copper plating layer will change, and if left for a long time, the same treatment will need to be repeated. there were.
本発明の目的は、設備の一連化が可能で搬送に人手の介
入による基板の折れや損傷の発生がなく、また、長時間
放置による回路鋼めっき表面状態の変質のない印刷配線
板の製造方法を提供することにある。An object of the present invention is to produce a printed wiring board that allows for serialization of equipment, that does not cause bending or damage to the board due to manual intervention during transportation, and that does not cause deterioration of the surface condition of circuit steel plating due to long-term storage. Our goal is to provide the following.
本発明の多層印刷配線板の製造方法は、表面に銅層が被
覆された内層用基板の前記銅層表面上に酸化被膜を形成
する工程と、該酸化被膜を還元処理する工程と、還元処
理された前記鋼層表面上に電導性感光性樹脂被膜を用い
たホトエツチング法により回路形成を行う工程とを含ん
で構成されている。The method for manufacturing a multilayer printed wiring board of the present invention includes the steps of forming an oxide film on the surface of the copper layer of an inner layer substrate whose surface is coated with a copper layer, reducing the oxide film, and reducing the oxide film. The method includes the step of forming a circuit on the surface of the steel layer by photoetching using a conductive photosensitive resin film.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第1図(a)〜(g)は本発明の第1の実施例を説明す
る工程順に示した断面図である。FIGS. 1(a) to 1(g) are sectional views showing a first embodiment of the present invention in order of steps.
第1の実施例は、まず第1図(a>に示すように、所定
の個所に六3が穿設され、鋼箔2か表面に設けである基
板1を用意する。In the first embodiment, first, as shown in FIG. 1(a), a substrate 1 is prepared, in which holes 3 are bored at predetermined locations and steel foil 2 is provided on the surface.
次に、第1図(b)に示すように、化学銅めっき又は電
気銅めっき処理により銅箔2の表面上及び六3の内壁面
に銅めつき層4を析出させる。Next, as shown in FIG. 1(b), a copper plating layer 4 is deposited on the surface of the copper foil 2 and on the inner wall surface of the 63 by chemical copper plating or electrolytic copper plating.
次に、第1図(c)に示すように、めっき層4表面上に
酸化被膜を形成させたのち、還元処理により金属銅に還
元する。Next, as shown in FIG. 1(c), an oxide film is formed on the surface of the plating layer 4, and then reduced to metallic copper by a reduction treatment.
次に、第1図(d)に示すように、銅めっき層4表面上
に導電性悪光性樹脂(以下EDと記す)被膜5を形成す
る。Next, as shown in FIG. 1(d), a conductive anti-glare resin (hereinafter referred to as ED) film 5 is formed on the surface of the copper plating layer 4.
次に、第1図(e)に示すように、露光、現像によりE
D被1115のパターン形成を行う。Next, as shown in FIG. 1(e), E
A pattern of the D cover 1115 is formed.
次に、第1[](f)に示すように、工・ソチンクによ
り銅層のパターン形成を行なう。Next, as shown in Part 1 (f), a pattern of the copper layer is formed by etching and socinc.
次に、第1図<g)に示すように、積層工程前にED被
膜5を剥離する事により内層用基板が得られる。Next, as shown in FIG. 1<g), the ED coating 5 is peeled off before the lamination step to obtain an inner layer substrate.
以上の方法により、第1図(b)の銅めっき処理工程か
ら第1[g(d)のED被膜形成工程まで設備の一連化
か可能となる。By the above method, it is possible to integrate the equipment from the copper plating process shown in FIG. 1(b) to the ED film forming process shown in the first g(d).
第2図(a)〜(f>は本発明の第2の実施例を説明す
る工程順に示した断面図である。FIGS. 2(a) to 2(f) are sectional views showing a second embodiment of the present invention in order of steps.
第1図(a)〜(g)に示した第1の実施例は、スルー
ホールを有する内層用基板の場合であったか、第2の実
施例では、スルーホールのない内層用基板の場合の実施
例である。The first embodiment shown in FIGS. 1(a) to (g) was for an inner layer substrate having through holes, and the second embodiment was for an inner layer substrate without through holes. This is an example.
第2の実施例は、第2[3(a)に示すように、まず、
銀箔2が表面に設けである基板1を用意する。In the second embodiment, as shown in the second [3(a)], first,
A substrate 1 having a silver foil 2 provided on its surface is prepared.
第2図(b)の酸化還元工程以降は、第1図(c)の工
程以降と全く同じ方法で行う事により、内層用基板が得
られる。The oxidation-reduction step shown in FIG. 2(b) and subsequent steps are carried out in exactly the same manner as the steps shown in FIG. 1(c), thereby obtaining an inner layer substrate.
以上の方法により、第2図(b)の銅層表面上の酸化被
膜処理工程から第2図(c)のED被膜形成工程まで設
備の一連化が可能となる。By the above method, it becomes possible to integrate the equipment from the step of treating the oxide film on the surface of the copper layer shown in FIG. 2(b) to the step of forming the ED film shown in FIG. 2(c).
以上説明したように本発明は、銅層表面上に酸化被膜を
形成したあと還元処理を導入し、これらの処理をED被
膜形成による回路形成の前に行う事により、めっき処理
、銅層表面の酸化還元処理、ED被被膜よる回路形成の
3工程の設備を一連化する事ができ、簡素化された無人
化の合理的なラインにできるという効果がある。As explained above, the present invention introduces a reduction treatment after forming an oxide film on the surface of a copper layer, and performs these treatments before circuit formation by forming an ED film, thereby reducing the plating process and the surface of the copper layer. The equipment for the three steps of oxidation-reduction treatment and circuit formation using an ED coating can be integrated into a series, which has the effect of creating a streamlined, unmanned line.
また、ED被被膜銅層表面上の酸化被膜の保護となるた
め、積層を行う前にED被被膜剥離すれは、長期放置に
よる酸化被膜形成の再処理が不要になるという効果を有
する。Furthermore, since it protects the oxide film on the surface of the ED-coated copper layer, peeling off the ED film before lamination has the effect of eliminating the need for reprocessing to form an oxide film due to long-term storage.
第1図(a)〜<g)は本発明の第1の実施例を説明す
る工程順に示した断面図、第2図(a)〜(f)は本発
明の第2の実施例を説明する工程順に示した断面図であ
る。
1・・・基板、2・・・銅箔、3・・・穴、4・・銅め
つき層、5・・・ED被被膜FIGS. 1(a) to <g) are cross-sectional views showing the steps of the first embodiment of the present invention, and FIGS. 2(a) to (f) illustrate the second embodiment of the present invention. FIG. 1... Board, 2... Copper foil, 3... Hole, 4... Copper plating layer, 5... ED coating
Claims (1)
に酸化被膜を形成する工程と、該酸化被膜を還元処理す
る工程と、還元処理された前記銅層表面上に電導性感光
性樹脂被膜を用いたホトエッチング法により回路形成を
行う工程とを含む事を特徴とする多層印刷配線板の製造
方法。A step of forming an oxide film on the surface of the copper layer of the inner layer substrate whose surface is coated with a copper layer, a step of reducing the oxide film, and a step of forming an electrically conductive photosensitive film on the surface of the reduced copper layer. A method for manufacturing a multilayer printed wiring board, comprising the step of forming a circuit by a photoetching method using a resin film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP30223490A JP2874330B2 (en) | 1990-11-07 | 1990-11-07 | Method for manufacturing multilayer printed wiring board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP30223490A JP2874330B2 (en) | 1990-11-07 | 1990-11-07 | Method for manufacturing multilayer printed wiring board |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH04174596A true JPH04174596A (en) | 1992-06-22 |
JP2874330B2 JP2874330B2 (en) | 1999-03-24 |
Family
ID=17906566
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP30223490A Expired - Lifetime JP2874330B2 (en) | 1990-11-07 | 1990-11-07 | Method for manufacturing multilayer printed wiring board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2874330B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2000016597A1 (en) * | 1998-09-14 | 2000-03-23 | Ibiden Co., Ltd. | Printed wiring board and its manufacturing method |
CN105517361A (en) * | 2015-12-18 | 2016-04-20 | 景旺电子科技(龙川)有限公司 | Method for making copper blocks in copper block containing PCB |
-
1990
- 1990-11-07 JP JP30223490A patent/JP2874330B2/en not_active Expired - Lifetime
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2000016597A1 (en) * | 1998-09-14 | 2000-03-23 | Ibiden Co., Ltd. | Printed wiring board and its manufacturing method |
US7230188B1 (en) | 1998-09-14 | 2007-06-12 | Ibiden Co., Ltd. | Printed wiring board and its manufacturing method |
US7691189B2 (en) | 1998-09-14 | 2010-04-06 | Ibiden Co., Ltd. | Printed wiring board and its manufacturing method |
US7827680B2 (en) | 1998-09-14 | 2010-11-09 | Ibiden Co., Ltd. | Electroplating process of electroplating an elecrically conductive sustrate |
US8065794B2 (en) | 1998-09-14 | 2011-11-29 | Ibiden Co., Ltd. | Printed wiring board and its manufacturing method |
CN105517361A (en) * | 2015-12-18 | 2016-04-20 | 景旺电子科技(龙川)有限公司 | Method for making copper blocks in copper block containing PCB |
Also Published As
Publication number | Publication date |
---|---|
JP2874330B2 (en) | 1999-03-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6684497B2 (en) | Manufacturing methods for printed circuit boards | |
US7521779B2 (en) | Roughened printed circuit board | |
US20070070613A1 (en) | Method of manufacturing high density printed circuit boad | |
JPH0590756A (en) | Production of rigid/flexible board | |
US11690178B2 (en) | Multilayer printed wiring board and method of manufacturing the same | |
JPH04283992A (en) | Manufacture of printed circuit board | |
JP3224803B2 (en) | Circuit board manufacturing method | |
TWI672086B (en) | Method for manufacturing circuit board | |
KR20010009975A (en) | Method of producing a multi-layer printed-circuit board | |
KR101862243B1 (en) | Method for manuracturing printed circuit board with via and fine pitch circuit and printed circuit board by the same method | |
JPH11274731A (en) | Thin-film multilayer circuit substrate and its manufacture | |
JPH04174596A (en) | Manufacture of multilayered printed wiring board | |
JP3155565B2 (en) | Manufacturing method of printed wiring board | |
US5114518A (en) | Method of making multilayer circuit boards having conformal Insulating layers | |
JP2000200975A (en) | Manufacture of multilayer wiring substrate | |
JP6234132B2 (en) | Wiring board manufacturing method | |
JP2000049440A (en) | Manufacture of printed wiring multilayer board | |
JPH09130049A (en) | Method of forming via hole by build-up method of multilayer printed wiring board, and multilayer printed wiring board manufactured by it | |
KR100704917B1 (en) | Printed circuit board and the manufacturing method thereof | |
EP0264617A1 (en) | Multilayer circuit board and method of manufacture therefor | |
JP3077255B2 (en) | Wiring board and its manufacturing method | |
JPH10224036A (en) | Build-up printed wiring board and its manufacturing method | |
JPH1041623A (en) | Metal core printed circuit board and manufacturing method therefor | |
JP2002111212A (en) | Method of manufacturing multilayered printed board | |
JP3817291B2 (en) | Printed wiring board |