JPH11274731A - Thin-film multilayer circuit substrate and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify a multilayer process, reduce a via hole occupation space, and to increase density by forming integrally the multilayer wiring layer part of a laminate film and a core substrate. SOLUTION: When upper and lower wiring patterns 5 are connected via at least two interlayer insulation films, via holes 3 and 4 that penetrate at least two interlayer insulation films are provided and are connected directly, thus reducing the occupation space of the via holes 3 and 4 and hence increasing density. A laminate film 6 for constituting a multilayer wiring part 1 is made of a resin film 7 that becomes the interlayer insulation film and a metal thin film 8. Then, for simplifying the succeeding formation process of the wiring patterns 5, a resin film 9 that becomes a pattern formation mask is provided on the surface of the metal thin film 8, thus simplifying a multiple-stage build-up process and directly connecting the wiring pattern to a Cu via of being filled into a via hole through the interlayer insulation film with at least two layers and hence reducing the occupation space of the via.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin-film multilayer circuit board and a method of manufacturing the same, and more particularly, to a thin-film multilayer circuit board capable of achieving high density and having excellent environmental properties and a method of manufacturing the same. is there.

[0002]

2. Description of the Related Art With the recent increase in the speed of electronic computers, the increase in the capacity of semiconductor devices, and the degree of integration, the mounting method has also changed greatly, and the mounting circuit boards used for mounting semiconductor devices and the like have also increased. The density mounting, fine wiring, and multi-layering have become mainstream, and many wiring layers have been formed in a small space.

As a conventional high-density mounting circuit board, a printed circuit board is used as a core board, and an insulating layer such as a conductor circuit and a resin is alternately stacked thereon to connect and conduct internal / exterior circuits. It has been known.

In this case, as a method of forming a wiring pattern, an electrolytic plating method,
An electroless plating method, a vapor deposition method, a sputtering method, or the like is used. In addition, as a patterning method of the insulating layer, a method by photolithography using a photosensitive resin, a laser, a plasma using a non-photosensitive resin, Alternatively, there is a method using sandblasting.

[0005] Further, as a method of forming a conductive circuit, that is, a conductive pattern, a subtractive method in which a pattern is formed by etching the entire surface of the insulating layer after panel plating, a resist pattern is formed on the surface of the insulating layer, and an electroless Full-additive method in which a conductor layer is formed by plating and then the resist is peeled off, or a thin conductor layer to be a seed layer is formed on the surface of the insulating layer, a resist pattern is formed thereon, and a conductor layer is formed by electrolytic plating Then, a semi-additive method is known in which the resist pattern is peeled off, and then the seed layer coated on the resist pattern is etched by etching the entire surface.

Here, a manufacturing process of a conventional build-up multilayer printed wiring board will be briefly described with reference to FIG. First, a through hole 92 is provided in a copper-clad core substrate 91, and Cu is formed on the inner wall of the through hole 92 by electrolytic plating.
After the plating layer 93 is formed, the first wiring pattern 94 is formed by selectively etching the copper layer stretched on the surface of the core substrate 91.

Next, as shown in FIG. 8B, a resin varnish is applied and cured, or
A first interlayer insulating film 95 is formed by laminating a dry film made of a thermoplastic resin.

Referring to FIG. 8C, a via hole 96 for the first wiring pattern 94 is selectively formed in the first interlayer insulating film 95 by using photolithography, laser processing, or sandblasting.

Next, a second wiring pattern 97 connected to the first wiring pattern 94 via the via hole 96 is formed by the above-described subtractive method, semi-additive method, full-additive method or the like.

Next, similarly, a second interlayer insulating film 98 is formed, a via hole is formed in the second interlayer insulating film 98, and then a third wiring pattern 99 is formed. By repeating the desired number of layers, a multilayer printed wiring board is completed.

[0011]

However, such a method of forming a multi-layer wiring layer by build-up requires a multi-step process, and further requires a straight line when two or more conductor layers are connected. As shown in FIG. 8E, the connection must be alternately shifted, so that the space occupied by the via hole becomes large, and there is a problem that the density is limited.

When a liquid polymer such as a resin varnish is used in the step of forming the interlayer insulating film, the surface is not completely flat and some irregularities are formed. Are accumulated, the number of layers that can be manufactured without difficulty at the current manufacturing technology level is two to three, and there is a problem that further multilayering is difficult.

Furthermore, in the conventional process, an organic solvent is used as a solvent for the resin varnish, a developing solution for forming a via hole pattern, and a fine treatment is performed on the surface of the insulating layer as a pretreatment for forming a Cu thin film by electroless plating. Many kinds of chemicals, such as desmear for forming dents, several kinds of chemicals used for electroless plating, and stripping solutions for etching resists, must be used. Reducing their use is an essential social issue.

Accordingly, it is an object of the present invention to simplify a multi-layering process, to reduce the space occupied by via holes, to increase the density, and to reduce the use of chemicals.

[0015]

Here, means for solving the problems in the present invention will be described with reference to FIG. 1. FIG. 1 (a) is a sectional view of a main part of a thin film multilayer circuit board. FIG. 1B is a cross-sectional view of a main part of a laminate film constituting a multilayer wiring layer. 1 (a) and 1 (b) (1) The present invention is characterized in that in a thin film multilayer circuit board, a multilayer wiring layer portion 1 in which a laminate film 6 is multilayered and a core substrate 2 are integrated. .

As described above, since the multilayer wiring layer portion 1 is formed by using the laminate film 6, the multilayering process is simplified, and the use process and the use amount of chemicals are reduced. Excellent.

(2) The present invention is characterized in that, in the above (1), a part of the via holes 3 and 4 for connecting the layers in the multilayer wiring layer portion 1 penetrates two or more interlayer insulating films. And

As described above, when the upper and lower wiring patterns 5 are connected via the two or more interlayer insulating films, the via holes 3 and 4 penetrating the two or more interlayer insulating films are provided and directly connected to each other. , 4 occupied space can be reduced, thereby enabling higher density.

(3) According to the present invention, in a method of manufacturing a thin film multilayer circuit board, after forming the multilayer wiring layer portion 1 by a film laminating method, the multilayer wiring layer portion 1 is conductively connected to the core substrate 2. , Characterized by being integrated.

(4) The present invention includes the step (3) of forming via holes 3 and 4 penetrating through two or more interlayer insulating films for connecting the layers in the multilayer wiring layer section 1. It is characterized by.

(5) According to the present invention, in the above (4), the via holes 3 and 4 penetrating the two or more interlayer insulating films are formed by laser processing, and at least the output of the laser beam at the time of removing the conductor layer. Is greater than the output of the laser beam when the lowermost interlayer insulating film is removed.

As described above, when the via holes 3 and 4 penetrating the two or more interlayer insulating films are formed by laser processing,
By controlling the output of the laser beam according to the object to be removed, the resin film 7 serving as the interlayer insulating film and the conductor layer can be removed in a series of steps, and the laser beam during removal of the lowermost interlayer insulating film can be removed. By making the output smaller, the via holes 3 and 4 can be formed without damaging the metal thin film 8 for forming the lower wiring pattern 5 to be connected.

(6) Further, according to the present invention, in any one of the above (3) to (5), the laminated film 6 constituting the multilayer wiring layer portion 1 may be a resin film 7 serving as an interlayer insulating film;
It is characterized by comprising a metal thin film 8 provided on at least one surface of a resin film 7 serving as an interlayer insulating film, and a resin film 9 serving as a pattern forming mask provided on the surface of the metal thin film 8.

As described above, the laminate film 6 constituting the multilayer wiring layer portion 1 is composed of the resin film 7 and the metal thin film 8 serving as an interlayer insulating film, and simplifies the subsequent steps of forming the wiring pattern 5. Preferably, a resin film 9 serving as a pattern forming mask is provided on the surface of the metal thin film 8.

(7) According to the present invention, in the above (6), the metal thin film 8 provided on at least one surface of the resin film 7 to be an interlayer insulating film is formed by plating the via holes 3 and 4 with a plating method.
A seed layer in the step of embedding a conductor in the substrate.

As described above, since the metal thin film 8 provided on the laminate film 6 is used as a seed layer in the plating step of embedding a conductor in the via holes 3 and 4, it is not necessary to separately form the seed layer. In addition, the manufacturing process can be simplified.

(8) In the present invention, in the above (7), the plating step is an electrolytic plating step, and the metal thin film 8 provided on at least one surface of the resin film 7 serving as an interlayer insulating film is provided.
Is selectively formed to form the wiring pattern 5.

As described above, when the via holes 3 and 4 are buried, the via holes 3 and 4 can be quickly buried by using the electrolytic plating method, and the wiring pattern 5 is formed by the metal thin film 8 forming the laminate film 6. Is formed by a subtractive method of patterning, the amount of chemicals such as a plating solution used can be reduced.

(9) In the present invention, in the above (7), the plating step of embedding a conductor in the via holes 3 and 4 is either an electroless plating step or an electrolytic plating step, and the wiring pattern 5 At the time of formation, one of electroless plating and electrolytic plating is performed using the metal thin film 8 provided on at least one surface of the resin film 7 serving as an interlayer insulating film as a seed layer.

As described above, an electroless plating method may be used as the plating step.
In the formation step, the wiring pattern 5 can be miniaturized by forming it by a semi-additive method of plating the metal thin film 8 as a seed layer.

(10) Further, according to the present invention, in any one of the above (7) to (9), the resin film 9 serving as a wiring pattern forming mask provided on the surface of the metal thin film 8 may be used in an electrolytic plating step. It is characterized in that it functions as a support film when connecting an electrode for electrolytic plating to the metal thin film 8.

As described above, by forming the resin film 9 serving as a wiring pattern forming mask constituting the laminate film 6 so as to be a support film for connecting electrodes to the metal thin film 8 in the electrolytic plating step, The damage of the seed layer in the electrolytic plating step can be prevented without complicating the configuration.

[0033]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A manufacturing process for a multilayer printed wiring board according to a first embodiment of the present invention will be described with reference to FIGS. Referring to FIG. 2A, first, a resin layer 12 made of a thermoplastic resin having a thickness of 20 to 50 μm, for example, 30 μm, for example, a polyimide-based thermoplastic resin, has a thickness of 5 to 15 μm, for example, 10 μm.
Dry film 11 with Cu thin films 13 and 14 attached
Prepare

On the surfaces of the Cu thin films 13 and 14 constituting the dry film 11, the Cu thin films 13 and 14 are supported and have a thickness of 5 to 20 μm serving as an etching mask in a patterning step of the Cu thin films 13 and 14. For example, support films 15 and 16 having a thickness of 15 μm are provided. Note that the support films 15 and 16 use a dry film resist when a photo process is used as a patterning process, and use an excimer laser, a carbon dioxide laser, or Nd:
When patterning is performed by laser processing using a YAG laser or the like, a resin capable of laser processing may be used, and a dry film resist is used here.

Next, after fixing the dry film 11 by vacuum suction, the fourth harmonic (λ = 266n) of a Nd: YAG laser is used.
m), the laser beam 17 is selectively irradiated with the oscillation frequency lowered and the laser beam output increased, and the supporting film 16
Then, the Cu thin film 14 is removed, and then the resin layer 12 is removed by irradiating the laser beam 17 with the oscillation frequency raised and the laser beam output reduced, thereby forming a via hole 18.

In this laser processing step, the wavelength is 26
Since the ultraviolet light of 6 nm is used, both the resin and the metal can be efficiently removed, and the output of the laser beam 17 is adjusted according to the object to be removed.
And the resin layer 12 can be accurately removed without using the Cu thin film 13 as an etching stop layer.

Next, an electrode for electrolytic plating was connected to the Cu thin film 13 exposed at the end of the dry film 11, that is, the terminal 19, and the dry film 11 was fixed by the support film 15. By performing electrolytic plating in a plating bath in this state, the inside of the via hole 18 is buried with Cu to form a Cu via 20.

The height of the Cu via 20 in this case is
It is formed extra high enough to compensate for the amount of etching in the subsequent patterning step. The terminal 19 is
2B may be provided at the same time as the step of forming the via hole 18, or the end may be exposed in advance in the step of manufacturing the dry film 11 itself.

Next, as shown in FIG. 2D, the support film 16 is selectively removed by a photo process to form an etching mask having an opening 21 for forming a wiring pattern.

Next, referring to FIGS. 2E and 2F, the Cu thin film 14 is etched using the support film 16 provided with the opening 21 as an etching mask, and then the support film 16 is peeled off to obtain a wiring pattern 22. .

Next, as shown in FIG. 3 (g), a dry film 2 in which a Cu thin film 25 and a support film 26 are provided only on one side of a resin layer 24 made of a thermoplastic resin.
3 is laminated by heating while being pressed in an atmosphere where a vacuum is sucked. In this laminating step, the resin layer 24 and the resin layer 12 adhere to each other without generating voids, so that the concave portions between the adjacent wiring patterns 22 are filled with the resin.

Next, referring again to FIG. 3 (h), the 266 nm ultraviolet laser beam 27 is again applied.
By irradiating while adjusting the output according to the object to be removed, a via hole 28 penetrating the resin layer 12 and the resin layer 24 serving as two interlayer insulating films reaching the Cu thin film 25 is formed.

Next, the inside of the via hole 28 is buried with Cu again by electrolytic plating to form a Cu via 29. In addition,
In this case, the newly laminated dry film 2
3 is connected to an electrode at the time of electrolytic plating to the terminal portion of the Cu thin film 25, and the Cu thin film 25 becomes a seed layer.
Reference numeral 6 denotes a support film for supporting the seed layer. In this case, the terminal portion may be formed in the step of forming the via hole 28, or may be provided in advance in the dry film 23 itself. .

Next, as shown in FIG. 3 (j), the support film 15 is again selectively etched away by a photo process to form an etching mask having an opening for forming a wiring pattern. After etching the Cu thin film 13, the support film 15 is peeled off to form the wiring pattern 3.
0 is formed.

Referring to FIG. 3 (k), the support film 26 is also selectively etched away by a photo process on the opposite surface to form an etching mask having an opening for forming a wiring pattern. After etching the Cu thin film 25 using this etching mask, the support film 26 is peeled off to form the wiring pattern 31.

Next, as shown in FIG. 3 (l), the dry films 32, 3 in which a Cu thin film and a support film are provided only on one surface of a resin layer made of a thermoplastic resin are again formed.
In an atmosphere in which 3 is evacuated to vacuum, the wiring pattern 3
Lamination is performed by pressing and heating the surface on which the wiring pattern 31 and the wiring pattern 31 are formed.

Next, referring to FIG. 4 (m), the 266 nm ultraviolet laser beam 34 is again applied.
By irradiating while adjusting the output according to the object to be removed, a via hole 35 penetrating the four interlayer insulating films of the resin layers 39 to 40 reaching the Cu thin film constituting the dry film 33 is formed.

Referring to FIG. 4 (n), the inside of the via hole 35 is buried with Cu again by electrolytic plating to form a Cu via 36. Then, the Cu thin film constituting the dry films 32 and 33 on both sides is patterned and wired. By forming the patterns 37 and 38, a multilayer wiring layer portion composed of a multilayer laminate film is completed. In this case, the electrode for the electrolytic plating is connected to the terminal of the Cu thin film of the newly laminated dry film 33, and the Cu thin film is used as a seed layer.
The terminal may be formed in the step of forming the via hole 35,
Alternatively, it may be provided in advance on the dry film 33 itself.

4 (o). Finally, in a vacuum-sucked atmosphere, the inner wall of the through-hole 42 is heated and integrated with the core substrate 41 with the multilayer wiring layer pressed while being pressed with Cu. A multilayer printed wiring board, that is, a thin film multilayer circuit board is completed.

Although the multilayer wiring layer formed by the film laminating method is integrated only on one side of the core substrate 41 in the drawing, the multilayer wiring layer formed by the film laminating method is formed on both sides of the core substrate 41. It is also possible to attach them, and if they are attached to both sides, the stress is evenly applied to both sides, so that the bending and bending of the thin film multilayer circuit board can be prevented.

As described above, in the first embodiment of the present invention, since the multilayer wiring layer is formed by the film laminating method using the dry film, the multi-step build-up process is simplified. Further, since the upper and lower wiring patterns separated by the two or more interlayer insulating films are directly connected by the Cu vias filled in the via holes penetrating the two or more interlayer insulating films, the space occupied by the via holes or the Cu vias is reduced. Therefore, the density of the thin film multilayer circuit board can be increased.

Also, since a dry film is used,
Since the step of forming the interlayer insulating film using a resin varnish or the like becomes unnecessary, the solvent or the like involved in the step of forming the interlayer insulating film becomes unnecessary,
In addition, since the via hole forming step is performed by laser processing, an etching solution or the like accompanying the chemical etching step is not required, and further, since the support film is used as it is as an etching mask, a photoresist coating step is not required. Therefore, the type and amount of chemicals to be used can be reduced, and the manufacturing process can be made environmentally friendly.

Next, with reference to FIGS. 5 to 7, a process of manufacturing a multilayer printed wiring board according to a second embodiment of the present invention by a semi-additive method will be described. Referring to FIG. 5A, first, a seed layer in an electroless plating process or an electrolytic plating process is formed on both surfaces of a resin layer 42 made of a thermoplastic resin having a thickness of 20 to 50 μm, for example, 30 μm, for example, a polyimide-based thermoplastic resin. 1-2 μm in thickness, for example,
A dry film 51 on which 1.5 μm seed Cu thin films 53 and 54 are attached is prepared.

Also in this case, on the surface of the seed Cu thin films 53 and 54 constituting the dry film 51, the seed Cu thin films 53 and 54 are supported and have a thickness 5 serving as a plating protection mask in a wiring pattern forming step. Support films 55 and 56 having a thickness of 50 μm, for example, 20 μm are provided. Note that the support films 55 and 56 in this case also use a dry film resist when a photo process is used as a patterning process, and are processed by laser processing using an excimer laser, a carbon dioxide laser, an Nd: YAG laser, or the like. In the case of patterning, a resin that can be laser-processed may be used. Here, a dry film resist is used.

Next, after fixing the dry film 51 by vacuum suction, the fourth harmonic (λ = 266n) of the Nd: YAG laser is applied.
m), the laser beam 57 is selectively irradiated with the oscillation frequency lowered and the laser beam output increased, and the supporting film 56
And the seed Cu thin film 54 is removed, and then the laser light 57 is emitted while the oscillation frequency is increased and the laser light output is reduced.
Is irradiated to remove the resin layer 52 to form a via hole 58.

Next, as shown in FIG. 5C, the seed C exposed at the end of the dry film 51 is formed.
By connecting an electrode for electrolytic plating to the u thin film 53, that is, the terminal portion 59, and performing electrolytic plating in a plating bath with the dry film 51 fixed with the support film 55,
The inside of the via hole 58 is buried with Cu to form a Cu via 60.
To form

The height of the Cu via 60 in this case is
The seed Cu thin film 54 is formed at substantially the same height as the upper surface.
Also, the terminal portion 59 in this case may be provided at the same time as the step of forming the via hole 58 in FIG. 5B, or the end may be exposed in advance in the step of manufacturing the dry film 51 itself. good.

Next, as shown in FIG. 5D, the support film 56 is selectively etched and removed by a photo process to form a support film pattern 61 serving as a plating protection mask in an electrolytic plating step for forming a wiring pattern.

Then, electrolytic plating is performed using the support film pattern 61 as a plating protection mask, so that the exposed portion of the seed Cu thin film 54 and the surface of the Cu via 60 are covered with the support film pattern 61.
The Cu plating layer 62 having a thickness equal to or less than the film thickness is formed.

Next, after the support film pattern 61 is peeled off, the entire surface is etched, so that the seed Cu thin film 54 in the region where the Cu plating layer 62 was not formed because the support film pattern 61 was covered. Is selectively removed to form a wiring pattern 6
Form 3 In the entire surface etching step, the surface of the Cu plating layer 62 is also slightly etched.

Next, as shown in FIG. 6 (g), the dry film 64 having the seed Cu thin film 66 and the support film 67 provided only on one surface of the resin layer 65 made of a thermoplastic resin is heated while being pressed in an atmosphere where a vacuum is sucked. Laminate by doing.

Next, referring again to FIG. 6H, the 266 nm ultraviolet laser beam 68 is again applied.
By irradiating while adjusting the output according to the removal target, the via hole 6 penetrating the resin layer 65 and the resin layer 54 serving as two interlayer insulating films reaching the seed Cu thin film 53
9 is formed.

Next, referring to FIG. 6I, the inside of the via hole 69 is buried with Cu again by electrolytic plating to form a Cu via 70.

Next, the support film 67 is selectively etched again by a photo process to form a support film pattern for forming a Cu plating layer, and this support film pattern is protected by plating. The exposed portion of the seed Cu thin film 66 and the surface of the Cu via
After forming the u plating layer, the support film pattern is peeled off,
By performing the entire surface etching, the wiring pattern 71 is formed.
To form

Referring to FIG. 6 (k), the wiring pattern is formed again in an atmosphere in which the dry film 72 having the seed Cu thin film 74 and the support film 75 provided only on one surface of the resin layer 73 made of thermoplastic resin is evacuated to a vacuum. The laminate is formed by heating while pressing on the surface on which 71 is formed.

Next, by irradiating again with 266 nm ultraviolet laser light while adjusting the output according to the object to be removed, the laser light penetrates the entire resin layer 73 to the resin layer 52. After the via hole 76 is formed, a Cu plating layer 77 is formed on the inner wall of the via hole 76 by performing electrolytic plating.

Referring to FIG. 7 (m), the support films 55, 7 are again formed by a photo process.
5 is selectively removed by etching to form a support film pattern for forming a Cu plating layer, and electrolytic plating is performed using the support film pattern as a plating protection mask to expose exposed portions of the seed Cu thin films 53 and 74 and After a Cu plating layer is formed on the surface of the Cu plating layer 77, the support film pattern is peeled off, and the entire surface is etched to form wiring patterns 78 and 79 on both surfaces, thereby completing a multilayer wiring layer portion.

Finally, in a vacuum-sucked atmosphere, the inner wall of the through-hole 81 is integrated with the core substrate 80 in which the inner wall of the through-hole 81 is pressed and heated while pressing the multilayer wiring layer portion, that is, a multilayer printed wiring board, Thus, a thin film multilayer circuit board is completed.

In this case as well, the multilayer wiring layer formed by the film lamination method is integrated only on one side of the core substrate 80 in the drawing, but the multilayer wiring layer formed by the film lamination method on both surfaces of the core substrate 80 is integrated. The wiring layer portion may be adhered, and if it is adhered to both surfaces, the stress is evenly applied to both surfaces, so that the bending and bending of the thin film multilayer circuit board can be prevented.

As described above, in the second embodiment of the present invention, the multilayer wiring layer is formed by the film laminating method using a dry film as in the first embodiment. The multi-stage build-up process is simplified, and the upper and lower wiring patterns separated by two or more interlayer insulating films are directly connected by Cu vias filled in via holes penetrating the two or more interlayer insulating films. Therefore, the space occupied by the via holes or Cu vias can be reduced, and the density of the thin film multilayer circuit board can be increased.

Since a dry film is used,
Since the step of forming the interlayer insulating film using a resin varnish or the like becomes unnecessary, the solvent or the like involved in the step of forming the interlayer insulating film becomes unnecessary,
In addition, since the via hole forming process is performed by laser processing, an etching solution accompanying the chemical etching process is not required, and further, since the support film is used as it is as a plating protection mask, a photoresist coating process is not required. Therefore, it is possible to reduce the types and amounts of chemicals to be used, thereby achieving a manufacturing process that is in harmony with the environment.

Further, in the second embodiment, since the wiring pattern is formed by the semi-additive method, the wiring pattern is formed in comparison with the case of using the subtractive method as in the first embodiment. Miniaturization is possible, and high density is possible. However, in the second embodiment, since plating is used in the step of forming the wiring pattern, the amount of chemicals used is slightly increased as compared with the first embodiment.

In the description of the second embodiment, when the Cu plating layer serving as the wiring pattern is formed, the electrolytic plating method is used. However, the electroless plating method, that is, the chemical plating method is used. May be used.

For example, recently, a high-speed (thickening) electroless plating method has been developed as a method of electrolessly plating Cu. By using this high-speed (thickening) electroless plating method, it is possible to reduce the production level. Practical application becomes possible. In addition,
Also in the case of electroless plating, a seed Cu thin film serving as a seed layer is required to form a Cu plating layer.

Further, in the step of forming a Cu via for filling a via hole or the step of forming a Cu plating layer on the inner surface of a via hole penetrating the whole, an electroless plating method may be used instead of the electrolytic plating method. In this case, in this case, the step of forming the terminal portion 59 becomes unnecessary.

The embodiments of the present invention have been described above. However, the present invention is not limited to the configuration described in the embodiments, and various modifications are possible. , Nd: YAG laser at the fourth harmonic (λ =
The wavelength is not limited to 266 nm, but may be any ultraviolet ray having a high energy density, and a third harmonic (λ = 355 nm) of an Nd: YAG laser may be used, or an excimer laser may be used. Good thing.

In the description of each of the above embodiments, the output of the laser beam is controlled by using the oscillation frequency dependency of the optical output. However, the output may be simply controlled by the applied power.

In the description of each of the above embodiments, patterning is performed by a photo process using a dry film resist as a support film. However, the same process as that for forming a via hole is performed using a non-photosensitive resin. Alternatively, patterning may be performed by laser processing. In this case, a predetermined pattern is drawn by a laser beam, and the throughput is reduced, but the amount of chemicals used is reduced and the environmental property is further improved. In this case, the laser light does not necessarily need to be ultraviolet light, and primary light of a Nd: YAG laser or a carbon dioxide laser may be used.

Further, after the laminating step, from which side the via hole is formed and the wiring pattern is formed are arbitrary, and may be appropriately determined according to the required number of layers.

In the description of each of the above embodiments, the resin layer of the dry film is made of a thermoplastic resin. However, the present invention is not limited to such a structure. May be used.

[0081]

According to the present invention, the multilayer wiring layer is formed by the film laminating method, and the via hole and the via penetrating the two or more interlayer insulating films are formed, so that the manufacturing process is simplified. At the same time, the density can be increased, and the process of forming via holes is performed by laser processing, so the amount of chemicals used can be significantly reduced. it can.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a basic configuration of the present invention.

FIG. 2 is an explanatory diagram of a manufacturing process partway through the first embodiment of the present invention.

FIG. 3 is an explanatory diagram of a manufacturing process of the first embodiment of the present invention up to the middle of FIG. 2;

FIG. 4 is an explanatory diagram of a manufacturing process of the first embodiment of the present invention after FIG. 3;

FIG. 5 is an explanatory diagram of a manufacturing process partway through a second embodiment of the present invention.

FIG. 6 is an explanatory diagram of a manufacturing process of the second embodiment of the present invention up to the middle of FIG. 5;

FIG. 7 is an explanatory diagram of a manufacturing process of the second embodiment of the present invention after FIG. 6;

FIG. 8 is an explanatory diagram of a manufacturing process of a conventional build-up multilayer printed wiring board.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Multilayer wiring layer part 2 Core board 3 Via hole 4 Via hole 5 Wiring pattern 6 Laminating film 7 Resin film 8 Metal thin film 9 Resin film 11 Dry film 12 Resin layer 13 Cu thin film 14 Cu thin film 15 Support film 16 Support film 17 Laser light 18 Via hole 19 Terminal 20 Cu Via 21 Opening 22 Wiring Pattern 23 Dry Film 24 Resin Layer 25 Cu Thin Film 26 Support Film 27 Laser Light 28 Via Hole 29 Cu Via 30 Wiring Pattern 31 Wiring Pattern 32 Dry Film 33 Dry Film 34 Laser Light 35 Via Hole 36 Cu via 37 Wiring pattern 38 Wiring pattern 39 Resin layer 40 Resin layer 41 Core substrate 42 Through hole 51 Dry film 52 Resin layer 53 Seed Cu thin film 54 Seed Cu thin film 55 Support film 5 Supporting film 57 Laser light 58 Via hole 59 Terminal 60 Cu via 61 Supporting film pattern 62 Cu plating layer 63 Wiring pattern 64 Dry film 65 Resin layer 66 Seed Cu thin film 67 Supporting film 68 Laser light 69 Via hole 70 Cu via 71 Wiring pattern 72 Dry Film 73 Resin layer 74 Seed Cu thin film 75 Support film 76 Via hole 77 Cu plating layer 78 Wiring pattern 79 Wiring pattern 80 Core substrate 81 Through hole 91 Core substrate 92 Through hole 93 Cu plating layer 94 First wiring pattern 95 First interlayer insulating film Reference numeral 96 Via hole 97 Second wiring pattern 98 Second interlayer insulating film 99 Third interlayer insulating film

Claims (10)

[Claims] 1. A thin film multilayer circuit board, wherein a multilayer wiring layer portion in which a laminate film is multilayered is integrated with a core substrate. 2. The thin film multilayer circuit board according to claim 1, wherein a part of the via hole for connecting the layers in the multilayer wiring layer portion penetrates at least two interlayer insulating films. 3. A method for manufacturing a thin-film multilayer circuit board, comprising: forming a multilayer wiring layer portion by a film laminating method; and then electrically connecting the multilayer wiring layer portion to a core substrate and integrating the core substrate. 4. A method for manufacturing a thin film multilayer circuit board according to claim 3, further comprising the step of forming a via hole penetrating two or more interlayer insulating films for connecting the layers in said multilayer wiring layer portion. . 5. A via hole penetrating through the two or more interlayer insulating films is formed by laser processing, and at least the output of the laser light at the time of removing the conductive layer is changed by the laser light at the time of removing the lowermost interlayer insulating film. 5. The method according to claim 4, wherein the output is larger than the output. 6. A laminate film constituting the multilayer wiring layer portion, the laminate film includes a resin film serving as an interlayer insulating film, a metal thin film provided on at least one surface of the resin film serving as the interlayer insulating film,
6. The method for manufacturing a thin film multilayer circuit board according to claim 3, comprising a resin film serving as a pattern forming mask provided on the surface of the metal thin film. 7. The thin film according to claim 6, wherein the metal thin film provided on at least one surface of the resin film serving as the interlayer insulating film is used as a seed layer in a step of embedding a conductor in a via hole by a plating method. A method for manufacturing a multilayer circuit board. 8. The method according to claim 1, wherein the plating step is an electrolytic plating step, and a wiring pattern is formed by selectively removing a metal thin film provided on at least one surface of the resin film serving as the interlayer insulating film. A method for manufacturing a thin film multilayer circuit board according to claim 7. 9. A metal thin film provided on at least one side of a resin film to be an interlayer insulating film when the plating step is either an electroless plating step or an electrolytic plating step and a wiring pattern is formed. 8. The method for manufacturing a thin-film multilayer circuit board according to claim 7, wherein either one of electroless plating and electrolytic plating is performed using the as a seed layer. 10. A resin film provided on a surface of the metal thin film and serving as a wiring pattern forming mask acts as a support film when an electrode for electrolytic plating is connected to the metal thin film in an electrolytic plating step. The method for manufacturing a thin-film multilayer circuit board according to any one of claims 7 to 9, wherein: