JPH0416941B2 - - Google Patents

Info

Publication number
JPH0416941B2
JPH0416941B2 JP57226016A JP22601682A JPH0416941B2 JP H0416941 B2 JPH0416941 B2 JP H0416941B2 JP 57226016 A JP57226016 A JP 57226016A JP 22601682 A JP22601682 A JP 22601682A JP H0416941 B2 JPH0416941 B2 JP H0416941B2
Authority
JP
Japan
Prior art keywords
semiconductor element
substrate
solder
film
wiring pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57226016A
Other languages
Japanese (ja)
Other versions
JPS59117188A (en
Inventor
Masaru Sakaguchi
Muneo Ooshima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57226016A priority Critical patent/JPS59117188A/en
Publication of JPS59117188A publication Critical patent/JPS59117188A/en
Publication of JPH0416941B2 publication Critical patent/JPH0416941B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、耐熱温度が低い物質を有する配線基
板に電子部品及び半導体素子をはんだ溶融接合し
た配線基板の構成に係り、基板上に基板材料より
熱伝導率の小さい材料からなる膜を形成したもの
である。
Detailed Description of the Invention [Industrial Field of Application] The present invention relates to the construction of a wiring board in which electronic components and semiconductor elements are melt-bonded by soldering to a wiring board containing a substance with a low heat resistance temperature. A film made of a material with lower thermal conductivity is formed.

〔従来技術〕[Prior art]

配線基板上に電子部品及び半導体素子をはんだ
で接合したハイブリツドモジユールは既に広く知
られている。これらのモジユールは、基板に耐熱
性の良好なアルミナセラミツクを用いたものが多
く、該セラミツク基板上に直接回路パターンを形
成して、該回路パターンの所要位置に部品をはん
だ接合している。
Hybrid modules in which electronic components and semiconductor elements are bonded to a wiring board by soldering are already widely known. Many of these modules use alumina ceramic, which has good heat resistance, for the substrate, and a circuit pattern is directly formed on the ceramic substrate, and components are soldered to the desired positions of the circuit pattern.

一部のモジユールでは、基板に耐熱衝撃性の劣
るガラス材を用いて前記セラミツク基板と同様の
構成でモジユールを形成している。ところが、こ
れらのモジユール上に耐熱性の低い物質あるいは
部品を搭載した後、前記電子部品及び半導体素子
をはんだ接続する必要があり、はんだ付個所のみ
局所加熱を行なつてはんだ付けをしている。この
場合局所加熱による熱が基板の平面方向に大きな
温度勾配を生じさせ、基板を破断してしまうとい
う不具合が起つている。
In some modules, a glass material having poor thermal shock resistance is used for the substrate, and the module is formed with the same structure as the ceramic substrate. However, after mounting materials or components with low heat resistance on these modules, it is necessary to solder the electronic components and semiconductor elements, and soldering is performed by locally heating only the soldering points. In this case, the heat generated by local heating causes a large temperature gradient in the planar direction of the substrate, causing a problem that the substrate may break.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、上記の欠点をなくし局所加熱
によつても基板の破損を起こさない配線基板の構
成法を提供するにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for configuring a wiring board that eliminates the above-mentioned drawbacks and does not cause damage to the board even when subjected to local heating.

〔発明の概要〕[Summary of the invention]

本発明では、基板上に基板より熱伝導率の小さ
い材料からなる膜を形成し、この上面に配線パタ
ーンを形成し、さらにその配線パターン上に電子
部品及び半導体素子を局所加熱によつてはんだ付
けできるようにしたものである。
In the present invention, a film made of a material with lower thermal conductivity than the substrate is formed on the substrate, a wiring pattern is formed on the upper surface of the film, and electronic components and semiconductor elements are soldered onto the wiring pattern by local heating. It has been made possible.

〔発明の実施例〕[Embodiments of the invention]

以下本発明の実施例を第1図〜第5図にて説明
する。
Embodiments of the present invention will be described below with reference to FIGS. 1 to 5.

第1図は、下部ガラス基板2と上部ガラス基板
4の間に液晶6を封入した液晶モジユール8で、
下部ガラス基板2の上面には液晶を駆動するため
の半導体素子10が接続されている。
FIG. 1 shows a liquid crystal module 8 in which a liquid crystal 6 is sealed between a lower glass substrate 2 and an upper glass substrate 4.
A semiconductor element 10 for driving a liquid crystal is connected to the upper surface of the lower glass substrate 2.

第2図は、第1図の一部を拡大して表示した断
面図で第1図と同じ符号を配したものは、同じ内
容を示している。第2図において、下部基板2と
半導体素子10とは、はんだ12によつて接続さ
れる。従来構成の半導体素子接合部の拡大を第3
図に示す。本図においても第1図及び第2図と同
一符号のものは同じ内容を示す。第3図におい
て、半導体素子10はガラス基板上に形成された
配線パターン14の接合エリアにはんだ12によ
つてはんだ付け接合されている。この場合、はん
だが配線パターン14上をぬれ広がるのを防止す
るため、はんだマスク16よつて配線パターン上
の一定エリアのみはんだにぬれるようにし、他の
部分をカバーしている。
FIG. 2 is an enlarged cross-sectional view of a part of FIG. 1, and the same reference numerals as in FIG. 1 indicate the same contents. In FIG. 2, lower substrate 2 and semiconductor element 10 are connected by solder 12. In FIG. The third step was to enlarge the semiconductor element junction of the conventional configuration.
As shown in the figure. In this figure as well, the same reference numerals as in FIGS. 1 and 2 indicate the same contents. In FIG. 3, a semiconductor element 10 is soldered to a bonding area of a wiring pattern 14 formed on a glass substrate using a solder 12. In this case, in order to prevent the solder from spreading on the wiring pattern 14, the solder mask 16 is used so that only a certain area on the wiring pattern is wetted with the solder, and other parts are covered.

第4図は本発明になる基板構成を示す図で、前
記各図と同一符号を付したものは同じ内容を示し
ている。第4図において、ガラス基板2上には、
ポリイミド系樹脂を用いた膜20が形成されてい
る。第5図は、本発明になるモジユールをはんだ
付けする方法を説明するもので、液晶モジユール
8は雰囲気の制御が可能なトンネル炉22内に設
置され、予熱盤24はトンネル炉22の下部にあ
つて、モジユールを下方から予熱できる。トンネ
ル炉22の上面は赤外線ランプ26からの赤外線
照射により熱線が透過するフタ28によつて密閉
される。
FIG. 4 is a diagram showing the structure of a substrate according to the present invention, and the same reference numerals as those in the previous figures indicate the same contents. In FIG. 4, on the glass substrate 2,
A film 20 made of polyimide resin is formed. FIG. 5 explains the method of soldering the module according to the present invention, in which the liquid crystal module 8 is installed in a tunnel furnace 22 whose atmosphere can be controlled, and the preheating plate 24 is placed at the bottom of the tunnel furnace 22. You can preheat the module from below. The upper surface of the tunnel furnace 22 is sealed with a lid 28 through which heat rays emitted from an infrared lamp 26 are transmitted.

まず、第4図においてガラス基板2上に印刷法
によつて半導体素子10が設置される位置にポリ
イミド樹脂からなる膜20を形成する。膜20を
形成した後、配線パターン14を作るべくクロ
ム、銅及びクロムを蒸着法によりガラス基板2上
に付着させる。この後、配線パターンを形成する
ためのフオト工程、エツチング工程を経て、モジ
ユールに必要な配線パターン14を形成する。は
んだマスク16は、クロム、銅、クロムの三層構
造に蒸着した最上層のクロムを窓状にエツチング
して除去し下部のパターン部14の銅を露呈さ
せ、銅のところのみはんだ付けができるようにし
ている。半導体素子10は、あらかじめはんだ1
2が付着された状態で供給されており、前記した
基板2のはんだ付けパターンと半導体素子10の
はんだ12が位置合せされて仮接続される。この
状態では配線パターン14とはんだは接触してい
るのみで完全な接合は行なわれていない。次に前
記仮位置合せされたモジユール8を第5図に示す
如くN2ガスに置換されたトンネル炉22内に設
置する。ここでモジユール8は予熱盤によつて約
100℃に予備加熱される。これと同時に赤外線ラ
ンプ26の中心をはんだ付けする半導体素子10
の上面に移動させる。赤外線ランプ26の第2焦
点は半導体素子10の上面に焦点合わせされてお
り、赤外線ランプ26の点灯により半導体素子1
0の上面が加熱され、半導体素子10上面の熱は
第4図に示す素子10内を伝導していきはんだ1
2を加熱し膜20に達する。ここで半導体素子1
0及びはんだ内の熱伝導率は大きいため急激に昇
温するが、膜20に熱伝導率の小さいポリイミド
樹脂を用いているため、この膜20により熱伝達
が抑制されて、膜20の下部にあるガラスの昇温
を押えることができる。さらにこの熱伝達の抑制
によりはんだ12の昇温を早める。このようにし
てはんだ10を加熱溶融させ、配線パターン14
と半導体素子12をはんだ接合する。
First, as shown in FIG. 4, a film 20 made of polyimide resin is formed on a glass substrate 2 by a printing method at a position where a semiconductor element 10 is to be installed. After forming the film 20, chromium, copper, and chromium are deposited on the glass substrate 2 by vapor deposition to form the wiring pattern 14. Thereafter, a photo process and an etching process are carried out to form a wiring pattern, and the wiring pattern 14 necessary for the module is formed. The solder mask 16 has a three-layer structure of chromium, copper, and chromium, and the top layer of chromium is removed by etching in the form of a window to expose the copper in the lower pattern portion 14 so that only the copper can be soldered. I have to. The semiconductor element 10 is soldered with solder 1 in advance.
The soldering pattern of the substrate 2 and the solder 12 of the semiconductor element 10 are aligned and temporarily connected. In this state, the wiring pattern 14 and the solder are only in contact and are not completely joined. Next, the temporarily aligned module 8 is placed in a tunnel furnace 22 replaced with N2 gas, as shown in FIG. Here, module 8 is heated approximately by the preheating plate.
Preheated to 100℃. At the same time, the semiconductor element 10 is soldered to the center of the infrared lamp 26.
move it to the top surface. The second focus of the infrared lamp 26 is focused on the upper surface of the semiconductor element 10, and lighting of the infrared lamp 26 causes the semiconductor element 1 to
The upper surface of the solder 1 is heated, and the heat on the upper surface of the semiconductor element 10 is conducted inside the element 10 shown in FIG.
2 to reach the membrane 20. Here, semiconductor element 1
0 and the solder have high thermal conductivity, so the temperature rises rapidly. However, since polyimide resin with low thermal conductivity is used for the film 20, heat transfer is suppressed by the film 20, and the temperature rises rapidly at the bottom of the film 20. It is possible to suppress the temperature rise of certain glasses. Furthermore, by suppressing this heat transfer, the temperature of the solder 12 is accelerated. In this way, the solder 10 is heated and melted, and the wiring pattern 14
and the semiconductor element 12 are soldered together.

赤外線ランプ26から照射された赤外線は、半
導体素子10の外周部を通過して直接基板2に照
射される場合があり、このような状況において、
赤外線光が直接ポリイミド樹脂を照射することに
なると、樹脂の発熱が大きく、発熱した樹脂から
ガラス2への熱伝達によりガラス2を破損するこ
とになる。このため、膜20を半導体素子10の
下部にのみ設け、赤外線光が直接ポリイミド樹脂
に照射されない構成としている。
The infrared rays emitted from the infrared lamp 26 may pass through the outer periphery of the semiconductor element 10 and directly irradiate the substrate 2. In such a situation,
If the polyimide resin is directly irradiated with infrared light, the resin will generate a large amount of heat, and the glass 2 will be damaged due to heat transfer from the generated resin to the glass 2. For this reason, the film 20 is provided only under the semiconductor element 10, so that the polyimide resin is not directly irradiated with infrared light.

本実施例では熱伝導率が基板より小さい材料と
してポリイミド樹脂を用いているが、前記目的に
合致する材料であれば、ポリイミド樹脂以外の材
料も当然包含されるものである。さらに加熱方法
として赤外線ランプを用いているが、レーザ光を
用いた場合及び加熱ブロツクさらには加熱ガスを
用いた局所加熱方法にも十分適用される。
In this embodiment, polyimide resin is used as a material whose thermal conductivity is smaller than that of the substrate, but materials other than polyimide resin are naturally included as long as they meet the above purpose. Furthermore, although an infrared lamp is used as a heating method, it is also fully applicable to a case where a laser beam is used, a heating block, and a local heating method using a heated gas.

膜20の基板2上への形成は印刷法によつて行
なつたが、浸付法、スピンナー(回転塗布)等も
十分適用できる。
Although the film 20 was formed on the substrate 2 by a printing method, a dipping method, a spinner (rotary coating), or the like may also be used.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、半導体素子側からの加熱に対
し、熱伝導体の小さい膜が基板への熱伝達を抑制
するので、基板の温度勾配を小さくすることがで
き、基板の破損を防止する。さらに前記抑制効果
ははんだ付け部の昇温スピードを向上させはんだ
付け時間を短縮することが可能となり、耐熱性が
小さい部品への熱影響を小さくすることができ
る。
According to the present invention, the small thermal conductor film suppresses heat transfer to the substrate in response to heating from the semiconductor element side, so the temperature gradient of the substrate can be reduced and damage to the substrate can be prevented. Furthermore, the suppressing effect can improve the temperature rise speed of the soldered part, shorten the soldering time, and reduce the thermal influence on components with low heat resistance.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は液晶モジユールの斜視図、第2図は液
晶モジユールの断面図、第3図は従来法による半
導体素子取り付け部の断面図、第4図は本発明の
一実施例の半導体素子取り付け部の断面図、第5
図は半導体素子取付け方法を示す断面図である。 2……ガラス基板、8……液晶モジユール、1
0……半導体素子、12……はんだ、14……配
線パターン、20……膜、22……トンネル炉、
26……赤外線ランプ。
FIG. 1 is a perspective view of a liquid crystal module, FIG. 2 is a cross-sectional view of the liquid crystal module, FIG. 3 is a cross-sectional view of a conventional semiconductor element mounting part, and FIG. 4 is a semiconductor element mounting part of an embodiment of the present invention. 5th cross-sectional view of
The figure is a sectional view showing a method for attaching a semiconductor element. 2...Glass substrate, 8...Liquid crystal module, 1
0... Semiconductor element, 12... Solder, 14... Wiring pattern, 20... Film, 22... Tunnel furnace,
26...Infrared lamp.

Claims (1)

【特許請求の範囲】[Claims] 1 ガラス基板と、該ガラス基板上に設けられた
該ガラス基板の熱伝導率よりも小さい熱伝導率の
膜と、該膜上に設けられた配線パターンと、該配
線パターンと接続されたはんだ溶融接合部と、該
はんだ溶融接合部上に設けられた半導体素子とか
らなることを特徴とする半導体モジユール。
1. A glass substrate, a film provided on the glass substrate and having a thermal conductivity lower than that of the glass substrate, a wiring pattern provided on the film, and a solder melt connected to the wiring pattern. A semiconductor module comprising a joint portion and a semiconductor element provided on the solder fusion joint portion.
JP57226016A 1982-12-24 1982-12-24 Method of constructing circuit board Granted JPS59117188A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57226016A JPS59117188A (en) 1982-12-24 1982-12-24 Method of constructing circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57226016A JPS59117188A (en) 1982-12-24 1982-12-24 Method of constructing circuit board

Publications (2)

Publication Number Publication Date
JPS59117188A JPS59117188A (en) 1984-07-06
JPH0416941B2 true JPH0416941B2 (en) 1992-03-25

Family

ID=16838464

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57226016A Granted JPS59117188A (en) 1982-12-24 1982-12-24 Method of constructing circuit board

Country Status (1)

Country Link
JP (1) JPS59117188A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51150671A (en) * 1975-06-19 1976-12-24 Sharp Kk Method of fixing electronic parts
JPS5726493A (en) * 1980-07-23 1982-02-12 Alps Electric Co Ltd Circuit board
JPS57147246A (en) * 1981-03-06 1982-09-11 Hitachi Ltd Circuit board

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51150671A (en) * 1975-06-19 1976-12-24 Sharp Kk Method of fixing electronic parts
JPS5726493A (en) * 1980-07-23 1982-02-12 Alps Electric Co Ltd Circuit board
JPS57147246A (en) * 1981-03-06 1982-09-11 Hitachi Ltd Circuit board

Also Published As

Publication number Publication date
JPS59117188A (en) 1984-07-06

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