JPH04167584A - Printed wiring board - Google Patents
Printed wiring boardInfo
- Publication number
- JPH04167584A JPH04167584A JP29608890A JP29608890A JPH04167584A JP H04167584 A JPH04167584 A JP H04167584A JP 29608890 A JP29608890 A JP 29608890A JP 29608890 A JP29608890 A JP 29608890A JP H04167584 A JPH04167584 A JP H04167584A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- printed wiring
- wiring board
- circuit connection
- test
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000007689 inspection Methods 0.000 claims description 16
- 238000000034 method Methods 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 3
- 238000005452 bending Methods 0.000 description 2
- 101100136092 Drosophila melanogaster peng gene Proteins 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は印刷配線板に関し、特に表面実装型集積回路を
搭載する印刷配線板に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a printed wiring board, and particularly to a printed wiring board on which a surface-mounted integrated circuit is mounted.
従来、この種の表面実装型集積回路の搭載に用いられる
印刷配線板は、第２図に示すように、絶縁層５上に集積
回路接続用パッド１と検査用ランド３を決められた設計
基準に従って集積回路接続用パッド１と検査用ランド３
をライン２で接続して形成されていた。Conventionally, printed wiring boards used to mount this type of surface-mount integrated circuit have been designed according to a predetermined design standard in which integrated circuit connection pads 1 and test lands 3 are provided on an insulating layer 5, as shown in FIG. According to the integrated circuit connection pad 1 and test land 3
were formed by connecting them with line 2.
しかしながら上述した従来の印刷配線板には、以下のよ
うな欠点があった。However, the conventional printed wiring board described above has the following drawbacks.
（１）検査用ランド３を２．５４−格子にのせると、集
積回路接続用パッドｌから検査用ランド３までの距離が
長いため、印刷配線板１枚の中で占有する面積が大きく
、部品の実装密度が上らない。また、面積を小さくする
ため検査用ランド３を２．５４ｍｍ格子からはずすと、
汎用布線検査機を使用することができないため検査コス
トが上がる。(1) When the test land 3 is placed on a 2.54-grid, the distance from the integrated circuit connection pad l to the test land 3 is long, so the area occupied on one printed wiring board is large. The mounting density of components cannot be increased. Also, in order to reduce the area, if the inspection land 3 is removed from the 2.54mm grid,
Inspection costs increase because a general-purpose wiring inspection machine cannot be used.
（２）ライン２の幅が設計基準の制約を受ける他の信号
ラインと同じ細い幅で（例えば０．１２ｍｍ）で形成さ
れている為、集積回路接続用パッド１と検査用ランド３
の間も布線検査を行う必要がある。(2) Since the width of line 2 is the same narrow width as other signal lines (for example, 0.12 mm) which is subject to design standard restrictions, the width of line 2 is as narrow as that of other signal lines (for example, 0.12 mm).
It is also necessary to perform wiring inspection during this period.
本発明の目的は、部品実装密度が高く、汎用布線検査機
が使用できる安価で、集積回路接続用パッドと検査用ラ
ンド間のラインの布線検査を省略できる印刷配線板を提
供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a printed wiring board that has a high component mounting density, is inexpensive, can be used with a general-purpose wiring inspection machine, and can omit wiring inspection of lines between integrated circuit connection pads and inspection lands. be.
本発明は、４８ピンの表面実装型集積回路を実装する印
刷配線板において、前記集積回路の前記４８ピンのそれ
ぞれの近くに２．５４ｍｍ格子にのった検査用ランドを
有し、該検査用ランドと集積回路接続用パッドを結ぶラ
インの幅が０．２５ｍｍ、前記集積回路接続用パッドと
前記検査用ランドと前記ラインとによって形成される回
路の最小間隔が０．２５ｍｍ、該回路を含む長方形の面
積が少くとも５．２３ａｌｌであるパターンを有してい
る。The present invention provides a printed wiring board on which a 48-pin surface mount integrated circuit is mounted, which has a test land on a 2.54 mm grid near each of the 48 pins of the integrated circuit, and The width of the line connecting the land and the integrated circuit connection pad is 0.25 mm, the minimum interval of the circuit formed by the integrated circuit connection pad, the inspection land, and the line is 0.25 mm, and a rectangle containing the circuit. The pattern has an area of at least 5.23all.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例の平面図である。FIG. 1 is a plan view of one embodiment of the present invention.
第１図に示すように、集積回路接続用ノ（ラド１は、基
準点４を中心として上下、左右にそれぞれ１２個づつ配
置され、パッド間ピッチは０．５ ｍｍである。As shown in FIG. 1, the pads 1 for connecting integrated circuits are arranged 12 each on the upper, lower, left and right sides of the reference point 4, and the pitch between the pads is 0.5 mm.
２．５４ｍｍ格子上にのる検査用ランド３は、集積回路
接続用パッド１の外側に位置し、それぞれ２列に並んで
配置されている。The test lands 3 on the 2.54 mm grid are located outside the integrated circuit connection pads 1, and are arranged in two rows.
ライン２は、検査用ランド３と集積回路接続用パッド１
を接続している。ライン２の始点は、集積回路接続用パ
ッド１の中心であり、終点は検査用ランド３の中心であ
る。Line 2 is a test land 3 and an integrated circuit connection pad 1.
are connected. The starting point of the line 2 is the center of the integrated circuit connection pad 1, and the ending point is the center of the test land 3.
基準点４を座標値（０，Ｏ）の原点とした時のライン２
の始点、屈曲点、終点の座標値を以下に示す。Line 2 when reference point 4 is the origin of coordinate values (0, O)
The coordinate values of the starting point, bending point, and ending point are shown below.
ここで（１）は始点、乙〕は屈曲点、（、）は終点を表
わし、単位は、鵬である。Here, (1) represents the starting point, Otsu] represents the bending point, and (,) represents the ending point, and the unit is peng.
Ｏ（−２，７５０，４，３５０）［−６，３５０，８，
２５６コ［−２，７５０，５，５８８］（−６，３５０
，８，８９０）
Ｏ（−２，２５０，４，３５０）［−５，３３４，１０
，４１４コ［−５，３３４，８，３８２１［−５，０８
１，８，２５６］［−２，２５０，６，０９６］（−６
，３５０，１１，４３０）ｏ（−１，７５０，４，３５
０）［−３，８１０，８，２５６］［−１，７５０，６
，６０４］（−３，８１０，８，８９０）
Ｏ（−１，２５０，４，３５０）［−２，７９４，１０
，４１４コ［−２，７９４，８，３８２コ［−２，５４
１，８，２５６］［−１，２５０，７，１１２］（−３
，８１０，１１，４３０）Ｏ（−０，７５０，４，３５
０）［−１，２７０，８，２５６］［−０，７５０，７
，６２０］（−１，２７０，８，８９０）
−（−０，２５０，４，３５のロー０．２５４，１０．
４１４コ［−０，２５４，８，３８２］［−０，２５０
，８，２５６コ（−１，２７０，１１，４３０）Ｏ（０
，２５０，４，３５０）［１，２７０，８，２５６］［
０，２５０，７，６２０コ（１，２７０，８，８９０）
ｏ （０，７５０，４，３５０）［２，２８６，１０
，４１４コ［２，２８６，８，３８２］口２．５４０．
８．２５６］［０，７５０，７，１１２］（１，２７０
，１１，４３０）０（１，２５０，４，３５０）［３，
８１０，８，２５６］［１，２５０，６，６０４］（３
，８１０，８，８９０）
Ｏ（１，７５０，４，３５０）［４，８２６，１０，４
１４］［４，８２６，８，３８２コ［５，０８０，８，
２５６コ［１，７５０，６，０９６］（３，８１０，１
１，４３０）Ｏ（２，２５０，４，３５０）［６，３５
０，８，２５６］［２，２５０，５，５８８コ（６，３
５０，８，８９０）
Ｏ（２，７５０，４，３５０）［７，３６６，１０，４
１４］［７，３６６、８，３８２］［７，６２０，８，
２５６コ［２，７５０，５，０８０］（６，３５０，１
１，４３０）以上、上述した座標値は、ライン２の１７
４の座標である。残りの座標値は、上述した座標値を基
準点４を原点として、９０°、１８０°、２７０゜回転
することによって得ることができる。O(-2,750,4,350) [-6,350,8,
256 [-2,750,5,588] (-6,350
,8,890) O(-2,250,4,350)[-5,334,10
,414 [-5,334,8,3821[-5,08
1,8,256][-2,250,6,096](-6
,350,11,430)o(-1,750,4,35
0) [-3,810,8,256] [-1,750,6
,604](-3,810,8,890) O(-1,250,4,350)[-2,794,10
,414 pieces [-2,794,8,382 pieces [-2,54
1,8,256][-1,250,7,112](-3
,810,11,430)O(-0,750,4,35
0) [-1,270,8,256] [-0,750,7
,620](-1,270,8,890) -(-0,250,4,35 rho 0.254,10.
414 pieces [-0,254,8,382] [-0,250
,8,256 (-1,270,11,430)O(0
,250,4,350) [1,270,8,256][
0,250,7,620 (1,270,8,890) o (0,750,4,350) [2,286,10
,414 pieces [2,286,8,382] mouths 2.540.
8.256] [0,750,7,112] (1,270
,11,430)0(1,250,4,350)[3,
810,8,256][1,250,6,604](3
,810,8,890) O(1,750,4,350)[4,826,10,4
14] [4,826,8,382 [5,080,8,
256 pieces [1,750,6,096] (3,810,1
1,430)O(2,250,4,350)[6,35
0,8,256] [2,250,5,588 (6,3
50,8,890) O(2,750,4,350)[7,366,10,4
14] [7,366,8,382][7,620,8,
256 pieces [2,750,5,080] (6,350,1
1,430) Above, the coordinate values mentioned above are 17 of line 2.
These are the coordinates of 4. The remaining coordinate values can be obtained by rotating the above-mentioned coordinate values by 90°, 180°, and 270° with reference point 4 as the origin.
また、検査用ランド３を２．５４ｍｍの格子にのせるた
めに基準点４の基板原点（図示省略）からの座標値（Ｘ
、Ｙ）を
Ｘ＝１．２７＋２．５４ｎ ｎ ＝整数 単位は−
Ｙ＝１．２７＋２．５４ｍ ｍ＝整数 単位は閣と
する。In addition, in order to place the inspection land 3 on a 2.54 mm grid, the coordinate value (X
, Y) as X=1.27+2.54n n = integer unit is -
Y=1.27+2.54m m=integer The unit is cabinet.
以上説明したように本発明は、次に列挙する効果がある
。As explained above, the present invention has the following effects.
（１） 印刷配線板上で検査用ランドを有する表面実
装型集積回路の占有する面積が５２３ｄ以下で、従来に
比べ５６％以下となるため、実装密度が上がる。(1) The area occupied by the surface mount integrated circuit having the inspection land on the printed wiring board is 523 d or less, which is 56% or less compared to the conventional one, so the packaging density is increased.
（之）検査用ランドが２．５４ｍｍ格子にのっているの
で、汎用布線検査機を適用できる。特に、０．５閣ピツ
チのパッドを直接検査するためには高価な検査装置が必
要で、かつ、接触の不安定等により品質面でも問題があ
るためこの効果は大きい。(No.) Since the inspection land is on a 2.54 mm grid, a general-purpose wiring inspection machine can be applied. In particular, this effect is significant because direct inspection of 0.5 pitch pads requires an expensive inspection device and also poses quality problems due to unstable contact.
（３）集積回路接続用パッドと検査用ランドを結ぶライ
ンのライン幅を従来の回路パターンに比べて太くでき、
その間隔も広くとれるので、オープン・ショート等のト
ラブルがなく、このライン部分の布線試験を省略できる
。(3) The line width of the line connecting the integrated circuit connection pad and the test land can be made thicker than that of conventional circuit patterns.
Since the spacing between them is wide, there are no problems such as open/short circuits, and the wiring test for this line part can be omitted.
第１図は本発明の一実施例の平面図、第２図は従来の印
刷配線板の一例の平面図である。
ｌ・・・・・・接続用パッド、２・・・・・・ライン、
３・・・・・・検査用ランド、４・・・・・・基準点、
５・・・・・・絶縁層。
代理人 弁理士 内 原 音
第１図FIG. 1 is a plan view of an embodiment of the present invention, and FIG. 2 is a plan view of an example of a conventional printed wiring board. l...Connection pad, 2...Line,
3...Inspection land, 4...Reference point,
5...Insulating layer. Agent Patent Attorney Oto Uchihara Figure 1
Claims (1)
おいて、前記集積回路の前記４８ピンのそれぞれの近く
に２．５４ｍｍ格子にのった検査用ランドを有し、該検
査用ランドと集積回路接続用パッドを結ぶラインの幅が
０．２５ｍｍ、前記集積回路接続用パッドと前記検査用
ランドと前記ラインとによって形成される回路の最小間
隔が０．２５ｍｍ、該回路を含む長方形の面積が少くと
も５．２３ｃｍ＾２であるパターンを有することを特徴
とする印刷配線板In a printed wiring board on which a 48-pin surface mount integrated circuit is mounted, a test land is provided in a 2.54 mm grid near each of the 48 pins of the integrated circuit, and the test land and the integrated circuit are arranged in a 2.54 mm grid. The width of the line connecting the connection pads is 0.25 mm, the minimum interval between the circuits formed by the integrated circuit connection pads, the inspection lands, and the lines is 0.25 mm, and the area of the rectangle containing the circuit is small. A printed wiring board characterized by having a pattern that is both 5.23 cm^2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29608890A JPH04167584A (en) | 1990-10-31 | 1990-10-31 | Printed wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29608890A JPH04167584A (en) | 1990-10-31 | 1990-10-31 | Printed wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04167584A true JPH04167584A (en) | 1992-06-15 |
Family
ID=17828967
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29608890A Pending JPH04167584A (en) | 1990-10-31 | 1990-10-31 | Printed wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04167584A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1995009459A1 (en) * | 1993-09-30 | 1995-04-06 | Atmel Corporation | Tab testing of area array interconnected chips |
| CN102209433A (en) * | 2010-03-30 | 2011-10-05 | 鸿富锦精密工业（深圳）有限公司 | Circuit board pin layout framework |
| CN103985701A (en) * | 2013-02-08 | 2014-08-13 | 欣兴电子股份有限公司 | Package substrate and detection method thereof |
-
1990
- 1990-10-31 JP JP29608890A patent/JPH04167584A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1995009459A1 (en) * | 1993-09-30 | 1995-04-06 | Atmel Corporation | Tab testing of area array interconnected chips |
| CN102209433A (en) * | 2010-03-30 | 2011-10-05 | 鸿富锦精密工业（深圳）有限公司 | Circuit board pin layout framework |
| CN103985701A (en) * | 2013-02-08 | 2014-08-13 | 欣兴电子股份有限公司 | Package substrate and detection method thereof |
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