JPH04167171A - Correlation arithmetic unit - Google Patents

Abstract

PURPOSE:To prevent unrequired turbulence in a correlation value by computing the correlation value between a pattern circulating and changing sequentially by an input fetching means and a comparison pattern by a correlation arithmetic means. CONSTITUTION:A reception signal S1 is supplied to a non-circulation type shift register circuit 21 sequentially, and it transferred to a circulation type shift register circuit 22 when the reception signal S1 of one cycle of pattern is stored. In other words, the pattern of the reception signal S1 before one cycle of the pattern of the reception signal S1 for which the non-circulation type shift register circuit 21 is performing a storing operation is stored. Therefore, while the pattern kind of the reception signal S1 is fixed and the same kind of pattern is changing at a prescribed cycle, the storing contents of those shift registers 21, 22 are set equally, and correlation output S6 taking an intended correlation value can be obtained in spite of coincidence/noncoincidence with the comparison pattern S4. Thereby, it is possible to prevent erroneous detection for a cyclic point and the turbulence of a demodulation operation from occurring.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a correlation calculation device, and can be applied to, for example, a receiving device in spread spectrum communication.

[Prior Art] For example, in a receiving device in spread spectrum communication, a correlation between a received signal pattern and an internally generated comparison pattern is determined to determine the type of received signal pattern or to establish synchronization with the received signal. It also detects the presence or absence of a received signal.

FIG. 4 shows a conventional correlation calculation device provided in such a receiving device.

In FIG. 4, this correlation calculation device 10 has a digital matched filter configuration capable of high-speed calculation, and includes an acyclic shift register circuit 11 having an m film configuration, and m exclusive shift register circuits as a coincidence/mismatch detection circuit. It is composed of NOR circuits (multipliers when the received signal and comparison pattern are multivalued or analog) 121 to 12m and an adder 13.

Here, m is the number of elements in one period of the received signal pattern (for example, the number of bits in the case of a 1-bit pattern).

The received signal S1 and the received signal clock S2 synchronized with the received signal S1 are provided to the acyclic shift register circuit 11. Shift register times #! 11 sequentially transitions the serially applied reception signal S1 every time the reception signal clock S2 is applied. Note that the pattern of the received signal S1 includes, for example, an M-series pattern and a gold-series pattern.

The values 831-83m of each stage of the shift register circuit 11 are taken out in parallel as a pattern and applied to the corresponding exclusive NOR circuits 121-12m.

In addition, these exclusive Noah circuits 121 to 12m
each of the elements 341 to 34 of the comparison pattern S4
m is given. Each exclusive Noah circuit 12
x (x is 1 to m) takes logic r1 when the value S3x of the Xth stage of the shift register circuit 11 and the element S4x of the comparison pattern S4 match, and when they do not match, the logic r1. The comparison result S5x which takes logic “0” is added to the adder 1.
Give to 3.

The adder 13 connects each exclusive NOR circuit 121 to 1
2m comparison results 851 to 85m are added, and the added value S
6 is output as the correlation value.

In fact, during the period in which the pattern of the received signal S1 is fixed, the comparison pattern S4 is fixed to the same type as the pattern of the received signal S1.

In such a situation, the correlation output S6 repeatedly changes with the period of the pattern of the received signal S1, as shown in FIG. As shown in A>, a peak value is taken once every period, and a constant value is taken in other periods.Based on such correlation output information (for example, information on the position and size of the bird), synchronization is performed. Establishment, detect pattern changes in the transmission system, and detect the presence or absence of transmission signals.

[Problems to be Solved by the Invention] Incidentally, in order to transmit information, it is necessary for the transmission system to switch the output pattern. Such switching itself is almost always performed in synchronization with the pattern cycle.

However, the above-mentioned acyclic shift register #1
Since the pattern of the received signal S1 is serially input to the shift register circuit 11, the values S31, ... S3m stored in the shift register circuit 11 are the values according to the received signal pattern before switching and the received signal pattern after switching. There may be cases where the values are mixed.

The correlation output between the entire received signal pattern of one type and the comparison pattern can be made to peak only at the correct synchronization point, as shown in FIG. pattern 831-3
The correlation output between 3m and comparison pattern S4 is shown in Figure 5(B).
As shown in Fig. 2, false target NPs may occur.

If a synchronization point is established using such a false peak NP, the demodulation operation cannot be performed accurately. Furthermore, after all the contents of the shift register circuit 11 have changed to the elements of the switched pattern, the switching of the pattern can be obtained from the correlation output information, but the synchronization point must be changed first before proceeding to this recognition process. There was a problem in that switching detection was delayed accordingly.

The present invention has been made in consideration of the above points, and is capable of suppressing unnecessary disturbances in the correlation output between the input pattern (for example, the received signal pattern in the case of a receiving device) and the internally generated comparison pattern. The purpose of this invention is to provide a correlation calculation device that can perform the following functions.

[Means for Solving the Problem] In order to solve the problem, the present invention provides a correlation calculation device that calculates a correlation value between a pattern of an externally applied input signal having periodicity and a comparison pattern.
an input acquisition means for dividing and inputting the input signal given serially for each cycle of the input signal pattern and circulating the input signal, and calculating a correlation value between the pattern that is circulated by the input acquisition means and changes sequentially, and the comparison pattern. and correlation calculation means.

[Operation] In the present invention, the input acquisition means divides and inputs the serially applied input signal every cycle of the input signal pattern and circulates it, and the correlation calculation means is circulated by the input acquisition means and changes sequentially. A correlation value between the pattern and the comparison pattern is calculated.

As a result, when the pattern of the input signal changes and the input signal string includes elements of two types of patterns, the correlation value with the comparison pattern is not calculated, and unnecessary disturbance of the correlation value can be prevented.

[Embodiment 1] Hereinafter, first to third embodiments of the present invention will be sequentially described in detail with reference to the drawings.

fake counterfeit FIG. 1 is a block diagram showing a first embodiment of the present invention.

This first embodiment differs from the conventional device in the configuration provided to the exclusive NOR circuit that takes in the received signal and actually compares its patterns, but the other configurations are similar to the conventional device. Therefore, in FIG. 1, parts corresponding to those in FIG. 4 showing the conventional device are given the same reference numerals.

In FIG. 1, the correlation calculation device 20 of the first embodiment includes exclusive NOR circuits 121 to 12 similar to the conventional one.
m and an adder 13, and further includes an acyclic shift register circuit 21 and a cyclic shift register circuit 22.
It is equipped with

The received signal S1 and the received signal clock S2 formed based on the received signal are sent to an acyclic shift register circuit 2.
1 is given. The acyclic shift register circuit 21 is
Every time the reception signal clock S2 is applied, the reception signal S1 applied serially is sequentially taken in and transitioned.

Each stage 211 to 21m of the acyclic shift register circuit 21
are each stage 22 of the cyclic shift register circuit 22.
Connected to 2-22m. The cyclic shift register circuit 22 changes the output value 8 of each stage of the acyclic shift register circuit 21 when given a cycle start signal S7 of the pattern of the received signal S1, which is formed from the correlation output S6, for example.
Take in 81-88m. Cyclic shift register circuit 2
2, each time the received signal clock S2 is applied, the received signal pattern 58 (the pattern of the received signal S1 one cycle before) taken in parallel from the acyclic shift register circuit 21 is sequentially circulated and transitioned. The values 391 to 39m of each stage of the cyclic shift register circuit 22 are taken out in parallel and sent to the corresponding exclusive NOR circuit 121.
~12m.

These exclusive NOR circuits 121-12m are provided with respective elements 841-34m of comparison pattern S4, respectively. Each exclusive Noah circuit 12X (X
1 to m) take the logic rl when the X-th stage value S9x of the cyclic shift register circuit 22 and the X-th element S4x of the comparison pattern S4 match, and take the logic rl when they do not match. The comparison result S5x which takes logic "0" is sent to adder 1.
3, and the adder 13 supplies each exclusive NOR circuit 1
The comparison results 851-85m of 21-12m are added and the added value S6 is output as a correlation value.

In the above configuration, the received signal S1 is sequentially applied to the acyclic shift register circuit #121, and is transferred to the cyclic shift register circuit 22 when the received signal S1 for one period of the pattern is stored.

That is, the pattern of the received signal S1 that is one period earlier than the period of the pattern of the received signal S1 during which the acyclic shift register circuit 21 is in the storing operation is stored in the cyclic shift register circuit 22.

Therefore, while the pattern type of the received signal S1 is fixed and the same type of pattern changes at a predetermined period,
The contents stored in the acyclic shift register circuit 21 and the contents stored in the cyclic shift register circuit 22 are the same, although they differ by one period (strictly speaking, the noise components mixed in the transmission system may be different). ), as in the prior art, a correlation output S6 is obtained that takes the intended correlation value both when it matches the comparison pattern S4 and when it does not match.

When the sending side switches the sending pattern at pattern intervals,
Naturally, the received signal S1 given to the correlation calculation device 20
The pattern also changes. As a result, there is a timing when elements of two types of patterns are mixedly stored in the acyclic shift register circuit 21. However, when the cyclic shift register circuit 22 is given the cycle start signal S7, the stored content S of the acyclic shift register circuit 21 is
81 to 88 m, so that when the acyclic shift register circuit 21 stores elements of two types of patterns in a mixed manner, loading is executed, and the pattern of the type before switching also matches the type of pattern after switching. The pattern is also completely accommodated in the cyclic shift register circuit 22.

As a result, although both the pre-switching type of pattern and the post-switching type of pattern transition, they are compared with the comparison pattern S4 in a complete state consisting only of the elements of that type of pattern,
A correlation output S6 having a correlation value without unnecessary correlation peaks is obtained.

That is, according to the first embodiment described above, a comparison with a comparison pattern is not performed in a received signal state in which elements of two types of patterns coexist, and unnecessary correlation peaks do not occur. Therefore, erroneous detection of synchronization points and disturbances in demodulation operation can be prevented.

A second embodiment of the present invention will now be described in detail with reference to the drawings. FIG. 2 is a block diagram showing the configuration of this second embodiment, and parts corresponding to those in FIG. 1 are designated by the same reference numerals.

The correlation calculation device 30 of the second embodiment uses one shift register circuit as an acyclic shift register circuit and a cyclic shift register circuit in a time-sharing manner, and achieves the same effect as the first embodiment. This is how it was done.

In FIG. 2, the correlation calculation device 30 of the second embodiment has exclusive soar circuits 121 to 12 similar to the conventional one.
m and an adder 13, and further includes a received signal S1
The shift register circuit 31 for taking in the shift register circuit 31, the input switching circuit 32 that switches the input signal to the shift register circuit 31, the clock switching circuit 33 that switches the clock to the shift register circuit 31, and the time of the correlation output S6 from the adder 13. A time axis expansion circuit 34 is provided to expand the axis.

The received signal S1 is given to the input switching circuit 32 as a selection input. In addition, the input switching circuit 32: - The value of the final stage of the shift register circuit 31 is given as another selection input. The received signal clock S2 formed from the received signal is given to the clock switching circuit 33 as a selection input. Further, the clock switching circuit 33 is supplied with the correlation calculation clock SIO as another selection input. A cycle start signal S7 is given to these input switching circuit 32 and clock switching circuit 33 as a selection control signal.

Here, the correlation calculation clock SIO has a frequency m times that of the received signal clock S2 (m is the number of stages of the shift register circuit 31). Furthermore, the period start signal S7 is a period belonging to a period from when a new period of the received signal pattern S1 starts until the first received signal clock S2 in that period is generated, and is a period belonging to the m correlation calculation clocks 810.
A period including the period (hereinafter referred to as a correlation calculation period) is represented by one logic level, and another period (hereinafter referred to as a pattern capture period) is represented by the other logic level.

When the cycle start signal S7 indicates a pattern capture period, the input switching circuit 32 selects the received signal S1, and the clock switching circuit 33 selects the received signal clock S2.

Thereby, the shift register circuit 31 functions as an acyclic shift register circuit, and each time the received signal clock S2 is applied, the shift register circuit 31 sequentially takes in and shifts the received signal S1. When the received signal S1 for one period of the pattern is taken into the shift register circuit 31 and the next period begins, the period start signal S7 indicates a correlation calculation period.

At this time, the input switching circuit 32 selects the final stage value of the shift register circuit 31, and the clock switching circuit 33 selects the correlation calculation clock SIO. In this way, the shift register circuit 31 functions as a cyclic shift register circuit, and makes one cycle of the captured pattern of the received signal S1 for one cycle during the correlation calculation period.

Therefore, even if the pattern type is switched in the transmission system, the patterns of the received signal S1 that are cycled within the correlation calculation period are of the same type. That is, in a state where elements of two types of patterns before and after pattern switching are mixed, the pattern of the received signal S1 is not cycled through within the correlation calculation period.

Each stored value 8111 to SLim of the shift register circuit 31
are taken out in parallel and given to exclusive NOR circuits 121 to 12m, and compared with each element 341 to 84m of comparison pattern S4, and the comparison results 851 to 35m are added by adder 13 and output as correlation output S6. be done.

This correlation output S6 is output during both the pattern acquisition period and the correlation calculation period, but the correlation output S6 during the pattern acquisition period is discarded as described later by the time axis conversion diagram B34.

The time axis conversion circuit 34 is composed of, for example, a FIFO memory, and is supplied with a period start signal S7, a reception signal clock S2, and a correlation calculation clock S10, and is provided with a period start signal S7, a reception signal clock S2, and a correlation calculation clock S10.
7 indicates the correlation calculation period, the correlation output S6 is taken in based on the correlation calculation clock S10, and when the cycle start signal S7 indicates the pattern acquisition period, the correlation output S6 is read based on the received signal clock S2. As a result, a final correlation output S60 obtained by extending the time axis of the correlation output S6 during the correlation calculation period is obtained and output.

According to the second embodiment, the correlation output S60 is not outputted in a received signal state in which elements of two types of patterns coexist, and unnecessary correlation value peaks are not generated. Therefore, erroneous detection of synchronization points and disturbances in demodulation operation can be prevented.

A third embodiment of the present invention will be described below with reference to the drawings. FIG. 3 shows the main structure of this third embodiment.

This third embodiment is a partial modification of the first and second embodiments. That is, the received signal S1 taken out in parallel from the shift register circuit 22 or 31
Each element of the pattern 881-88m or 8111-81
1m and the elements S41 to S4m of the comparison pattern S4 are performed without using the exclusive NOR circuits 121 to 12m.

Note that the first example and the second example are based on the comparison pattern S4.
It can also be applied to cases where the
The embodiment is applicable only when the comparison pattern S4 is fixed. For example, it can be applied when the transmission pattern is switched between the comparison pattern S4 and the logical inversion pattern of the comparison pattern S4, and the comparison pattern S4 itself does not need to be changed.

Now, an element S4x (x is 1 to m
) is logical "1". In this case, if the element S8x or St lx of the shift register circuit 22 or 31 is logic "1", it matches, so a logic "1" is output as the comparison result S5x, and the element S8x or St lx of the shift register circuit 22 or 31 is If it is a logic "0", there is a mismatch, so it is necessary to output a logic "0" as the comparison result S5x. Therefore, element S4 with comparison pattern S4
When X is logic "1", the logic level of the element S8x or 5llX of the given shift register circuit 22 or 31 matches the logic level of the comparison result S5x, and the logic level of the element S8x or Sl of the shift register circuit 22 or 31 matches. The adder 13 uses the logic level of lx as it is as the comparison result S5x.
can be given to

Next, an element S4y (y is 1 to
Consider the case where m) is logical "0". In this case, element S8y of the shift register circuit 22 or 31 matches if Sl ly is logic r□, so it outputs logic "1" as the comparison result S5y, and
Element S8. If y or Sl iy is logic "1", there is a mismatch, so it is necessary to output logic "0" as the comparison result S5y. Therefore, if a certain element S4y of the comparison pattern S4 is logic "0", the given shift register times! The logic level of the element S8y or 511y of 22 or 31 and the logic level of the comparison result S5y are opposite,
Element S8y or Sl of shift register circuit 22 or 31
The logic level of ly can be inverted and provided to the adder 13 as a comparison result S5y.

The third embodiment was made based on this idea, and FIG. 3 shows that the comparison pattern S4 is "101...001".
”. That is, comparison pattern S
For the logic "1" element S4x of 4, the logic level of the element s8X or Sl lx of the shift register circuit 22 or 31 is directly given to the adder 13 as a comparison result S5x,
Regarding the logic "0" element S4y of the comparison pattern S4, the logic level of the element S8y or Sl y of the shift register circuit F13fI22 or 31 is changed by the inverter circuit 42...
- It is inverted via 4(m-2) and 4(m-1) and given to the adder 13 as a comparison result S5y.

Therefore, according to the third embodiment, the same effects as those of the first and second embodiments described above are achieved, and the overall structure is further simplified.

Other Examples The correlation calculation device of the present invention is applicable not only to receiving devices but also to other devices.

Furthermore, it can be applied to correlation calculations not only for binary patterns but also for multi-value patterns.

[Effects of the Invention] As described above, according to the present invention, the input capturing means divides and captures the serially applied input signal for each period of the input signal pattern, circulates it for one period, and calculates the correlation calculation means. is circulated by this input acquisition means to calculate the correlation value between the pattern that changes sequentially and the comparison pattern, so when the input signal pattern changes and the input signal contains two types of pattern elements, the comparison pattern It is possible to prevent the obtained correlation value from having unnecessary correlation peaks, etc., because the correlation value is not calculated.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment of a correlation calculation device according to the invention, FIG. 2 is a block diagram showing a second embodiment of the invention, and FIG. 3 is a block diagram showing a third embodiment of the invention. figure,
FIG. 4 is a block diagram showing a conventional device, and FIG. 5 is an explanatory diagram of the drawbacks of the conventional device. 121~12m...exclusive Noah circuit, 13
...Adder, 20.30...Correlation calculation device, 21.
...Acyclic shift register circuit, 22...Cyclic shift register circuit, 31...Shift register circuit, 3
2... Input switching circuit, 33... Tarot switching circuit,
42.4 (m-2>, 4 (m-1>...inverter circuit.

Claims (1)

[Scope of Claims] (1) In a correlation calculation device that calculates a correlation value between a pattern of an input signal having periodicity given from the outside and a comparison pattern, the above input signal given serially is processed for one period of the input signal pattern. A correlation operation characterized by comprising: an input acquisition means for dividing and inputting and circulating each pattern, and a correlation calculation means for calculating a correlation value between a pattern that is circulated by the input acquisition means and changes sequentially, and a comparison pattern. Device. (2) When the input acquisition means includes acyclic shift register means that sequentially acquires the input signals applied serially, and when the input signal for one cycle of the input signal pattern is stored in the acyclic shift register means. 2. The correlation calculation device according to claim 1, further comprising cyclic shift register means which receives the input signal in parallel and then circulates the input signal. (3) The input acquisition means is constituted by one shift register means, and this shift register means is used as an acyclic shift register means for sequentially acquiring the input signal applied serially, and this acyclic shift register Claim 1 characterized in that when used as a means, when an input signal for one period of an input signal pattern is stored, it is used as a cyclic shift register means for circulating the input signal in a time-division manner. The correlation calculation device described in . (4) The correlation calculation device according to any one of claims 1 to 3, wherein the input signal is a binary signal. (5) The above-mentioned correlation calculation means directly uses the logic level of the element to be compared with the element at one logic level of the comparison pattern as a comparison result, and also calculates the logic level of the element to be compared with the element at the other logic level of the comparison pattern. 5. The correlation calculation device according to claim 4, comprising a comparison means for inverting the level to obtain a comparison result, and an addition means for adding the comparison results for each element by the comparison means.