JPH04165404A - Sequence controller - Google Patents

Abstract

PURPOSE:To prevent the time required for main program execution from becoming extremely long by providing a common storage part with a received data presence/absence flag, and checking this flag by a central arithmetic processing unit (CPU) and inputting received data. CONSTITUTION:The common storage part 3 is equipped with the received data presence/absence flag 17 and a received data size area 18. When an external reception interruption signal 10 is generated, a communication control processor 2 writes the data and its data size in a received data area 5 and the received data size area 18 when the flag 17 is '0' and sets the flag 17 to '1'. A CPU 1, on the other hand, performs flag check operation 14 periodically to perform receiving operation 7 for the received data and reset the flat 17 to '0' when the flag 17 is '1'. Consequently, the CPU inputs the received data without any reception interruption, so the execution speed of a main program which performs the sequence control of the CPU never becomes slow.

Description

[Detailed description of the invention] Industrial application field The present invention is applicable to various FA (factory automation)
The present invention relates to a sequence control device that controls a sequence control device.

BACKGROUND OF THE INVENTION In recent years, sequence control devices that control various types of FA have become more sophisticated and faster. A conventional example of such a sequence control device will be explained with reference to FIGS. 4 and 5.

In Fig. 4, 1 is the central processing unit (hereinafter referred to as CPU).
It is sometimes called. ) to perform sequence control. 2 is a communication control processing device, which controls communication with others. Reference numeral 3a denotes a common storage unit between the CPIII and the communication processing bag W2, which is in the 2PORT-RAM format. 4 is a transmission data area in the common storage section 3a, and 5 is a reception data area in the common storage section 3a. 6 indicates the operation of writing received data from the communication control processing device 2 into the received data area 5. 7 shows an operation in which the CPUI takes in data from the received data area 5. 8 is C
This shows the work of writing data from PIII to the transmission data area 4. Reference numeral 9 indicates an operation in which the communication control processing device 2 takes in transmission data from the transmission data area. 10 is a reception interrupt signal sent to the communication control processing device 2 from the outside. 11 is from the communication control processing device 2 to CPt1l
This is the reception interrupt signal for the 12 is a transmission interrupt signal sent from the CPUI to the communication control processing device 2; 13 is a transmission interrupt signal sent from the communication control processing device 2 to the outside.

In the sequence control device configured as described above, when a reception interrupt signal 10 from the outside is generated, a data write operation 6 is performed, a reception interrupt signal 11 is generated to the CPUI in a chain, and a data write operation 7 is performed. will be held. FIG. 5 shows a main program for executing sequence control on the CPUI. C in step 1
When PtJl detects the reception interrupt signal 11, it interrupts the execution of the sequence control of the main program, moves to step 2, fetches the reception data from the common storage unit 3, and
Next, in step 3, data processing is performed.

Problem to be Solved by the Invention However, in the above configuration, the reception interrupt signal 11 to cpUl is generated every time the reception interrupt signal 10 from the outside is generated. When this occurs, the CPU must interrupt the execution of the main program and deal with the interrupt signal, resulting in a problem that the execution speed of the main program l5CAN becomes extremely slow. Also CPU
Since I needs to perform error control for the signal 11, there is also the problem that the burden placed on the CPU becomes heavy.

Means for Solving the Problems In order to solve the above problems, the present invention provides a central processing unit that executes sequence control, a communication control processing unit that transmits and receives data to and from the outside, and a communication control processing unit that transmits and receives data from the communication control processing unit. Sequence control consisting of a common storage unit having a reception data area that takes in received data and sends it to the central processing unit, and a transmission data area that takes in transmission data from the central processing unit and sends it to the communication control processing unit. The apparatus is characterized in that a received data presence/absence flag is provided in the common storage section, and the central processing unit checks the received data presence/absence flag to fetch received data from the received data area of the common storage section. .

According to the present invention, the CPU that executes sequence control checks the reception data presence/absence flag while executing the main program without receiving any reception interrupt signal.
It is possible to capture at most one piece of received data during the execution of the main program 1, and it is possible to prevent the time required for the execution of the main program 1 from becoming extremely slow.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to FIGS. 1 to 3.

In FIG. 1, 1 is a CPLI, 2 is a communication control processing unit, 3 is a common storage unit, 4 is a transmission data area, 5 is a reception data area, 6 is a task of writing received data, 7 is a task of importing received data, 8 is the work of writing the transmission data,
Reference numeral 9 indicates an operation to capture transmission data, IO indicates a reception interrupt signal, 12 indicates a transmission interrupt signal, and 13 indicates a transmission interrupt signal, which are basically the same as those explained for the conventional example shown in FIG. . However, unlike the conventional example, the common storage section 3 includes a transmission data presence/absence flag 15, a transmission data size area 16, a reception data presence/absence flag 17,
A received data size area 18 is provided. Further, in FIG. 1, 14 indicates the operation of checking the status of the reception flag from the CPU 1 to the common storage unit 3, and 19 indicates the operation of checking the status of the reception flag from the communication control processing device 2 to the common storage unit 3. , the reception interrupt signal 11 in FIG.
This is the behavior set in place of .

2 shows a main program for executing sequence control in the CPUI, and FIG. 3 shows a main program of the communication control processing device 2. As shown in FIG.

In FIG. 2, the old CP determines whether the received data presence/absence flag 17 is "1" in step 4 (see step 11 in FIG. 3), and if the flag is "1", it moves to step 5 and stores the data in the common memory. The received data is taken in from the section 3, and then the flag 17 is returned to "0" using the steering knob 6. In Ste Knob 4, if flag ``Oj'', step 7
No data is imported as shown in .

In FIG. 3, the communication control processing device 2 determines in step 8 whether or not the received data presence/absence flag 17 is "1", and if the flag is "1", the received data is transferred to the receive buffer as shown in step 9. No data is written to the common storage unit 3. On the other hand, if the flag is "0" in step 8, the process moves to step 10 and the data in the buffer into which data is taken in first among the plurality of buffers possessed by the communication control processing device 2 is stored in a common memory. 3, and then in step 11 the received data presence/absence flag 17 is set to "1".

Since the sequence control device of this embodiment is configured as described above, when the reception interrupt signal 10 is generated from the outside, the communication control processing device 2 sends the reception data presence flag 17
If the number is 0, the data and data size are stored in the received data area 5 and the received data size area 18 of the common storage unit 3.
and sets the flag 17 to "1". On the other hand, C
In the main program, the PU 1 periodically performs a flag check operation 14, and if the flag 17 is "11", performs a work 7 to import the received data, and checks the flag 1.
Return 7 to "0". When the received data in the received data area 5 is taken into the CPUI in this way, the flag 17
is "0", so the first received data among the received data stored in the receive buffer of the communication control device 2 is stored in the received data area 5 and the received data size area of the common storage unit 3 along with its data size. 18? This will be written.

Effects of the Invention According to the present invention, since the CPU can take in received data without receiving a reception interrupt, the CPLI
l5C of the main program that executes sequence control of
The execution speed of the AN does not become extremely slow, it is possible to properly execute sequence control, and the load on the CPU can be reduced.

[Brief explanation of the drawing]

1 to 3 show one embodiment of the present invention, FIG. 1 is a block diagram showing the overall configuration, FIG. 2 is a flowchart of the main program of the CPU, and FIG. 3 is the main program of the communication control processing device. Showing the flowchart of the program, the fourth
5 and 5 show a conventional example, FIG. 4 is a block diagram showing the overall configuration, and FIG. 5 is a flowchart of the main program of the CPU. i-1---Central processing unit (CP[J)2--
------Communication control processing device 3-----Common storage section 4-1--Transmission data area 5------Receiving data area 17--Receiving data presence/absence flag

Claims (1)

[Claims] (1) A central processing unit that executes sequence control;
a communication control processing device that transmits and receives data to and from the outside;
A common memory having a reception data area that takes in reception data from the communication control processing unit and sends it to the central processing unit, and a transmission data area that takes in transmission data from the central processing unit and sends it to the communication control processing unit. The sequence control device is configured such that a received data presence/absence flag is provided in the common storage section, and the central processing unit reads the received data from the received data area of the common storage section by checking the received data presence/absence flag. A sequence control device characterized by: