JPH04163973A - Variable color light emitting diode - Google Patents
Variable color light emitting diodeInfo
- Publication number
- JPH04163973A JPH04163973A JP2290055A JP29005590A JPH04163973A JP H04163973 A JPH04163973 A JP H04163973A JP 2290055 A JP2290055 A JP 2290055A JP 29005590 A JP29005590 A JP 29005590A JP H04163973 A JPH04163973 A JP H04163973A
- Authority
- JP
- Japan
- Prior art keywords
- light emitting
- emitting diode
- layer
- carrier concentration
- diode chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910002601 GaN Inorganic materials 0.000 claims abstract description 14
- 239000004065 semiconductor Substances 0.000 claims abstract description 7
- -1 gallium nitride compound Chemical class 0.000 claims abstract description 4
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 4
- 150000001875 compounds Chemical class 0.000 claims description 3
- 239000003086 colorant Substances 0.000 abstract description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 2
- 230000001105 regulatory effect Effects 0.000 abstract 2
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 229910052594 sapphire Inorganic materials 0.000 description 8
- 239000010980 sapphire Substances 0.000 description 8
- 239000000758 substrate Substances 0.000 description 8
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- HQWPLXHWEZZGKY-UHFFFAOYSA-N diethylzinc Chemical compound CC[Zn]CC HQWPLXHWEZZGKY-UHFFFAOYSA-N 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 238000001947 vapour-phase growth Methods 0.000 description 2
- 241000218202 Coptis Species 0.000 description 1
- 235000002991 Coptis groenlandica Nutrition 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- BAPZCSMFCUVUHW-UHFFFAOYSA-N dichloro(fluoro)methane Chemical compound F[C](Cl)Cl BAPZCSMFCUVUHW-UHFFFAOYSA-N 0.000 description 1
- 238000000295 emission spectrum Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000004020 luminiscence type Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 150000002902 organometallic compounds Chemical class 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000004382 potting Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 1
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
- H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Led Device Packages (AREA)
- Led Devices (AREA)
Abstract
Description
本発明は、発光色を可変できる発光ダイオードに関する
。The present invention relates to a light emitting diode that can change the color of its emitted light.
従来、発光ダイオード（以下ｒＬＥＤＪという）は一対
のリードフレームの一方に発光ダイオードチップをボン
ディングし、上部電極ともう一方のリードフレームとを
Ａｕなどのワイヤで接続後、樹脂成形したものが知られ
ている。Conventionally, light-emitting diodes (hereinafter referred to as rLEDJs) have been known to be made by bonding a light-emitting diode chip to one of a pair of lead frames, connecting the upper electrode to the other lead frame with a wire such as Au, and then molding the chip with resin. There is.
しかし、従来は、高輝度の青色の発光ダイオードが得ら
れないことから、青色を１つの原色として変化させる可
変色発光ダイオードは知られていない。
本発明は、青色を原色に含む可変色発光グイオ−ドを提
供することを目的とする。
本発明は、本発明者らにより、窒化ガリウム系化合物半
導体から成るｉ層とｎ層の接合型の発光ダイオードチッ
プにおいて、ｎ層を低キャリア濃度ｎ層と高キャリア濃
度ｎ“層との二重層構造としたことで、（従来は、ｉ層
（半絶縁層）と単層のｎ層との接合であった。）青色の
発光光度を著しく向上させることができた。この高輝度
化により、その青色を１つの原色として他の発光と混合
させて、高範囲の可変色制御が可能となった。However, since a high-intensity blue light-emitting diode cannot be obtained conventionally, a variable color light-emitting diode that changes blue as one primary color is not known. An object of the present invention is to provide a variable color light emitting diode containing blue as a primary color. The present invention has been developed by the present inventors to provide an i-layer and n-layer junction type light emitting diode chip made of a gallium nitride-based compound semiconductor, in which the n-layer is a double layer consisting of a low carrier concentration n-layer and a high carrier concentration n'' layer. By adopting this structure, we were able to significantly improve the luminous intensity of blue light (conventionally, it was a junction between an I layer (semi-insulating layer) and a single N layer).With this increase in brightness, By using the blue color as a primary color and mixing it with other emitted light, a wide range of variable color control is now possible.
上記課題を解決するための発明の構成は、窒化ガリウム
系化合物半導体（ＡｌＸＧａｌ−、Ｎ；Ｘ＝Ｏを含む）
からなり、ｊ型のｉ層と、ｉ層に接合する低キャリア濃
度ｎ層と、低キャリア濃度ｎ層に接合する高キャリア濃
度ｎ“層とを有し、高キャリア濃度ｎ１層及びｉ層の電
極が同一面上に形成された第１の発光ダイオードチップ
と、第１の発光ダイオードチップと異なる発光色を有す
る第２の発光ダイオードチップと、第１の発光ダイオー
ドチップの両電極が接合される離間して形成された第１
及び第２のランドを有し、その一方のランドは第２の発
光ダイオードチップの１つの電極が接合されており、そ
のランドと離間して形成され、第２の発光ダイオードチ
ップの他の電極がリード接続される第３のランドを有す
るリードフレームとを設けたことである。The structure of the invention for solving the above problems is a gallium nitride-based compound semiconductor (AlXGal-, N; including X=O)
It has a j-type i layer, a low carrier concentration n layer that is connected to the i layer, and a high carrier concentration n'' layer that is connected to the low carrier concentration n layer, and has a high carrier concentration n1 layer and an i layer. A first light emitting diode chip having electrodes formed on the same surface, a second light emitting diode chip having a different emission color from the first light emitting diode chip, and both electrodes of the first light emitting diode chip are joined. The first spaced apart
and a second land, one of the lands is connected to one electrode of the second light emitting diode chip, is formed apart from the land, and the other electrode of the second light emitting diode chip is connected to the land. A lead frame having a third land to which the lead is connected is provided.
窒化ガリウム系化合物半導体で形成されたｊ層、低キャ
リア濃度ｎ層、高キャリア濃度ｎ４層とから成る第１の
発光ダイオードチップは発光輝度の高い青色を発光する
。
即ち、高キャリア濃度ｎ“層によりｎ層全体の電気抵抗
を小さくでき、発光ダイオードチップの直列抵抗が下が
り、発光ダイオードチップの発熱を抑えることができる
。又、ｉ層に接合するｎ層は低キャリア濃度とすること
、つまり ＧａＮを高純度化して発光領域（ｊ層及びそ
の近傍）の青色発光を抑制する欠陥や不純物原子濃度を
抑えることができる。以上の作用により青色の発光強度
が向上した。
又、第２の発光ダイオードチップは、青色以外の色を発
光する。又、リードフレームは３つのランドを有しおり
、第１及び第２のランドに対して第１の発光ダイオード
チップの電極がダイボンディングされる。又、第１又は
第２のランドに第２の発光ダイオードチップの第１の電
極がバンブ接合されてふり、第２の発光ダイオードチッ
プの第２の電極は９Ｊ３０ランドとリード接続されてい
る。
このような構成により、発光色の異なる２つの発光ダイ
オードチップを集積することができ、両売光ダイオード
チップの電極間の印加電圧を調整することで、発光色を
可変することができる。特に、第１の発光ダイオードチ
ップにおいて、ｎ層を高キャリア濃度ｎ１層と低キャリ
ア濃度ｎ層との二重層構造とすることにより、青色の発
光輝度を向上させることが出来たので、高輝度の可変色
ダイオードを作成することができた。
ｒ実施例】
以下、本発明を具体的な実施例に基づいて説明する。
まず、第１の発光ダイオードチップ１ｏの構成について
説明する。
第１図において、発光ダイオードチップ１ｏは、サファ
イア基板１を有しており、そのサファイア基板１に５０
０人のＡＩＮのバッファ層２が形成されている。そのバ
ッファ層、２の上には、順に、膜厚的２．２μｍのＧａ
Ｎから成る高キャリア濃度ｎ＋層３と膜厚的１．５μｍ
のＧａＮから成る低キャリア濃度ｎ層４が形成されてお
り、更に、低キャリア濃度ｎ層４の上に膜厚的０．２μ
ｍのＧａＮから成る１層５が形成されている。そして、
１層５に接続するアルミニウムで形成された電極７と高
キャリア濃度ｎ４層３に達するアルミニウムで形成され
た電極８とが形成されている。
次に、この構造の発光ダイオードチップ１０の製造方法
について説明する。
上記発光ダイオードチップ１０は、有機金属化合物気相
成長法（以下ｒ１４ＱＶＰＢ Ｊと記す）による気相成
長により製造された。
用いられたガスは、ＮＨ，とキャリアガスＨ３とトリメ
チルガリウム（Ｇａ （Ｃｌｌ ｓ） −） （以下ｒ
ＴＭＧ Ｊと記す）とトリメチルアルミニウム（ＡＩ
（Ｃ１，） ｓ） （以下ｒＴＭＡＪと記す）とシラン
（ＳｉＨ，）とジエチル亜鉛（以下「口ＥＺ Ｊと記す
）である。
まず、有機洗浄及び熱処理により洗浄したａ面を主面と
する単結晶のサファイア基板１をＭＯＶＰＥ装置の反応
室に載置されたサセプタに装着する。
次に、常圧でＨ３を流速２１７分で反応室に流しながら
温度１１００℃でサファイア基板１を気相エツチングし
た。
次に、温度を４００℃まで低下させて、Ｈ３を２１／分
、ＮＨ，を１０１／分、ＴＭＡをＨ３でバブリングして
１．８８１０−５モル／分で供給してＡｊ２Ｎのバッフ
ァ層２が約５００人の厚さに形成された。
次に、サファイア基板ｌの温度を１１５０℃に保持し、
Ｈ２を２０１１／分、ＮＨ，を１０１／分、ＴＭＧをＨ
２でバブリングして １．７Ｘ １０−’モル／分、Ｈ
２で０．８６ＰＰｍまで希釈したシラン（Ｓｉｎ、）を
２００ｍｊ’ ／分の割合で３０分間供給し、膜厚的２
．２μｍ１キャリア濃度１、５Ｘ １０”／ ｃｏ！の
ＧａＮから成る高キャリア濃度ｎ１層３を形成した。
続いて、サファイア基板１の温度を１１５０℃に保持し
、Ｈ２を２０１／分、ＮＨ，を１０１／分、ＴＭＧ Ｇ
Ｈ。
でバブリングして１．７Ｘ１０−’モル／分の割合で２
０分間供給し、膜厚的１．５μｍ１キャリア濃度ｌＸ１
０”／ Ｃｌ１ｌのＧａＮから成る・低キャリア濃度ｎ
層４を形成した。
次に、サファイア基板１を９００℃にして、Ｈ３を２０
１／分、ＮＨ，を１０１／分、ＴＭＧをＨ２でバブリン
グして１．７Ｘ１０−’モル／分、ＤＥＺをＨ３でバブ
リングして １．５ Ｘｌ０−’モル／分の割合で２分
間供給して、膜厚０．０４μｍのＧａＮから成る１層５
を形成した。
このようにして、第２図に示すような多層構造が得られ
た。
次に、第３図に示すように、１層５の上に、スパッタリ
ングによりＳｉ０２層１１を２０００人の厚さに形成し
た。次に、そのＳｉｎ２層１１上にフォトレジスト１２
を塗布して、フォトリソグラフにより、そのフォトレジ
スト１２を高キャリア濃度ｎ′″層３に対する電極形成
部位のフォトレジストを除去したパターンに形成した。
次に、第４図に示すように、フォトレジスト１２によっ
て覆われていない５１０２層１１をフッ酸系エツチング
液で除去した。
次に、第５図に示すように、フォトレジスト１２及び５
層０２層１１によって覆われていない部位の１層５とそ
の下の低キャリア濃度ｎ層４と高キャリア濃度ｎ＋層３
の上面一部を、真空度０．０４Ｔｏｒｒ、高周波電力０
．４４Ｗ／ｃｄ、 ＣＣｌ２Ｆ！ガスを１０ｍ１／分の
割合で供給しドライエツチングした後引続き、Ａｒでド
ライエツチングした。
次に、第６図に示すように、１層５上に残っているＳｉ
ｎ、層１１をフッ酸で除去した。
次に、第７図に示すように、試料の上全面に、ＡＩ層１
３を蒸着により形成した。そして、そのＡ１層１３の上
にフォトレジスト１４を塗布して、フォトリソグラフに
より、そのフォトレジスト１４が高キャリア濃度ｎ３層
３及び１層５に対する電極部が残るように、所定形状に
パターン形成した。
次に、第７図に示すようにそのフォトレジスト１４をマ
スクとして下層のＡＩ層１３の露出部を硝酸系エツチン
グ液でエツチングし、フォトレジスト１４をアセトンで
除去し、高キャリア濃度ｎ◆層３の電極８．１層５の電
極７を形成した。
このようにして、第１図に示すＭＩＳ （Ｍｅｔａｌ−
１ｎｓ−ｕｌａｔｏｒ Ｓｅｍ１ｃｏｎｄｕｃｔｏｒ）
構造の窒化ガリウム系発光素子を製造することができる
。
このようにして製造された発光ダイオードチップ１００
発光強度を測定したところ、０．２＋ａｃｄであった。
これは、単純にｉ層とキャリア濃度５Ｘ１０１７／ ｃ
ｆｆｌ、厚さ４μｍのｎ層とを接続した従来の発光ダイ
オードに比べて、発光強度が４倍に向上した。
又、発光面を観察した所、発光点の数が増加しているこ
とも観察された。
尚、比較のために、低キャリア濃度ｎ層４のキャリア濃
度を各種変化させた上記試料を製造して、発光強度及び
発光スペクトラムを測定した。その結果を、第８図に示
す。
キャリア濃度が増加するに連れて、発光強度が減少し、
且つ、発光波長が赤色側に変位することが分かる。この
ことは、ドーピング元素のシリコンが１層５に不純物元
素として拡散または混入するためであるき思われる。
次に、可変色発光ダイオード３０について説明する。
第１０図、第１１図において、リードフレーム２０は間
隔を隔てて並列に配設された正負一対の第１及び第２の
リード部材４１．３１、第３のリード部材３５により構
成されている。
第１及び第２のリード部材４１．３１にはそれらの先端
部４２．３２に第１及び第２のランドを構成する平坦部
４３．３３が形成されており、その平坦部４３．３３に
続いて外側に傾斜した反射部４４．３４が一体的に形成
されている。又、第３のリード部材３５の端面３５１は
第３のランドを構成している。
このようなリード部材４１．３１の平坦部（第１及び第
２のランド）４３．３３に、前述した第１の発光ダイオ
ードチップ１０が架橋され、そのチップ１０の電極７，
８が、それぞれ、平坦部４３．３３に対して導電性ペー
ストでバンプ接合されている。
又、第２の発光ダイオードチップ３６は、第１２図に示
すように、Ｐ−ＡＩＧａＡｓ層３６１とｎ−Ａｊｉ！Ｇ
ａＡｓ層・３６２とを有し、ｐ−Ａｊｌ！ＧａＡｓ層３
６１とｎ−ＡｊｉＧａＡｓ層３６２の上層上６２れぞれ
、金糸の電極３６３゜３６４が形成されている。
第２の発光ダイオードチップ３６は、一方の面側にある
電極３６３は第２のリード部材３１の平坦部（第２のラ
ンド）３３に載置され、導電性銀ペーストによって接合
されている。又、他方の面側にある電極３６４は第３の
リード部材３５の端面（第３のランド）３５１と金線３
７によりワイヤボンディングされている。
次に、第１の発光ダイオードチップ１０と第２の発光ダ
イオードチップ３６とが接合されたＩＪ −ドフレーム
２０には、第９図に示すように、エポキシ樹脂等の透明
樹脂がポツティングされる。このポツティングによりレ
ンズ部材３９が成形される。
このような配設状態において、第１のリード部材４１、
第２のリード部材３１、第３のリード部材３５の順に、
低くなる電位を印加することで、第１の発光ダイオード
チップ１０と第２の発光ダイオードチップ３６は共に順
方向のバイアスが印加され、共に発光する。このとき可
変色発光ダイオード３０は、全体として、赤紫色で発光
する。
又、第１のリード部材４１と第２のリード部材３１０間
にのみ、正電圧を印加すると、＄１の発光ダイオードチ
ップ１０のみが発光し、この可変色発光ダイオード３０
は青色で発光する。又、第２のリード部材３１と第３の
リード部材３５間にのみ、正電圧を印加すると、ＷＪ２
の発光ダイオードチップ３６のみが発光し、この可変色
発光ダイオード３０は赤色で発光する。
又、各リード部材に印加する電圧の大きさを変化させる
ことで青、赤の間の混合色の発光が可能となる。
以上述べたように、ｎ層を二重層構造とすることで、青
色発光の輝度を向上させることができたので、初めて、
赤色との混合が可能となり、高範囲の発光色の制御が可
能となった。
以上の実施例では、第２の発光ダイオードチップの発光
色は赤色とした・が、ＧａＰ等の緑色発光の発光ダイオ
ードチップを用いても良い。
又、上記の構造とすることで、２つの発光ダイオードチ
ップ１０．３６の表面から出た光に加えて、それら２つ
のチップの端面から出た光も第１のリード部材４１．第
２のリード部材３１に設けられた反射部４４．３４によ
り前方に反射されるので、発光効率を向上させることが
できる。The first light emitting diode chip, which includes a J layer made of a gallium nitride compound semiconductor, a low carrier concentration n layer, and a high carrier concentration n4 layer, emits blue light with high luminance. In other words, the electrical resistance of the entire n-layer can be reduced by the high carrier concentration n'' layer, which reduces the series resistance of the light-emitting diode chip and suppresses the heat generation of the light-emitting diode chip. By increasing the carrier concentration, that is, by highly purifying GaN, it is possible to suppress the concentration of defects and impurity atoms that suppress blue light emission in the light emitting region (J layer and its vicinity).The above effects improve the blue light emission intensity. Further, the second light emitting diode chip emits light in a color other than blue.The lead frame has three lands, and the electrodes of the first light emitting diode chip are connected to the first and second lands. The first electrode of the second light emitting diode chip is bump-bonded to the first or second land, and the second electrode of the second light emitting diode chip is connected to the 9J30 land by a lead. With this configuration, two light emitting diode chips that emit light of different colors can be integrated, and the color of the emitted light can be varied by adjusting the voltage applied between the electrodes of both light emitting diode chips. In particular, in the first light emitting diode chip, by making the n-layer a double layer structure consisting of a high carrier concentration n1 layer and a low carrier concentration n layer, we were able to improve the blue luminance. A variable brightness color diode was able to be produced. r Examples The present invention will be described below based on specific examples. First, the configuration of the first light emitting diode chip 1o will be described. In the figure, a light emitting diode chip 1o has a sapphire substrate 1, and the sapphire substrate 1 has a
A buffer layer 2 of 0 AINs is formed. On the buffer layer 2, a Ga film having a thickness of 2.2 μm is sequentially formed.
High carrier concentration n+ layer 3 made of N and a film thickness of 1.5 μm
A low carrier concentration n layer 4 made of GaN is formed, and a film thickness of 0.2 μm is further formed on the low carrier concentration n layer 4.
One layer 5 made of m GaN is formed. and,
An electrode 7 made of aluminum that connects to the first layer 5 and an electrode 8 made of aluminum that reaches the high carrier concentration n4 layer 3 are formed. Next, a method for manufacturing the light emitting diode chip 10 having this structure will be described. The light emitting diode chip 10 was manufactured by vapor phase growth using an organometallic compound vapor phase growth method (hereinafter referred to as r14QVPB J). The gases used were NH, carrier gas H3, and trimethyl gallium (Ga (Cll s) -) (hereinafter r
TMG J) and trimethylaluminum (AI
(C1,) s) (hereinafter referred to as rTMAJ), silane (SiH, ), and diethylzinc (hereinafter referred to as ``EZJ''). The crystalline sapphire substrate 1 was mounted on a susceptor placed in the reaction chamber of the MOVPE apparatus.Next, the sapphire substrate 1 was vapor-phase etched at a temperature of 1100° C. while flowing H3 into the reaction chamber at a flow rate of 217 minutes at normal pressure. Next, the temperature was lowered to 400°C, and H3 was bubbled at 21/min, NH, at 101/min, and TMA was bubbled with H3 and supplied at a rate of 1.8810-5 mol/min to form the Aj2N buffer layer 2. was formed to a thickness of approximately 500 mm.Next, the temperature of the sapphire substrate l was maintained at 1150 °C,
H2 at 2011/min, NH at 101/min, TMG at H
Bubble with 2 1.7X 10-'mol/min, H
Silane (Sin, ) diluted to 0.86 PPm with
．． A high carrier concentration n1 layer 3 made of GaN with a carrier concentration of 2 μm1 and 5×10”/co! was formed. Subsequently, the temperature of the sapphire substrate 1 was maintained at 1150° C., H2 was heated at 201/min, and NH was heated at 101/min. /min, TMG G
H. 2 at a rate of 1.7 x 10-' mol/min.
Supply for 0 minutes, film thickness 1.5 μm 1 carrier concentration 1
Made of GaN with 0”/Cl1l/Low carrier concentration n
Layer 4 was formed. Next, the sapphire substrate 1 is heated to 900°C, and H3 is heated to 20°C.
1/min, NH, was supplied at a rate of 101/min, TMG was bubbled with H2 at a rate of 1.7X10-' mol/min, DEZ was bubbled with H3 and supplied at a rate of 1.5 Xl0-' mol/min for 2 minutes. One layer 5 made of GaN with a thickness of 0.04 μm
was formed. In this way, a multilayer structure as shown in FIG. 2 was obtained. Next, as shown in FIG. 3, a Si02 layer 11 was formed on the layer 5 by sputtering to a thickness of 2000 nm. Next, a photoresist 12 is placed on the Sin2 layer 11.
was applied, and the photoresist 12 was formed by photolithography into a pattern in which the photoresist at the electrode formation site for the high carrier concentration n'' layer 3 was removed.Next, as shown in FIG. The 5102 layer 11 not covered by the photoresists 12 and 12 was removed using a hydrofluoric acid etching solution.Next, as shown in FIG.
Layer 02 1 layer 5 in the area not covered by layer 11, the lower carrier concentration n layer 4 and the high carrier concentration n+ layer 3
A part of the upper surface of the
．． 44W/cd, CCl2F! After dry etching by supplying gas at a rate of 10 ml/min, dry etching was performed with Ar. Next, as shown in FIG.
n, layer 11 was removed with hydrofluoric acid. Next, as shown in FIG. 7, an AI layer 1 is placed on the entire upper surface of the sample.
3 was formed by vapor deposition. Then, a photoresist 14 was coated on the A1 layer 13, and the photoresist 14 was patterned into a predetermined shape by photolithography so that electrode portions for the high carrier concentration n3 layer 3 and 1 layer 5 remained. . Next, as shown in FIG. 7, using the photoresist 14 as a mask, the exposed portion of the lower AI layer 13 is etched with a nitric acid-based etching solution, and the photoresist 14 is removed with acetone. Electrode 8.1 Electrode 7 of layer 5 was formed. In this way, MIS (Metal-
1ns-ulator Sem1conductor)
A gallium nitride-based light emitting device having this structure can be manufactured. Light emitting diode chip 100 manufactured in this way
When the luminescence intensity was measured, it was 0.2+acd. This is simply the i layer and carrier concentration 5X1017/c
Compared to a conventional light-emitting diode in which ffl and an n-layer with a thickness of 4 μm are connected, the light emission intensity has been improved four times. Furthermore, when the light emitting surface was observed, it was also observed that the number of light emitting points was increasing. For comparison, the above samples were manufactured in which the carrier concentration of the low carrier concentration n-layer 4 was varied, and the emission intensity and emission spectrum were measured. The results are shown in FIG. As the carrier concentration increases, the emission intensity decreases,
Moreover, it can be seen that the emission wavelength shifts to the red side. This seems to be because silicon, which is a doping element, diffuses or mixes into the first layer 5 as an impurity element. Next, the variable color light emitting diode 30 will be explained. In FIGS. 10 and 11, the lead frame 20 is composed of a pair of positive and negative lead members 41, 31 and a third lead member 35, which are arranged in parallel at intervals. The first and second lead members 41.31 have flat portions 43.33 forming first and second lands formed at their tip portions 42.32, and following the flat portions 43.33, A reflecting portion 44.34 is integrally formed and is inclined outwardly. Further, the end surface 351 of the third lead member 35 constitutes a third land. The above-described first light emitting diode chip 10 is bridged on the flat portions (first and second lands) 43.33 of the lead member 41.31, and the electrodes 7,
8 are respectively bump-bonded to the flat portions 43 and 33 with conductive paste. Further, as shown in FIG. 12, the second light emitting diode chip 36 has a P-AIGaAs layer 361 and an n-Aji! G
aAs layer 362, and p-Ajl! GaAs layer 3
Gold thread electrodes 363 and 364 are formed on the upper layer 61 and the n-AjiGaAs layer 362, respectively. In the second light emitting diode chip 36, the electrode 363 on one side is placed on the flat part (second land) 33 of the second lead member 31 and bonded with conductive silver paste. Further, the electrode 364 on the other side is connected to the end surface (third land) 351 of the third lead member 35 and the gold wire 3.
7 for wire bonding. Next, as shown in FIG. 9, a transparent resin such as epoxy resin is potted onto the IJ-board frame 20 to which the first light emitting diode chip 10 and the second light emitting diode chip 36 are bonded. The lens member 39 is molded by this potting. In such an arrangement state, the first lead member 41,
In the order of the second lead member 31 and the third lead member 35,
By applying a lower potential, both the first light emitting diode chip 10 and the second light emitting diode chip 36 are forward biased and emit light. At this time, the variable color light emitting diode 30 emits reddish-purple light as a whole. Further, when a positive voltage is applied only between the first lead member 41 and the second lead member 310, only the $1 light emitting diode chip 10 emits light, and this variable color light emitting diode 30
emits blue light. Furthermore, when a positive voltage is applied only between the second lead member 31 and the third lead member 35, WJ2
Only the light emitting diode chip 36 emits light, and this variable color light emitting diode 30 emits red light. Furthermore, by changing the magnitude of the voltage applied to each lead member, it is possible to emit light in a mixed color between blue and red. As mentioned above, by making the n-layer a double layer structure, we were able to improve the brightness of blue light emission, and for the first time,
It is now possible to mix with red, making it possible to control a wide range of emitted light colors. In the above embodiment, the second light emitting diode chip emits red light, but a green light emitting diode chip such as GaP may also be used. Furthermore, with the above structure, in addition to the light emitted from the surfaces of the two light emitting diode chips 10.36, the light emitted from the end faces of those two chips is also transmitted to the first lead member 41. Since the light is reflected forward by the reflecting portion 44.34 provided on the second lead member 31, the light emitting efficiency can be improved.
第１図は本発明の具体的な一実施例に係る可変色発光ダ
イオードの１つの構成要素の第１の発光ダイオードチッ
プの構成を示した構成図、第２図乃至第７図はその発光
ダイオードチップの製造工程を示した断面図、第８図は
低キャリア濃度ｎ層のキャリア濃度と発光強度及び発光
波長との関係を示した測定図、第９図は同実施例の可変
色発光ダイオードの全体の構成を示した縦断面図、第１
０図は同可変色発光ダイオードのリードフレームを示し
た縦断面図。第１１図は第１０図におけるリードフレー
ムを発光ダイオードチップ側から見た平面図。第１２図
は第２の発光ダイオードチップの構成を示した構成図で
ある。
１０ 第１の発光ダイオードチップ
１ ゛サファイア基板 ２ バッファ層 ３ 高キャリ
ア濃度ｎ４層 ４−低キャリア濃度ｎ層５１層 ７，８
・・電極
４１”−第一１のリード部材 ３１°第２のリード部材
３５゛第３のリード部材 ４３．３３．３５１−平坦
部（第１．第２．第３のランド）４４゜３４ 反射部
３６ 第２の発光ダイオードチップ
３９ レンズ部材
２０ リードフレーム
第１ 図
第８図
キャリア濃度（ｃ、、ｉ”３）
第９図
第１１図
二FIG. 1 is a block diagram showing the configuration of a first light emitting diode chip, which is one component of a variable color light emitting diode according to a specific embodiment of the present invention, and FIGS. 2 to 7 are diagrams showing the structure of the light emitting diode. FIG. 8 is a cross-sectional view showing the manufacturing process of the chip. FIG. 8 is a measurement diagram showing the relationship between the carrier concentration of the low carrier concentration n-layer, the emission intensity, and the emission wavelength. FIG. Longitudinal cross-sectional view showing the overall configuration, 1st
Figure 0 is a vertical sectional view showing the lead frame of the variable color light emitting diode. FIG. 11 is a plan view of the lead frame in FIG. 10, viewed from the light emitting diode chip side. FIG. 12 is a configuration diagram showing the configuration of the second light emitting diode chip. 10 First light emitting diode chip 1 Sapphire substrate 2 Buffer layer 3 High carrier concentration n4 layer 4-Low carrier concentration n layer 51 layer 7,8
...Electrode 41'' - First lead member 31° Second lead member 35° Third lead member 43.33.351 - Flat part (first, second, third land) 44° 34 Reflection Part 36 Second light emitting diode chip 39 Lens member 20 Lead frame 1 Figure 8 Carrier concentration (c,,i''3) Figure 9 Figure 11 Figure 2
Claims (1)
＿−＿ＸＮ；Ｘ＝０を含む）からなるｉ層と、前記ｉ層
に接合する低キャリア濃度ｎ型の窒化ガリウム系化合物
半導体（Ａｌ＿ＸＧａ＿１＿−＿ＸＮ；Ｘ＝０を含む）
からなる低キャリア濃度ｎ層と、前記低キャリア濃度ｎ
層に接合する高キャリア濃度ｎ＾＋型の窒化ガリウム系
化合物半導体（Ａｌ＿ＸＧａ＿１＿−＿ＸＮ；Ｘ＝０を
含む）からなる高キャリア濃度ｎ＾＋層とを有し、前記
高キャリア濃度ｎ＾＋層及び前記ｉ層の電極が同一面上
に形成された第１の発光ダイオードチップと、 前記第１の発光ダイオードチップと異なる発光色を有す
る第２の発光ダイオードチップと、前記第１の発光ダイ
オードチップの両電極が接合される離間して形成された
第１及び第２のランドを有し、その一方のランドは前記
第２の発光ダイオードチップの１つの電極が接合されて
おり、そのランドと離間して形成され、前記第２の発光
ダイオードチップの他の電極がリード接続される第３の
ランドを有するリードフレームとを有する可変色発光ダ
イオード。[Claims] I-type gallium nitride compound semiconductor (Al_XGa_1
_-_XN; including X=0); and a low carrier concentration n-type gallium nitride compound semiconductor (Al_XGa_1_-_XN; including X=0) bonded to the i-layer.
a low carrier concentration n layer consisting of the low carrier concentration n layer;
a high carrier concentration n^+ layer made of a high carrier concentration n^+ type gallium nitride-based compound semiconductor (Al_XGa_1_-_XN; including X=0) which is bonded to the high carrier concentration n^+ layer; and a first light emitting diode chip in which the electrodes of the i-layer are formed on the same surface; a second light emitting diode chip having a different emission color from the first light emitting diode chip; and the first light emitting diode chip. has first and second lands formed spaced apart to which both electrodes of the second light emitting diode chip are bonded; one land is bonded to one electrode of the second light emitting diode chip; and a lead frame having a third land to which the other electrode of the second light emitting diode chip is lead-connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2290055A JPH04163973A (en) | 1990-10-27 | 1990-10-27 | Variable color light emitting diode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2290055A JPH04163973A (en) | 1990-10-27 | 1990-10-27 | Variable color light emitting diode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04163973A true JPH04163973A (en) | 1992-06-09 |
Family
ID=17751205
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2290055A Pending JPH04163973A (en) | 1990-10-27 | 1990-10-27 | Variable color light emitting diode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04163973A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000275636A (en) * | 1999-03-25 | 2000-10-06 | Seiko Epson Corp | Light source and illumination device as well as liquid crystal device using the illumination device |
| US6357889B1 (en) | 1999-12-01 | 2002-03-19 | General Electric Company | Color tunable light source |
| JP2006339060A (en) * | 2005-06-03 | 2006-12-14 | Akita Denshi Systems:Kk | Lighting system |
| EP2267798A1 (en) * | 1997-07-29 | 2010-12-29 | OSRAM Opto Semiconductors GmbH | Optoelectronic device |
-
1990
- 1990-10-27 JP JP2290055A patent/JPH04163973A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2267798A1 (en) * | 1997-07-29 | 2010-12-29 | OSRAM Opto Semiconductors GmbH | Optoelectronic device |
| JP2000275636A (en) * | 1999-03-25 | 2000-10-06 | Seiko Epson Corp | Light source and illumination device as well as liquid crystal device using the illumination device |
| US6357889B1 (en) | 1999-12-01 | 2002-03-19 | General Electric Company | Color tunable light source |
| JP2006339060A (en) * | 2005-06-03 | 2006-12-14 | Akita Denshi Systems:Kk | Lighting system |
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