JPH04163938A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH04163938A
JPH04163938A JP2290395A JP29039590A JPH04163938A JP H04163938 A JPH04163938 A JP H04163938A JP 2290395 A JP2290395 A JP 2290395A JP 29039590 A JP29039590 A JP 29039590A JP H04163938 A JPH04163938 A JP H04163938A
Authority
JP
Japan
Prior art keywords
resistors
pull
design
interface circuit
resistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2290395A
Other languages
Japanese (ja)
Inventor
Yoshirou Iwasa
伊郎 岩佐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP2290395A priority Critical patent/JPH04163938A/en
Publication of JPH04163938A publication Critical patent/JPH04163938A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To increase the degree of freedom of design by setting the circuit resistance values of pull-up resistors, pull-down resistors, etc., at will by only an aluminum contact process. CONSTITUTION:Explanation is made about an interface circuit section as an example. An output interface circuit section 202 and an input interface circuit section 205 are provided. A resistor row 204 on the side of a Pch. region is provided, and a series arrangement is adopted for the array order of the resistors so as to be connectable with aluminum wiring, etc. In case of using pull-up resistors for a circuit, the resistance values needed by design are constituted by the resistor row 204. The series arrangement is adopted for the array order of the resistors of a resistor row 205 on the side of Nch. region so as to be connectable with the aluminum wiring, etc. In this way, the degree of freedom of design widens as pull-up or pull-down resistors can be changed by arranging connectable resistors and connecting individual resistors in compliance with demands, in a master prepared beforehand such as a semicustom IC, etc.

Description

【発明の詳細な説明】 ［産業上の利用分野］ 本発明は、半導体装置に関わり、特にマスタースライス
方式等によるセミカスタムＩＣなどの半導体装置に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device such as a semi-custom IC using a master slice method or the like.

［従来の技術］ 従来のセミカスタム半導体装置において、プルアップ抵
抗、プルダウン抵抗などを設計する場合には、あらかじ
めマスターと呼ばれる、ある工程までをあらかじめ準備
された半導体装置の基盤に、ソースを”＋”電位に固定
した抵抗、もしくはソースを”−”電位に固定した抵抗
などのドレイン部分をアルミ、またはコンタクト工程で
接続する事で構成していた。[Conventional technology] In conventional semi-custom semiconductor devices, when designing pull-up resistors, pull-down resistors, etc., the source is placed on the base of a semiconductor device called a master, which has been prepared up to a certain process in advance. It was constructed by connecting the drain part of a resistor whose source was fixed at a potential or a resistor whose source was fixed at a negative potential using aluminum or a contact process.

［発明が解決しようとする課題］ しかし、従来の方法では、マスター設計時に設定された
抵抗の値でしか設計が不可能で、セミカスタム半導体装
置であるにもがかわらず、設計の自由度が極めて低いも
のであった。[Problem to be solved by the invention] However, with the conventional method, it is possible to design only with the resistance value set at the time of master design, and even though it is a semi-custom semiconductor device, the degree of freedom in design is limited. It was extremely low.

そこで、本発明は、従来同様にセミカスタム半導体装置
においてのプルアップ、プルダウン抵抗値などを、アル
ミ、コンタクト工程だけで任意の抵抗値に設計が出来る
。Therefore, in the present invention, the pull-up and pull-down resistance values in a semi-custom semiconductor device can be designed to arbitrary resistance values just by the aluminum and contact process, as in the conventional semiconductor device.

そのため、自由度を要求される設計などに適する。Therefore, it is suitable for designs that require a degree of freedom.

［課題を解決するための手段］ 本発明の半導体装置は、外部とのインターフェースを行
うための入出力インターフェースセルをあらかじめマス
ターとしてもつ半導体装置などにおいて、プルアップ、
プルダウン抵抗などの回路をアルミ、コンタクト工程だ
けで、ある特定範囲内の抵抗値を任意に設定できる事を
特徴とする。[Means for Solving the Problems] The semiconductor device of the present invention is a semiconductor device having an input/output interface cell as a master in advance for interfacing with the outside.
It is characterized by the ability to arbitrarily set the resistance value within a certain range by simply using aluminum and contacting circuits such as pull-down resistors.

［実施例］ 以下に本発明の半導体装置の実施例を図面に基ずいて説
明する。[Example] Examples of the semiconductor device of the present invention will be described below based on the drawings.

第１図は、本発明の半導体装置のマスターと呼ばれる部
分の構成を示したものである。第１図はセミカスタムＩ
Ｃの代表的な存在であるゲートアレイを例にとった場合
のＩＣチップ全体図である。図中１０１はＩＣ外部とＩ
Ｃ内部の信号インターフェースを行うＩ１０セル領域で
ある。本発明の回路はこのＩ１０セル領域内で形成する
。図中１０２はＩＣとＩＣパッケージ間をボンディング
ワイヤー等で接続するＰＡＤと呼ばれる部分である。図
中１０３は、ＩＣ外部とＩＣ内部の信号インターフェー
スを行う為の入力インターフェース回路領域である。図
中１０４は、ＩＣ外部とＩＣ内部の信号インターフェー
スを行う為の出力インターフェース領域である。図中１
０５はＩＣの回路構成を行う為のトランジスタチャネル
領域である。第１図の１０１の中を第２図の模式図にお
いて説明する。FIG. 1 shows the configuration of a portion called a master of a semiconductor device of the present invention. Figure 1 is semi-custom I
1 is an overall diagram of an IC chip, taking as an example a gate array, which is a typical example of C. In the figure, 101 indicates the outside of the IC and I
This is an I10 cell area that performs a signal interface inside C. The circuit of the present invention is formed within this I10 cell region. In the figure, 102 is a part called a PAD that connects the IC and the IC package with a bonding wire or the like. In the figure, 103 is an input interface circuit area for performing a signal interface between the outside of the IC and the inside of the IC. In the figure, reference numeral 104 is an output interface area for performing a signal interface between the outside of the IC and the inside of the IC. 1 in the diagram
05 is a transistor channel region for configuring the circuit of the IC. The inside of 101 in FIG. 1 will be explained with reference to the schematic diagram in FIG. 2.

図中２０１はＩＣ外部とＩＣ内部の信号インターフェー
スを行うＩ１０セル領域である。In the figure, 201 is an I10 cell area that provides a signal interface between the outside of the IC and the inside of the IC.

図中２０２は出力インターフェース回路部である。図中
２０３は入力インターフェース回路部である。図中２０
４はＰｃｈ領域側の抵抗列である。抵抗の配列順はアル
ミ配線などで接続が可能なようにシリーズに配置してい
る。回路にプルアップ抵抗を取り入れる場合には要求さ
れる設計抵抗値をこの２０４で構成する。In the figure, 202 is an output interface circuit section. In the figure, 203 is an input interface circuit section. 20 in the diagram
4 is a resistor string on the Pch region side. The resistors are arranged in series so that they can be connected using aluminum wiring, etc. When a pull-up resistor is incorporated into the circuit, this 204 constitutes a required design resistance value.

図中２０５はＮｃｈ領域側の抵抗列である。In the figure, 205 is a resistor string on the Nch region side.

抵抗の配列順はアルミ配線などで接続が可能なようにシ
リーズに配置している。回路にプルアップ抵抗を取り入
れたい場合には要求される設計抵抗値をこの２０５で構
成する。図中２０６は第１図の１０２と同様でＰＡＤ部
である。The resistors are arranged in series so that they can be connected using aluminum wiring, etc. When it is desired to incorporate a pull-up resistor into the circuit, this 205 constitutes the required design resistance value. Reference numeral 206 in the figure is similar to 102 in FIG. 1, and is a PAD section.

第３図は本発明の半導体装置のブロック図である。図中
３０１はＮｃｈ側の抵抗で一方をＧＮＤレベルに落とし
ている。図中３０２はＮｃｈ側の抵抗で、要求される設
計抵抗値を３０２を複数個と、３０１を接続する事によ
って任意の抵抗値を設計する事が可能である。図中３０
３はＰｃｈ側の抵抗で一方をＶＤＤレベルに接続してい
る。図中３０４はＰｃｈ側の抵抗で、要求される設計抵
抗値を３０４を複数個と、３０３を接続する事によって
任意の抵抗値を設計する事が可能である。図中３０５は
アルミ配線で、３０１と３０２、または３０３と３０４
を接続する為のものである。FIG. 3 is a block diagram of the semiconductor device of the present invention. In the figure, 301 is a resistor on the Nch side, one of which is lowered to the GND level. In the figure, 302 is a resistor on the Nch side, and by connecting a plurality of 302 and 301, it is possible to design an arbitrary resistance value. 30 in the diagram
3 is a resistor on the Pch side, one end of which is connected to the VDD level. In the figure, 304 is a resistor on the Pch side, and by connecting a plurality of 304 and 303, it is possible to design an arbitrary resistance value. In the figure, 305 is aluminum wiring, 301 and 302, or 303 and 304
It is for connecting.

［発明の効果］ 本発明は以上述べたように、セミカスタムＩＣなど、あ
らかじめ準備されるマスターにおいて、接続可能な抵抗
を配列し、要求に応じて個々の抵抗を接続する事でプル
アップ抵抗やプルダウン抵抗の抵抗値を変更できる為、
設計の自由度がひろがる。[Effects of the Invention] As described above, the present invention can create pull-up resistors or Since the resistance value of the pull-down resistor can be changed,
Greater freedom in design.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明のマスターとして使用するセミカスタム
ＩＣの全体図である。 １０１・・・ＩＣチップエ１０セル領域１０２・・・Ｐ
ＡＤ部 １０３・・・入力インターフェース回路部１０４・・・
出力インターフェース回路部１０５・・・トランジスタ
チャネル領域第２図は本発明の抵抗を、セミカスタムＩ
Ｃの外部と内部の信号をコントロールする入出力インタ
ーフェース回路部に配置した図である。 ２０１・・・工１０セル部 ２０２・・・出力コントロール回路部 ２０３・・・入力コントロール回路部 ２０４・・・Ｐｃｈ側抵抗配列部 ２０５・・・Ｎｃｈ側抵抗抵抗配 列部６・・・ＰＡＤ部 第３図は本発明の抵抗部の接続例の図である。 ３０１・・・Ｎｃｈ側（ＧＮＤ）接続抵抗部３０２・・
、・Ｎｃｈ側抵抗抵 抗部３−　・・Ｐｃｈ側（ＶＤＤ）接続抵抗部３０４・
・・Ｐｃｈ側抵抗部 ３０５・・・接続用アルミ配線 以上 出願人　セイコーエプソン株式会社 代理人　弁理士　鈴木喜三部（化１名）第１図 第３図FIG. 1 is an overall diagram of a semi-custom IC used as a master of the present invention. 101...IC chip 10 cell area 102...P
AD section 103...input interface circuit section 104...
Output interface circuit section 105...transistor channel region FIG. 2 shows the resistor of the present invention in a semi-custom I
FIG. 2 is a diagram illustrating the arrangement of an input/output interface circuit section that controls external and internal signals of C. 201... Engineering 10 Cell section 202... Output control circuit section 203... Input control circuit section 204... Pch side resistance array section 205... Nch side resistance Resistor array section 6... PAD section No. FIG. 3 is a diagram illustrating a connection example of the resistor section of the present invention. 301... Nch side (GND) connection resistance section 302...
,・Nch side resistance resistance section 3- ・・Pch side (VDD) connection resistance section 304・
...Pch side resistance part 305...Aluminum wiring for connection and above Applicant: Seiko Epson Co., Ltd. Agent Patent attorney: Kizobe Suzuki (1 person) Figure 1 Figure 3

Claims (1)

【特許請求の範囲】[Claims] 　半導体装置で、外部とのインターフェースを行うため
の入出力インターフェースセルをあらかじめマスターと
してもつ半導体装置などにおいて、プルアップ、プルダ
ウン抵抗などの回路をアルミ、コンタクト工程だけで、
ある特定範囲内の抵抗値を任意に設定できることを特徴
とする半導体装置。In semiconductor devices that have an input/output interface cell as a master in advance for interfacing with the outside, circuits such as pull-up and pull-down resistors can be built using only aluminum and contact processes.
A semiconductor device characterized in that a resistance value within a certain range can be arbitrarily set.
JP2290395A 1990-10-26 1990-10-26 Semiconductor device Pending JPH04163938A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2290395A JPH04163938A (en) 1990-10-26 1990-10-26 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2290395A JPH04163938A (en) 1990-10-26 1990-10-26 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH04163938A true JPH04163938A (en) 1992-06-09

Family

ID=17755459

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2290395A Pending JPH04163938A (en) 1990-10-26 1990-10-26 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH04163938A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008153588A (en) * 2006-12-20 2008-07-03 Matsushita Electric Ind Co Ltd Electric fuse circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008153588A (en) * 2006-12-20 2008-07-03 Matsushita Electric Ind Co Ltd Electric fuse circuit

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