JPH04163906A - Capacitor block - Google Patents

Abstract

PURPOSE:To make the circuit design easy and improve compactness of the title block by placing the capacitor section which forms the capacitor block in a multi-layer substrate between GND electrodes which partly serve as capacitor electrodes. CONSTITUTION:The 1st capacitor electrode pattern 10 is formed on the 1st layer of a multilayer substrate, the 2nd capacitor electrode pattern 11 is formed on the 2nd layer, the 3rd capacitor electrode pattern 12 is formed on the 3rd layer, and the 4th capacitor electrode pattern is formed on the 4th layer and these layers are arranged opposite the layered direction of the multilayer substrate. Then, the 1st to the 4th capacitor patterns 10, 13 are connected by the blind through hole 14, these electrodes are connected to GND, and become GND electrodes. Between the electrode patterns 10 and 11, a Ca capacitor is formed, between the electrode patterns 11 and 12, a Cb capacitor is formed, and between the electrode patterns 12 and 13, a Cc capacitor is formed. Therefore, a capacitor block is created which is sandwiched by GND electrodes.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a capacitor block, and more specifically, the present invention relates to a capacitor block, and more specifically, it is used in a circuit including a plurality of capacitors electrically connected to each other, such as a filter or an impedance conversion circuit. In particular, the present invention relates to a capacitor block mounted on a multilayer substrate using a thick film pattern.

[Conventional technology]

Figures 10 to 12 are diagrams showing conventional examples;
The figure shows an example of a π-type circuit, FIG. 11 is an example of a T-type circuit, and FIG. 12 is a cross-sectional view of a capacitor block.

In the figure, IN is an input terminal, OUT is an output terminal, 01 to C3
are capacitors, 1-1 to 1-3 are each layer (dielectric layer) of the multilayer board, 2-1 to 2-3 are capacitor electrode patterns, 3
4-1 to 4-3.5-1.5-3 are blind through holes (through holes filled with conductors), and 4-1 to 4-3.5-1.5-3 are capacitor electrode patterns.

Conventionally, circuits as shown in FIGS. 10 and 11 have often been used, for example, in filter sections and impedance conversion sections in various electronic circuits.

Figure 10 shows capacitors C1, C! , C3 are connected in a π-type, and FIG. 11 shows the capacitors CI, C2,
This is a circuit in which C3 is connected in a T-shape.

When such a π-type circuit or T-type circuit is constructed using a multilayer substrate, it becomes a capacitor block as shown in FIG. 12. In this example, capacitor electrode patterns for capacitors C1, C2, and C3 are formed with thick films on the first layer 1-1, second layer l-2, and third layer 1-3 of the multilayer substrate, respectively. 2-1~2-3.4-1~4-3.5-1~5-
It is configured using 3. In addition, capacitor electrode patterns 2-1, 2-3.4-1 and 4-3.5, which are outer electrodes,
-1 and 5-3 are connected by a blind through hole 3 (a through hole whose inside is filled with a conductor).

In the implementation example shown in FIG. 12, when the π-type circuit shown in FIG. 10 is configured, capacitors Ci and C3 are grounded (capacitor electrode patterns 2-1 and 5-1 are grounded), but capacitor C! is not grounded.

Therefore, in FIG. 12, capacitor electrode patterns 2-1, 2-3 constituting capacitor C1 and capacitor C3
The capacitor electrode patterns 5-1 and 5-3 constituting the capacitor C! The capacitor electrode patterns 4-1 and 4-3 (outer electrodes) constituting the capacitor are not grounded.

Furthermore, when the T-type circuit of FIG. 11 is mounted as shown in FIG. 12, the capacitor electrode pattern 4-1.4-3 constituting the capacitor C2 is grounded, but the capacitor C1
Capacitor electrode pattern 2-1.2-3 constituting C3
．． 5-1. Do not ground 5-3.

[Problem to be solved by the invention]

The above-mentioned conventional devices had the following drawbacks.

(1) When the π-type circuit shown in Fig. 10 is configured as a capacitor block using a multilayer board as shown in Fig. 12, or when the T-type circuit shown in Fig. 11 is configured as a capacitor block using a multilayer board as shown in Fig. 12. If configured, the capacitor electrode pattern of the ungrounded capacitor will be exposed to the surface.

For this reason, it is susceptible to disturbances.

(2) In particular, when a capacitor is built into a multilayer substrate, the electrodes become larger in order to obtain the necessary capacitance compared to a chip capacitor due to the number of laminated layers.

+31 For example, when a filter element is made using the above capacitor block, there is an ungrounded capacitor electrode pattern on the surface of the element, so when installing it on the motherboard, it is necessary to avoid stray capacitance between it and other circuits. need to be considered.

The present invention aims to eliminate such conventional drawbacks and to facilitate circuit design and realize miniaturization by forming each capacitor of a capacitor block in a structure sandwiched between GND conductors. .

[Means to solve the problem]

In order to achieve the above object, the present invention is configured as follows.

(1) A capacitor block in which a plurality of capacitors are built into a multilayer substrate, in which the capacitor portion constituting the capacitor block is placed between GND electrodes that are partially shared with the capacitor electrodes.

(2) Add G to any layer (dielectric layer) that makes up the multilayer board.
A first capacitor ttf+ pattern which is an ND electrode is provided, a second capacitor electrode pattern is provided opposite to the first capacitor electrode pattern in the stacking direction with a dielectric layer interposed therebetween, and the second capacitor A third capacitor electrode pattern is provided opposite to the electrode pattern in the stacking direction with the dielectric layer interposed therebetween; A fourth capacitor electrode pattern, which is a GND electrode, is provided facing each other, and the first and fourth capacitor electrode patterns are connected to each other.
By connecting to the D electrode, a π-type circuit consisting of a plurality of capacitors sandwiched between the GND electrodes was formed in the multilayer substrate.

(3) Add G to any layer (dielectric layer) that makes up the multilayer board.
A first capacitor electrode pattern, which is an ND electrode, is provided, and a second capacitor electrode pattern, which is independent of each other and is opposed to the first capacitor electrode pattern in the stacking direction with a dielectric layer interposed therebetween, is provided.
and a third capacitor electrode pattern, and fourth and fifth capacitor electrode patterns, which are independent from each other, are provided opposite to the second and third capacitor electrode patterns in the stacking direction with a dielectric layer interposed therebetween. , Furthermore, for the fourth and fifth capacitor electrode patterns,
A sixth capacitor electrode pattern, which is a GND electrode, is provided so as to face each other in the stacking direction via a dielectric layer, and the first and sixth capacitor electrode patterns are connected to form a GN.
By connecting to D and connecting between the second and fifth capacitor electrode patterns and between the third and fourth capacitor electrode patterns, π due to the plurality of capacitors sandwiched between the GND electrodes is A pattern circuit was formed.

(4) Add G to any layer (dielectric layer) constituting the multilayer board.
A first capacitor electrode pattern which is an ND electrode is provided, a second capacitor electrode pattern is provided opposite to the first capacitor electrode pattern in the stacking direction with a dielectric layer interposed therebetween, and the second capacitor electrode pattern is provided as a ND electrode. Third and fourth capacitor electrode patterns, which are independent of each other, are provided opposite to each other in the stacking direction with a dielectric layer interposed between the capacitor electrode patterns, and the third and fourth capacitor electrode patterns are provided with dielectric A fifth capacitor electrode pattern is provided facing the stacking direction through the body layer, and a GND electrode is further provided facing the fifth capacitor electrode pattern through the dielectric layer in the stacking direction. A certain sixth capacitor electrode pattern is provided, and the first and sixth capacitor electrode patterns are connected to form a GN.
By connecting to D and connecting the second and fifth capacitor electrode patterns, a T-shaped circuit including a plurality of capacitors sandwiched between the GND electrodes was formed in the multilayer substrate.

[Effect]

Since the present invention is configured as described above, it has the following effects.

(1) With the configuration as described in (1) above, the capacitor section consisting of a plurality of capacitors is sandwiched between the GND electrodes.

Therefore, when this capacitor block is mounted on the motherboard and used, it is not affected by external disturbances.
Furthermore, there is no need to consider stray capacitance.

(2) In the configuration (2) above, when the terminals are taken out from the second and third capacitor electrode patterns, there is a gap between one terminal and GND between the first and second capacitor electrode patterns. The capacitor is connected and the other terminal and GN
A capacitor between the third and fourth capacitor electrode patterns is connected between D, and a capacitor between the second and third capacitor electrode patterns is connected between both terminals. A capacitor circuit is formed.

Since these capacitors are sandwiched between the first and fourth capacitor electrode patterns, which are GND electrodes, they are not affected by external disturbances, and there is no need to consider stray capacitance.

(3) In the configuration (3) above, when the terminals are taken out from the second and third capacitor electrode patterns or the fourth and fifth capacitor electrode patterns, the negative terminal and G
A composite capacitor consisting of a capacitor between the first and second capacitor electrode patterns and a capacitor between the fifth and sixth capacitor electrode patterns is connected between ND, and between the other terminal and ground, the first, A composite capacitor of a capacitor between the third capacitor electrode pattern and a capacitor between the fourth and sixth capacitor electrode patterns is connected.

In addition, a composite capacitor consisting of a capacitor between the second and fourth capacitor electrode patterns and a capacitor between the third and fifth capacitor electrode patterns is connected between both terminals, forming a π-shaped capacitor circuit as a whole. be done.

Since these capacitors are sandwiched between the first and sixth capacitor electrode patterns, which are GND electrodes, they are not affected by disturbances and there is no need to take stray capacitance into consideration.

(4) In the configuration (4) above, when the terminals are taken out from the third and fourth capacitor electrode patterns, the capacitors between the second and third capacitor electrode patterns and the third , a series circuit is formed of a composite capacitor of the capacitor between the fifth capacitor electrode pattern, a composite capacitor of the capacitor between the second and fourth capacitor electrode patterns, and a composite capacitor of the capacitor between the fourth and fifth capacitor electrode patterns. Ru.

Further, between the connection point of the two composite capacitors and GND, a composite capacitor of a capacitor between the first and second capacitor electrode patterns and a capacitor between the fifth and sixth capacitor electrode patterns is connected, and as a whole, A T-shaped capacitor circuit is formed.

These capacitors are also sandwiched between the first and sixth capacitor electrode patterns, which are GND electrodes, and are not affected by external disturbances, and there is no need to take stray capacitance into consideration.

〔Example〕

Embodiments of the present invention will be described below based on the drawings.

1 to 6 are diagrams showing embodiments of the present invention. FIG. 1 is an explanatory diagram of mounting a capacitor block in the first embodiment (π-type circuit), and FIG. 2 is a diagram showing the implementation of the capacitor block in the first embodiment. Fig. 3 is an explanatory diagram of the implementation of the capacitor block in the second embodiment (π-type circuit), and Fig. 4 is an explanatory diagram of the π-type circuit of the second embodiment.
FIG. 5 is an explanatory diagram of the mounting of the capacitor block in the third embodiment (T-type circuit), and FIG. 6 is an explanatory diagram of the T-type circuit of the third embodiment.

In the figure, 10.15.19 is the first capacitor electrode pattern, 11.16-1.20 is the second capacitor electrode pattern, 12.16-2.21-1 is the third capacitor electrode pattern, 13. 17-1.21-2 is the fourth capacitor electrode pattern, 17-2.22 is the fifth capacitor electrode pattern, 18.23 is the sixth capacitor electrode pattern, 14 is the blind through hole, Ca1, Ca2
, Ca, Cbl, Cb2, Cb, Ccl, Ccx, CC
indicates a capacitor, and A and B indicate terminals.

(1) First Embodiment -----<Refer to FIGS. 1 and 2) This embodiment is an example of a capacitor block in which a π-type circuit is mounted on a multilayer substrate.

As shown in Fig. 2, the π-type circuit is one in which capacitors Ca, Cb, and Cc are connected in a π-type, and the
Both are mounted on a multilayer board with four or more layers to form a capacitor block as shown in FIG. However, in FIG. 1, each layer (dielectric layer) of the multilayer substrate is not shown.

First, when forming the electrodes of capacitors Ca, Cb, and Cc on a multilayer substrate, the terminal A side electrodes of capacitors Ca and Cc are made a common electrode (one electrode), and capacitor cb
and Cc's output terminal B side electrode as a common electrode (one electrode)
shall be. In this way, a π-type circuit consisting of three capacitors can be constructed using the four capacitor electrodes.

In this case, capacitor Ca and cbOGND side (ground side)
If the electrodes are configured separately, and the remaining two capacitor electrodes are placed between these two ground-side capacitor electrodes, a capacitor block with GND electrodes sandwiched on both sides can be created.

Therefore, as shown in Figure 1, in the first layer of the multilayer board,
A first capacitor electrode pattern 10 is formed, a second capacitor electrode pattern 11 is formed on the second layer, and a third capacitor electrode pattern 10 is formed on the second layer.
forming a third capacitor electrode pattern 12 on the layer;
Fourth capacitor electrode patterns 13 are formed on the fourth layer and are arranged to face each other in the stacking direction of the multilayer substrate.

And the first and fourth capacitor electrode patterns 10.1
3 are connected by a blind through hole 14, and these electrodes are connected to GND to form a GND electrode.

Also, connect the terminal A to the capacitor electrode pattern 11,
Terminal B is connected to the capacitor electrode pattern 12.

In this way, since each layer (dielectric layer) of the multilayer substrate is interposed between each capacitor electrode pattern, the first capacitor electrode pattern 1
A capacitor Ca is formed between 0 and the second capacitor electrode pattern 11, and the third capacitor electrode pattern 1
A capacitor cb is formed between the second capacitor electrode pattern 11 and the fourth capacitor electrode pattern 13, and a capacitor Cc is formed between the second capacitor electrode pattern 11 and the third capacitor electrode pattern 12.

Therefore, the capacitor block having the structure shown in FIG. 1 becomes a π-type circuit shown in FIG. 2.

If the first and fourth capacitor electrode patterns 10.13 are used as CND electrodes as described above, both sides can be connected to GN.
It becomes a capacitor block with a structure sandwiched between D electrodes.

(2) Second embodiment - (See Figures 3 and 4) In this embodiment, a π-type circuit as shown in Figure 4 is mounted on a multilayer board as shown in Figure 3. This is an example of a capacitor link.

In this circuit, a capacitor Cc connected between terminals A and B
is composed of two capacitors, CCI and CC2, and the capacitor Ca connected between terminal A and ground is connected to Ca1 and Ca1.
It is composed of two capacitors t, and the capacitor connected between terminal B and ground is composed of two capacitors Cbl and cb2.

That is, each capacitor constituting the π-type circuit is considered to be a combination of two capacitors. When such a π-type circuit is mounted on a multilayer board, the configuration is as shown in FIG. 3. Note that in FIG. 3, each layer (dielectric layer) of the multilayer substrate is not illustrated.

As shown in FIG. 3, a first capacitor electrode pattern 15 is formed on the first layer of the multilayer substrate, and a second capacitor electrode pattern 15 is formed on the second layer.
A third capacitor electrode pattern 16-1.16-2 is formed, fourth and fifth computer electrode patterns 17-1.17-2 are formed on the third layer, and a sixth computer electrode pattern 17-1.17-2 is formed on the fourth layer. A capacitor electrode pattern 18 is formed.

In this case, the first and sixth capacitor electrode patterns 15.
18 are arranged to face each other in the stacking direction of the multilayer substrate, and these two capacitor electrode patterns are used as GND electrodes (ground electrodes).

Also, between the two capacitor electrode patterns 15.18, second and third capacitor electrode patterns 16-1, 16-2 are provided via dielectric layers (each layer of the multilayer board), respectively.
and fourth and fifth capacitor electrode patterns 17-1
．． Set 17-2.

Then, second and third capacitor electrode patterns 16-1
．． The total area of 16-2 and the total area of the fourth and fifth capacitor electrode patterns 17-1 and 17-2 are each larger than the area of the first or sixth capacitor electrode pattern, which is the outer GND electrode. G
The capacitor block has a structure sandwiched between ND electrodes.

The connections between the above capacitor electrode patterns include connecting the second capacitor electrode pattern 17-1 to terminal A, connecting the third capacitor electrode pattern 17-2 to terminal B, and connecting the second and fifth capacitor electrode patterns to terminal A. Capacitor electrode pattern 16-1,
18-2, third and fourth capacitor electrode patterns 16
-2.17-1 and between the first and sixth capacitor electrode patterns are connected by blind through holes 14, respectively.

In addition, the first and sixth capacitor electrode patterns 15.18
is used as a GND electrode, so either electrode is connected to GND.

The capacitors formed between each capacitor electrode pattern of the capacitor block configured as described above are set as shown in the figure.

That is, for each capacitor electrode pattern, 15 and 16
The capacitor between -1 is Cax, the capacitor between 15 and 16=2 is Cbx, the capacitor between 16-1 and 17-1 is Oct, the capacitor between 16-2 and 17-2 is CC2,
Cbs the capacitor between 17-1 and 18, 17-2 and 1
Let the capacitor between 8 and 8 be Ca2.

In this way, the capacitor Ca can be connected between terminal A and GND.
A composite capacitor Ca of 2 and Caw is formed, a composite capacitor cb of capacitors Cbx and cb2 is formed between terminal B and GND, and a capacitor C is formed between terminals A and B.
A composite capacitor Cc of CI and Cca is formed, and a fourth
This becomes the π-type circuit shown in the figure.

(3) Third Embodiment -------<Refer to Figs. 5 and 6) In this embodiment, a T-shaped circuit as shown in Fig. 6 is mounted on a multilayer board. This is an example of a capacitor block as shown in the figure.

In this circuit, capacitors cb and c are connected between terminals A and B.
The composite capacitor b- and the composite capacitor Cc1 and CC2 are connected in series, and the composite capacitor Ca1 and Ca2 is connected between the connection point and GND.

When such a T-shaped circuit is mounted on a multilayer board, it becomes as shown in FIG. Also in FIG. 5, only the capacitor electrode pattern is shown, and each layer of the multilayer substrate is not shown.

As shown in FIG. 5, a first capacitor electrode pattern 19 is formed on the first layer of the multilayer substrate, and a second capacitor electrode pattern 19 is formed on the second layer.
A capacitor electrode pattern 20 is formed on the third layer, and third and fourth capacitor electrode patterns 21-1.21 are formed on the third layer.
-2, a fifth capacitor electrode pattern 22 is formed on the fourth layer, and a sixth capacitor electrode pattern 23 is formed on the fifth layer.

In this case, the first and sixth capacitor electrode patterns 19.
23 are arranged to face each other in the stacking direction of the multilayer substrate, and these two capacitor electrode patterns are used as GND electrodes.

Also, these two capacitor electrode patterns 19.23
In between, the second capacitor electrode pattern 20, the third and fourth capacitor electrode patterns 21-1, 21-2, and the fifth capacitor are connected through dielectric layers (each layer of the multilayer substrate). An electrode pattern 22 is arranged.

Then, third and fourth capacitor electrode patterns 21-1
．． The total area of the group 21-2 is made into a capacitor block sandwiched between GND electrodes so that it is not larger than the area of the first or sixth capacitor electrode pattern, which is the GND electrode.

The connection between each of the above capacitor electrode patterns is as follows:
Connect terminal A to the capacitor electrode pattern 21-1 of
Terminal B is connected to the fourth capacitor electrode pattern 21-2, and then the first and sixth capacitor electrode patterns 19.
23 and the second and fifth capacitor electrode patterns 20
．． 22 are connected by blind through holes 14, respectively.

In addition, the first and sixth capacitor electrode patterns 19.23
is used as a GND electrode, so either one of the electrodes is connected to GND.

With this configuration, the capacitors formed between the respective capacitor electrode patterns are set as shown. That is, for each capacitor electrode pattern, the capacitor between 19 and 20 is Cax, the capacitor between 20 and 21-1 is Cb, the capacitor between 20 and 21-2 is Ccl, and the capacitor between 21-1 and 22 is Cbs. , the capacitor between 21-2 and 22 is CC2, and the capacitor between 22 and 23 is Ca2.

In this way, a capacitor Cb is connected between terminals A and B.
+ and Cb! composite capacitor cb and capacitor Cc1
A series circuit of composite capacitors Cc of capacitors Cal and Cc2 is formed, and a composite capacitor Ca of capacitors Cal and Cax is formed between the connection point of the two composite capacitors and GND.
is formed, and a T-shaped circuit as shown in FIG. 6 is obtained.

(4) Application example of the present invention to a low-pass filter ---
(See FIGS. 7 to 9) An example in which the capacitor block of the present invention is applied to a low-pass filter will be described based on FIGS. 7 to 9. In the figure, the same reference numerals as in FIG. 3 indicate the same parts. Also, 24-1
is the first layer of the multilayer substrate, 24-2 is the second layer, 24-
3 is the third layer, 24-4 is the fourth layer, 25-1 is the first coil pattern, 25-2 is the second coil pattern, 2
5-3 is a third coil pattern, 25-4 is a fourth coil pattern, 16 is an input terminal (IN), 27 is an output terminal (OUT>), and 28 is a GND terminal.

A circuit to which the capacitor block of the present invention is applied is as shown in FIG. 7, and the π-type circuit capacitor block shown in FIG. 3 is used as the capacitor block.

This low-pass filter has an input terminal IN and an output terminal OU.
A capacitor CC is provided between the input terminals [N and GND
In this circuit, a capacitor Ca is provided between them, a capacitor cb is provided between the output terminal OUT and GND, and a coil L is provided in parallel with the capacitor Cc.

When this circuit is mounted on a multilayer board, it becomes as shown in FIGS. 8 and 9.

The multilayer board is composed of four dielectric layers: a first layer 24-1, a second layer 24-2, a third layer 24-3, and a fourth layer 24-4.

On the first layer 24-1, a first capacitor electrode pattern 15 serving as a GND electrode, a GND terminal 28 integrally formed with the first capacitor electrode pattern 15, and an input terminal (
IN) 26, output terminal (OUT) 27, and first coil pattern 25-1 are formed as thick film patterns.

On the second layer 24-2, second and third capacitor electrode patterns 16-1, 16-2 and a second coil pattern 25-2 are formed as thick film patterns.
-3, there are fourth and fifth capacitor electrode patterns 17.
-1.17-2 and the third coil pattern 25-3 are formed as thick film patterns.

On the fourth layer 24-4, there is a sixth capacitor electrode pattern 18 serving as a GND electrode and a fourth coil pattern 25.
-4 is formed as a thick film pattern.

Then, the thick film patterns formed on each layer of the multilayer substrate are connected using blind through holes as shown by dotted lines in the figure.

In this way, one coil L is formed by the first coil pattern 25-1 to the fourth coil pattern 25-4, and each capacitor Ca1Cb, . , CC are formed.

That is, the capacitor formed between each capacitor electrode pattern is the capacitor Ca by combining the capacitor between 15.16-1 and the capacitor between 17-2.18, as shown in FIG. 2 and 17
-1.18 is combined to form capacitor cb, 16-1.17-1 and 16-2.
Capacitor Cc is obtained by combining the capacitors between 17 and 2.

Further, each of these capacitors Ca5Cb, Cc and the coil L are located between the first coil pattern 25-1 and the capacitor electrode pattern 16-2, and between the fourth coil pattern 25
-4 and the sixth capacitor electrode pattern 18, a circuit as shown in FIG. 7 is obtained.

Although the embodiments have been described above, the present invention is not limited to the above examples, but can also be implemented as follows.

(1) Since the π-type circuit and the T-type circuit can be mutually converted, either circuit may be used as the capacitor block.

However, it is better to use a π-type circuit in order to reduce the number of calendars on the multilayer board.

(2) The multilayer board that makes up the capacitor block is
In order to obtain the desired capacitance, it is also possible to use different high dielectric constant materials in each layer.

(3) In order to obtain the desired capacitance, it is also possible to change the thickness of each layer (thickness of the dielectric layer).

(4) It is also possible to add more layers to obtain the desired capacity.

(5) The capacitor block is applicable not only to the above-mentioned low-pass filter but also to various circuits.

(6) In FIG. 3, the fourth and fifth capacitor electrode patterns 17-1 and 17-2 may be connected to the terminal AXB.

〔Effect of the invention〕

As explained above, the present invention has the following effects.

(1) The capacitor block has a GND electrode (GND
Since the structure is sandwiched between the capacitor electrode patterns on the sides, there is no need to consider stray capacitance.

(2) Since there is no need for a conductor to connect the capacitors in the capacitor block (as the capacitors are directly connected, no conductor is required for the connection), it is necessary to consider the wiring component (inductance component). There is no.

(3) Since the capacitors of the capacitor block are formed in the stacking direction of the multilayer substrate, the capacitor block can be miniaturized.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram of the implementation of the capacitor block in the first embodiment of the present invention (π type circuit), and Fig. 2 is the π type circuit of the first embodiment.
Fig. 3 is an explanatory diagram of the implementation of the capacitor block in the second embodiment (π type circuit), Fig. 4 is an explanatory diagram of the π type circuit of the second embodiment, and Fig. 5 is an explanatory diagram of the π type circuit of the third embodiment. Figure 6 is an explanatory diagram of the T-type circuit of the third embodiment. 7 to 9 show an example in which the capacitor block of the present invention is applied to a low-pass filter, FIG. 7 is a circuit example of the low-pass filter, FIG. 8 is an exploded perspective view of the low-pass filter, and FIG. 8
It is a sectional view taken along the x-y line in the figure. 10 to 12 are diagrams showing conventional examples. FIG. io is an example of a π-type circuit, FIG. 11 is an example of a T-type circuit, and FIG. 12 is a cross-sectional view of a capacitor block. 10.15.19-First capacitor electrode pattern 11.16-1.2〇-Second capacitor electrode pattern 12.16-2.21-1.-Third capacitor electrode pattern 13.17-1. 21-2-Fourth capacitor electrode pattern 17-2.22-Fifth capacitor electrode pattern 18.
23-Sixth capacitor electrode pattern 14-Blind through hole Ca1, Cax, Ca-Capacitor Cb1, Cbz, cb----Capacitor A, B--Terminal Patent applicant TDC Co., Ltd. Agent Patent attorney
Tatsuo Imamura (1 other person) Saiy Ousei J1: Capacitor block to be used/) Tribute's nail theory sun and moon map (tile type rotation each) Figure 1 Figure 2 Figure 2 Spear 3X Circle 4 rows of T Mold circle 4 Shibaaki figure 6 figure 2 fruit 3 up and down

Claims (4)

[Claims] (1) A capacitor block having a plurality of capacitors built into a multilayer substrate, characterized in that a capacitor section constituting the capacitor block is disposed between GND electrodes that partially share the capacitor electrodes. (2) Add G to any layer (dielectric layer) that makes up the multilayer board.
First capacitor electrode pattern (10) which is an ND electrode
and for this first capacitor electrode pattern (10),
A second capacitor electrode pattern (11) is provided to face the stacking direction with the dielectric layer in between, and a second capacitor electrode pattern (11) is provided to face the second capacitor electrode pattern (11) in the stacking direction with the dielectric layer in between. , third capacitor electrode pattern (1
2), further providing a fourth capacitor electrode pattern (13) which is a GND electrode, facing the third capacitor electrode pattern (12) in the stacking direction with a dielectric layer interposed therebetween; By connecting the first and fourth capacitor electrode patterns (10) and 13) to GND, a π-type circuit is formed in the multilayer substrate by a plurality of capacitors sandwiched between the GND electrodes. capacitor block. (3) Add G to any layer (dielectric layer) that makes up the multilayer board.
First capacitor electrode pattern (15) which is an ND electrode
and for this first capacitor electrode pattern (15),
Second and third capacitor electrode patterns (16-1,
16-2), and the second and third capacitor electrode patterns (16-1,
16-2), fourth and fifth capacitor electrode patterns (17-1, 17-2) are provided which are independent of each other and are opposed to each other in the stacking direction with a dielectric layer interposed therebetween; 5 capacitor electrode pattern (17-1
, 17-2), a sixth capacitor electrode pattern (18), which is a GND electrode, is provided opposite to each other in the stacking direction via a dielectric layer, and the first and sixth capacitor electrode patterns (15 , 18) to GND, and connect the second and fifth capacitor electrode patterns (16-1
, 17-2) and between the third and fourth capacitor electrode patterns (16-2, 17-1),
A capacitor block characterized in that a π-type circuit formed by a plurality of capacitors sandwiched between GND electrodes is formed in a multilayer substrate. (4) Add G to any layer (dielectric layer) constituting the multilayer board.
First capacitor electrode pattern (19) which is an ND electrode
and for this first capacitor electrode pattern (19),
A second capacitor electrode pattern (20) is provided to face the stacking direction with the dielectric layer in between, and a second capacitor electrode pattern (20) is provided to face the second capacitor electrode pattern (20) in the stacking direction with the dielectric layer in between. , third and fourth capacitor electrode patterns (21-1, 21-2) independent of each other are provided, and the third and fourth capacitor electrode patterns (21-1,
21-2), a fifth capacitor electrode pattern (22) is provided so as to face each other in the stacking direction with a dielectric layer interposed therebetween, and a dielectric material A sixth capacitor electrode pattern (23), which is a GND electrode, is provided so as to face each other in the stacking direction through the layers, and the first and sixth capacitor electrode patterns (19, 23) are connected to GND. In addition, by connecting the second and fifth capacitor electrode patterns (20, 22), a T-shaped circuit of a plurality of capacitors sandwiched between GND electrodes is formed in the multilayer substrate. block.