JPH0653075A - Laminated ceramic capacitor for balanced line - Google Patents
Laminated ceramic capacitor for balanced lineInfo
- Publication number
- JPH0653075A JPH0653075A JP4219719A JP21971992A JPH0653075A JP H0653075 A JPH0653075 A JP H0653075A JP 4219719 A JP4219719 A JP 4219719A JP 21971992 A JP21971992 A JP 21971992A JP H0653075 A JPH0653075 A JP H0653075A
- Authority
- JP
- Japan
- Prior art keywords
- outer periphery
- electrodes
- capacitor
- internal electrode
- ceramic capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000003985 ceramic capacitor Substances 0.000 title claims description 27
- 239000000919 ceramic Substances 0.000 claims description 26
- 239000003990 capacitor Substances 0.000 abstract description 24
- 239000002648 laminated material Substances 0.000 abstract 4
- 230000002093 peripheral effect Effects 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000010304 firing Methods 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 description 1
- 229910002113 barium titanate Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007606 doctor blade method Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 229920000728 polyester Polymers 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/38—Multiple capacitors, i.e. structural combinations of fixed capacitors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Ceramic Capacitors (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は電話機、モデム等の通信
回路、或いはＤＣ−ＤＣコンバータ等の電源供給回路の
平衡線路にチップ型ノイズフィルタ（chip noise filte
r）として用いられる積層セラミックコンデンサに関す
る。更に詳しくは３個のコンデンサが内蔵されかつ３端
子が一体化された、電磁妨害ノイズ（electromagnetic
inter-ference）を吸収するに適したチップ型のバイパ
スコンデンサに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip noise filter for a balanced line of a communication circuit such as a telephone or a modem, or a power supply circuit such as a DC-DC converter.
r) The monolithic ceramic capacitor used as More specifically, the electromagnetic interference noise (electromagnetic interference noise) in which three capacitors are built in and three terminals are integrated
The present invention relates to a chip type bypass capacitor suitable for absorbing inter-ference).
【０００２】[0002]
【従来の技術】この種の通信回路又は電源供給回路に
は、一対の入力線路とアース線路からなる三線の平衡線
路（three wire balanced line）が使用される。こうし
た回路には同相ノイズ（common-mode noise）や差動ノ
イズ（differential noise）を除去するためにローパス
フィルタ又はバイパスフィルタが必要である。具体的に
は、図１７に示すように入力線路Ａとアース線路Ｇとの
間に積層セラミックコンデンサＣ1を、入力線路Ｂとア
ース線路Ｇとの間に積層セラミックコンデンサＣ2を、
また入力線路ＡとＢの間に積層セラミックコンデンサＣ
3をそれぞれ接続したフィルタがしばしば用いられる。
従来、上記３個の積層セラミックコンデンサのそれぞれ
は、１つのシート外周辺まで延びこのシート外周辺と反
対側のシート外周辺とは間隔をあけてシート表面に内部
電極が形成された角形の２枚のセラミック誘電体シート
を一組とし、これら２枚のセラミック誘電体シートを内
部電極の延びたシート外周辺がそれぞれ反対側になるよ
うに重ね合せ、この重ね合せた一組のセラミック誘電体
シートを複数組積層し一体化してなる積層体と、積層体
の両側面にそれぞれ露出した内部電極に接続して形成さ
れた一対の外部電極とを備える。そして３個のコンデン
サはプリント回路基板に別々に実装される。2. Description of the Related Art In this type of communication circuit or power supply circuit, a three wire balanced line consisting of a pair of input lines and a ground line is used. Such circuits require low pass or bypass filters to remove common-mode noise and differential noise. Specifically, as shown in FIG. 17, a monolithic ceramic capacitor C 1 is provided between the input line A and the earth line G, and a monolithic ceramic capacitor C 2 is provided between the input line B and the earth line G.
Also, between the input lines A and B, a monolithic ceramic capacitor C
Filters with three connected each are often used.
Conventionally, each of the above-mentioned three monolithic ceramic capacitors extends to the outer periphery of one sheet, and two rectangular prisms in which internal electrodes are formed on the surface of the sheet with a gap between the outer periphery of the sheet and the outer periphery of the opposite side sheet. Ceramic dielectric sheets as a set, and these two ceramic dielectric sheets are superposed so that the outer peripheries of the sheets where the internal electrodes extend are on opposite sides. A laminated body formed by laminating and integrating a plurality of sets, and a pair of external electrodes formed by connecting to internal electrodes exposed on both side surfaces of the laminated body are provided. Then, the three capacitors are separately mounted on the printed circuit board.
【０００３】[0003]
【発明が解決しようとする課題】このため、従来の３個
の積層セラミックコンデンサからなるフィルタでは、個
別にコンデンサを基板に実装するため、プリント配線が
複雑になり、プリント配線の残留インダクタンスのた
め、フィルタとしてのノイズ吸収性能に劣っていた。更
にコンデンサを基板に実装する際に、基板に広い実装面
積を必要とし、電子機器を小型化できない問題点があっ
た。本発明の目的は、小型で実装面積が少なくて済み、
高密度に回路基板に実装して電子機器を小型化できる平
衡線路用積層セラミックコンデンサを提供することにあ
る。本発明の別の目的は、単一の素子で３個のコンデン
サを近接して内蔵しかつ３端子を一体化することによ
り、フィルタ応答性が改善された、三線の平衡線路にお
ける同相ノイズや差動ノイズの除去が可能な平衡線路用
積層セラミックコンデンサを提供することにある。Therefore, in the conventional filter composed of three monolithic ceramic capacitors, the capacitors are individually mounted on the substrate, the printed wiring becomes complicated, and the residual inductance of the printed wiring causes It was inferior in noise absorption performance as a filter. Further, when mounting the capacitor on the substrate, there is a problem that a large mounting area is required on the substrate and the electronic device cannot be downsized. The object of the present invention is to have a small size and a small mounting area,
An object of the present invention is to provide a monolithic ceramic capacitor for balanced lines, which can be mounted on a circuit board with high density to reduce the size of electronic equipment. Another object of the present invention is to incorporate three capacitors in close proximity by a single element and integrate three terminals so that common-mode noise and difference in a three-wire balanced line in which filter response is improved. An object of the present invention is to provide a monolithic ceramic capacitor for balanced lines capable of removing dynamic noise.
【０００４】[0004]
【課題を解決するための手段】上記目的を達成するため
の本発明の構成を図１、図５及び図８に基づいて説明す
る。本発明の積層セラミックコンデンサ５０は、１つの
外周辺まで延びこの外周辺と反対側の外周辺とは間隔を
あけて第１内部電極１０ａが表面に形成された角形の第
１セラミック誘電体シート１０と、前記反対側の外周辺
まで延び前記１つの外周辺とは間隔をあけて第２内部電
極２０ａが表面に形成された角形の第２セラミック誘電
体シート２０と、両電極１０ａ，２０ａの延びていない
相対向する２つの外周辺まで延び両電極１０ａ，２０ａ
の延びている相対向する２つの外周辺とは間隔をあけて
第３内部電極３０ａが表面に形成された第３セラミック
誘電体シート３０とを交互に積重ねて積層体４５が形成
される。更に、この積層体４５の両側面には両電極１０
ａ，２０ａに接続する平衡線路接続用の一対の第１及び
第２外部電極４１，４２がそれぞれ形成され、この積層
体４５の別の両側面には第３内部電極３０ａに接続する
接地用の第３外部電極４３がそれぞれ形成される。A configuration of the present invention for achieving the above object will be described with reference to FIGS. 1, 5 and 8. The monolithic ceramic capacitor 50 of the present invention extends to one outer periphery and has a rectangular first ceramic dielectric sheet 10 on the surface of which a first internal electrode 10a is formed at a distance from the outer periphery and the opposite outer periphery. And a rectangular second ceramic dielectric sheet 20 having a second internal electrode 20a formed on the surface thereof and extending to the outer periphery on the opposite side and spaced apart from the one outer periphery, and the extension of both electrodes 10a, 20a. Both electrodes 10a, 20a extending to the outer periphery not facing each other
And the third ceramic dielectric sheets 30 having the third internal electrodes 30a formed on the surface thereof are alternately stacked with the two outer peripheries facing each other extending from each other to form a laminated body 45. Further, both electrodes 10 are formed on both side surfaces of the laminated body 45.
a pair of first and second external electrodes 41 and 42 for connecting a balanced line, which are connected to a and 20a, respectively, are formed, and the other side surfaces of this laminated body 45 are connected to the third internal electrode 30a for grounding. The third external electrodes 43 are formed respectively.
【０００５】[0005]
【作用】図８に示すように、コンデンサ５０を線路Ａ，
Ｂ，Ｇに接続すると、第１外部電極４１と第２外部電極
４２との間で差動ノイズを吸収するための１つのコンデ
ンサＣ3が形成され、第１外部電極４１と第３外部電極
４３との間及び第２外部電極４２と第３外部電極４３と
の間でそれぞれ同相ノイズを吸収するための２つのコン
デンサＣ1及びＣ2が形成される。このような構成のチッ
プ型の積層セラミックコンデンサは、３個のコンデンサ
が内蔵されかつ３つの端子電極４１，４２，４３が積層
体４５の側面に一体化するので、第一にフィルタ応答性
が改善され、第二に３個のコンデンサを単一の素子の形
態で、僅かなスペースと僅かな工数で回路基板に実装す
ることができる。As shown in FIG. 8, the capacitor 50 is connected to the line A,
When connected to B and G, one capacitor C 3 for absorbing differential noise is formed between the first external electrode 41 and the second external electrode 42, and the first external electrode 41 and the third external electrode 43 are formed. And the second external electrode 42 and the third external electrode 43, two capacitors C 1 and C 2 for absorbing in-phase noise are formed. In the chip type monolithic ceramic capacitor having such a configuration, three capacitors are built in and the three terminal electrodes 41, 42, 43 are integrated on the side surface of the laminated body 45, so that the filter response is improved first. Secondly, the three capacitors can be mounted on the circuit board in the form of a single element with a small space and a small number of steps.
【０００６】[0006]
【実施例】次に、本発明の実施例を図面に基づいて詳し
く説明する。 ＜実施例１＞先ず、誘電体グリーンシートを多数枚用意
した。この誘電体グリーンシートはポリエステルベース
シートの上面にチタン酸バリウム系のＪＩＳ−Ｒ特性を
有する誘電体スラリーをドクターブレード法によりコー
ティングした後、乾燥して形成される。これらのグリー
ンシートのうち、ある１群を第１セラミックグリーンシ
ートとし、別の群を第２セラミックグリーンシートと
し、更に別の群を第３セラミックグリーンシートとし
た。次いで第１、第２及び第３セラミックグリーンシー
トの各表面にそれぞれ別々のパターンでＡｇ／Ｐｄを主
成分とする導電性ペーストをスクリーン印刷し、８０℃
で４分間乾燥した。即ち、図５に示すように第１セラミ
ックグリーンシート１０の表面には、１つの外周辺まで
延びこの外周辺と反対側の外周辺とは間隔をあけて第１
内部電極１０ａが印刷形成された。また第２セラミック
グリーンシート２０の表面には、前記反対側の外周辺ま
で延び前記１つの外周辺とは間隔をあけて第２内部電極
２０ａが印刷形成された。更に第３セラミックグリーン
シート３０の表面には、両内部電極１０ａ，２０ａの延
びていない相対向する２つの外周辺まで延び両内部電極
１０ａ，２０ａの延びている相対向する２つの外周辺と
は間隔をあけて十字状の第３内部電極３０ａが印刷形成
された。この例では、３つの内部電極１０ａと２０ａと
３０ａの各面積はそれぞれ等しい。Embodiments of the present invention will now be described in detail with reference to the drawings. <Example 1> First, a large number of dielectric green sheets were prepared. This dielectric green sheet is formed by coating a barium titanate-based dielectric slurry having JIS-R characteristics on the upper surface of a polyester base sheet by a doctor blade method and then drying. Of these green sheets, one group was a first ceramic green sheet, another group was a second ceramic green sheet, and another group was a third ceramic green sheet. Then, a conductive paste containing Ag / Pd as a main component is screen-printed on the respective surfaces of the first, second and third ceramic green sheets in different patterns, and the temperature is set to 80 ° C.
And dried for 4 minutes. That is, as shown in FIG. 5, on the surface of the first ceramic green sheet 10, the first ceramic green sheet 10 extends to one outer periphery and is spaced apart from the outer periphery on the opposite side.
The internal electrode 10a was formed by printing. A second internal electrode 20a was formed on the surface of the second ceramic green sheet 20 by printing, extending to the outer periphery on the opposite side and spaced apart from the one outer periphery. Furthermore, on the surface of the third ceramic green sheet 30, there are two outer peripheral portions of the internal electrodes 10a, 20a which extend to the two outer peripheral portions of the internal electrodes 10a, 20a which face each other and which do not extend. Cross-shaped third internal electrodes 30a were formed by printing at intervals. In this example, the areas of the three internal electrodes 10a, 20a, and 30a are equal.
【０００７】図１及び図５に示すように、この例では第
２誘電体シート２０の上に、第１誘電体シート１０、第
３誘電体シート３０、第２誘電体シート２０、第１誘電
体シート１０、第３誘電体シート３０、及び第２誘電体
シート２０をこの順に積層した。この最上層には導電性
ペーストを全く印刷していない第４セラミックグリーン
シート４０を重ね合わせて合計８層の積層体４５を得
た。この積層体４５を熱圧着して一体化した後、１３０
０℃で約１時間焼成して焼結体を得た。この焼結体をバ
レル研磨して焼結体の周囲側面に内部電極１０ａ，２０
ａ及び３０ａを露出させた（図６）。この内部電極１０
ａ，２０ａが露出する焼結体の両端部にそれぞれＡｇを
主成分とする導電性ペーストを塗布し、また内部電極３
０ａが露出する焼結体の中央部の全周に同じ導電性ペー
ストを塗布した後、これらの導電性ペーストを焼付けて
一対の第１及び第２外部電極４１，４２と第３外部電極
４３をそれぞれ形成した。これにより、図７に示す積層
セラミックコンデンサ５０が得られた。As shown in FIGS. 1 and 5, in this example, the first dielectric sheet 10, the third dielectric sheet 30, the second dielectric sheet 20, and the first dielectric sheet 20 are provided on the second dielectric sheet 20. The body sheet 10, the third dielectric sheet 30, and the second dielectric sheet 20 were laminated in this order. A fourth ceramic green sheet 40 on which no conductive paste was printed was superposed on this uppermost layer to obtain a laminated body 45 having a total of eight layers. After the laminated body 45 is thermocompression bonded and integrated, 130
A sintered body was obtained by firing at 0 ° C. for about 1 hour. This sintered body is barrel-polished to form internal electrodes 10a, 20 on the peripheral side surfaces of the sintered body.
a and 30a were exposed (FIG. 6). This internal electrode 10
A conductive paste containing Ag as a main component is applied to both ends of the sintered body where a and 20a are exposed, and the internal electrode 3
After applying the same conductive paste to the entire circumference of the central portion of the sintered body where 0a is exposed, these conductive pastes are baked to form a pair of the first and second external electrodes 41, 42 and the third external electrode 43. Formed respectively. As a result, the monolithic ceramic capacitor 50 shown in FIG. 7 was obtained.
【０００８】この積層セラミックコンデンサ５０の特性
を調べるために、図８に示すように一対の入力線路Ａ及
びＢとアース線路Ｇのある三線の平衡線路にこの積層セ
ラミックコンデンサ５０を接続した。具体的には積層セ
ラミックコンデンサ５０の第１外部電極４１を線路Ａ
に、第２外部電極４２を線路Ｂに、第３外部電極４３を
線路Ｇにそれぞれ接続した。この平衡線路に高周波ノイ
ズ、電磁波等を混入した信号を流したところ、第１外部
電極４１と第２外部電極４２との間で差動ノイズが吸収
され、第１外部電極４１と第３外部電極４３との間及び
第２外部電極４２と第３外部電極４３との間でそれぞれ
同相ノイズが吸収された。この例では図８の回路におい
て、３つのコンデンサのキャパシタンスは次式で表わさ
れる。 Ｃ1 ＝ Ｃ2 ＝ Ｃ3 （１）In order to investigate the characteristics of the monolithic ceramic capacitor 50, the monolithic ceramic capacitor 50 was connected to a three-line balanced line having a pair of input lines A and B and a ground line G as shown in FIG. Specifically, the first external electrode 41 of the monolithic ceramic capacitor 50 is connected to the line A.
The second external electrode 42 was connected to the line B, and the third external electrode 43 was connected to the line G. When a signal mixed with high-frequency noise, electromagnetic waves, etc. is passed through this balanced line, the differential noise is absorbed between the first external electrode 41 and the second external electrode 42, and the first external electrode 41 and the third external electrode are absorbed. In-phase noise was absorbed between the second external electrode 42 and the third external electrode 43. In this example, in the circuit of FIG. 8, the capacitances of the three capacitors are represented by the following equation. C 1 = C 2 = C 3 (1)
【０００９】＜実施例２＞図９〜図１２は本発明の実施
例２の積層セラミックコンデンサの断面図である。これ
らの図において、図１〜図４に示した符号と同一符号は
同じ構成部品を示す。この例では第１誘電体シート１０
の上に、第３誘電体シート３０、第２誘電体シート２
０、第３誘電体シート３０、第１誘電体シート１０、第
３誘電体シート３０、及び第２誘電体シート２０をこの
順に積層した。この最上層には導電性ペーストを全く印
刷していない第４セラミックグリーンシート４０を重ね
合わせて合計８層の積層体４５を得た。この例では、内
部電極３０ａの面積は内部電極２０ａと３０ａの各面積
の半分である。その他の構成は実施例１と同じであるの
で、繰返しの説明を省略する。この積層セラミックコン
デンサの特性は、実施例１と同様であった。ただし、こ
の例では図８の回路において、３つのコンデンサのキャ
パシタンスは次式で表わされる。 Ｃ1 ＝ Ｃ2 ＝ Ｃ3／２．５ （２）<Embodiment 2> FIGS. 9 to 12 are sectional views of a laminated ceramic capacitor according to Embodiment 2 of the present invention. In these figures, the same reference numerals as those shown in FIGS. 1 to 4 indicate the same components. In this example, the first dielectric sheet 10
On top of the third dielectric sheet 30 and the second dielectric sheet 2
0, the third dielectric sheet 30, the first dielectric sheet 10, the third dielectric sheet 30, and the second dielectric sheet 20 were laminated in this order. A fourth ceramic green sheet 40 on which no conductive paste was printed was superposed on this uppermost layer to obtain a laminated body 45 having a total of eight layers. In this example, the area of the internal electrode 30a is half the area of each of the internal electrodes 20a and 30a. Since other configurations are the same as those of the first embodiment, the repeated description will be omitted. The characteristics of this multilayer ceramic capacitor were similar to those of Example 1. However, in this example, the capacitances of the three capacitors in the circuit of FIG. 8 are represented by the following equation. C 1 = C 2 = C 3 /2.5 (2)
【００１０】＜実施例３＞図１３〜図１６は本発明の実
施例３の積層セラミックコンデンサの断面図である。こ
れらの図において、図１〜図４に示した符号と同一符号
は同じ構成部品を示す。この例では第２誘電体シート２
０の上に、第１誘電体シート１０、第２誘電体シート２
０、第３誘電体シート３０、第１誘電体シート１０、第
２誘電体シート２０、第１誘電体シート１０、第３誘電
体シート３０、及び第２誘電体シート２０をこの順に積
層した。この最上層には導電性ペーストを全く印刷して
いない第４セラミックグリーンシート４０を重ね合わせ
て合計１０層の積層体４５を得た。この例では、３つの
内部電極１０ａと２０ａと３０ａの各面積はそれぞれ等
しい。その他の構成は実施例１と同じであるので、繰返
しの説明を省略する。この積層セラミックコンデンサの
特性は、実施例１と同様であった。ただし、この例では
図８の回路において、３つのコンデンサのキャパシタン
スは次式で表わされる。 Ｃ1 ＝ Ｃ2 ＝ Ｃ3／２ （３）<Third Embodiment> FIGS. 13 to 16 are sectional views of a monolithic ceramic capacitor according to a third embodiment of the present invention. In these figures, the same reference numerals as those shown in FIGS. 1 to 4 indicate the same components. In this example, the second dielectric sheet 2
0 on top of the first dielectric sheet 10 and the second dielectric sheet 2
0, the third dielectric sheet 30, the first dielectric sheet 10, the second dielectric sheet 20, the first dielectric sheet 10, the third dielectric sheet 30, and the second dielectric sheet 20 were laminated in this order. A fourth ceramic green sheet 40 on which no conductive paste was printed was superposed on this uppermost layer to obtain a laminated body 45 having a total of 10 layers. In this example, the areas of the three internal electrodes 10a, 20a, and 30a are equal. Since other configurations are the same as those of the first embodiment, the repeated description will be omitted. The characteristics of this multilayer ceramic capacitor were similar to those of Example 1. However, in this example, the capacitances of the three capacitors in the circuit of FIG. 8 are represented by the following equation. C 1 = C 2 = C 3 /2 (3)
【００１１】なお、本発明のセラミック誘電体シートの
積層数、接地用の第３内部電極３０ａの面積の広さは上
記例に限られるものではなく、必要とされるキャパシタ
ンスに応じて適宜変更することができる。The number of laminated ceramic dielectric sheets of the present invention and the size of the area of the third internal electrode 30a for grounding are not limited to the above examples, but may be appropriately changed according to the required capacitance. be able to.
【００１２】[0012]
【発明の効果】以上述べたように、本発明によれば、単
一の素子で３個のコンデンサを内蔵しかつ３端子を一体
化した小型のコンデンサを実現したので、プリント回路
基板への実装面積を広く必要とせず、僅かな工数で実装
でき、同時にフィルタ応答性を改善できる。また、三線
の平衡線路における同相ノイズや差動ノイズの除去する
ことができ、電磁妨害雑音（ＥＭＩ）を吸収するチップ
型ノイズフィルタ（ＣＮＦ）として好適に利用できる。
更に、第１内部電極の面積に対して第２内部電極の面積
を可変にすれば、内蔵するコンデンサのキャパシタンス
を変更できる利点もある。As described above, according to the present invention, a small capacitor in which three capacitors are built in a single element and three terminals are integrated is realized. Therefore, the capacitor is mounted on a printed circuit board. It does not require a large area and can be mounted with a small number of steps, and at the same time, the filter response can be improved. Further, in-phase noise and differential noise in the three balanced lines can be removed, and it can be suitably used as a chip type noise filter (CNF) that absorbs electromagnetic interference noise (EMI).
Further, by making the area of the second internal electrode variable with respect to the area of the first internal electrode, there is an advantage that the capacitance of the built-in capacitor can be changed.
【図１】本発明実施例の積層セラミックコンデンサのＣ
1＝Ｃ2＝Ｃ3の関係が成立する図７のＨ−Ｈ線断面図。FIG. 1 is a C of a multilayer ceramic capacitor according to an embodiment of the present invention
FIG. 8 is a sectional view taken along the line HH of FIG. 7 in which the relationship of 1 = C 2 = C 3 is established.
【図２】そのＪ−Ｊ線断面図。FIG. 2 is a sectional view taken along the line JJ.
【図３】そのＫ−Ｋ線断面図。FIG. 3 is a sectional view taken along the line KK.
【図４】そのＬ−Ｌ線断面図。FIG. 4 is a sectional view taken along the line LL.
【図５】その積層体の積層前の斜視図。FIG. 5 is a perspective view of the stacked body before stacking.
【図６】その積層体を焼成した焼結体の斜視図。FIG. 6 is a perspective view of a sintered body obtained by firing the laminated body.
【図７】その焼結体に第１〜第３外部電極を設けて作製
された積層セラミックコンデンサの斜視図。FIG. 7 is a perspective view of a laminated ceramic capacitor manufactured by providing first to third external electrodes on the sintered body.
【図８】その積層セラミックコンデンサを平衡線路に接
続した回路図。FIG. 8 is a circuit diagram in which the multilayer ceramic capacitor is connected to a balanced line.
【図９】本発明別の実施例の積層セラミックコンデンサ
のＣ1＝Ｃ2＝Ｃ3／２．５の関係が成立する図１に対応
する断面図。FIG. 9 is a cross-sectional view corresponding to FIG. 1 in which a relationship of C 1 = C 2 = C 3 /2.5 of a multilayer ceramic capacitor according to another embodiment of the present invention is established.
【図１０】そのＭ−Ｍ線断面図。FIG. 10 is a sectional view taken along line MM.
【図１１】そのＮ−Ｎ線断面図。FIG. 11 is a sectional view taken along the line NN.
【図１２】そのＯ−Ｏ線断面図。FIG. 12 is a sectional view taken along line OO.
【図１３】本発明別の実施例の積層セラミックコンデン
サのＣ1＝Ｃ2＝Ｃ3／２の関係が成立する図１に対応す
る断面図。[13] C 1 = C 2 = cross-sectional view C 3/2 relationship corresponding to FIG. 1 which satisfies the multilayer ceramic capacitor of the present invention another embodiment.
【図１４】そのＰ−Ｐ線断面図。FIG. 14 is a sectional view taken along the line P-P.
【図１５】そのＱ−Ｑ線断面図。FIG. 15 is a sectional view taken along the line QQ.
【図１６】そのＲ−Ｒ線断面図。FIG. 16 is a sectional view taken along the line RR.
【図１７】従来の積層セラミックコンデンサを平衡線路
に接続した回路図。FIG. 17 is a circuit diagram in which a conventional monolithic ceramic capacitor is connected to a balanced line.
１０ 第１セラミック誘電体シート（第１セラミックグ
リーンシート） １０ａ 第１内部電極 ２０ 第２セラミック誘電体シート（第２セラミックグ
リーンシート） ２０ａ 第２内部電極 ３０ 第３セラミック誘電体シート（第３セラミックグ
リーンシート） ３０ａ 第３内部電極 ４１ 第１外部電極 ４２ 第２外部電極 ４３ 第３外部電極 ４５ 積層体 ５０ 積層セラミックコンデンサ10 1st ceramic dielectric sheet (1st ceramic green sheet) 10a 1st internal electrode 20 2nd ceramic dielectric sheet (2nd ceramic green sheet) 20a 2nd internal electrode 30 3rd ceramic dielectric sheet (3rd ceramic green sheet) Sheet) 30a Third internal electrode 41 First external electrode 42 Second external electrode 43 Third external electrode 45 Laminated body 50 Multilayer ceramic capacitor
Claims (1)
側の外周辺とは間隔をあけて第１内部電極(10a)が表面
に形成された角形の第１セラミック誘電体シート(10)
と、 前記反対側の外周辺まで延び前記１つの外周辺とは間隔
をあけて第２内部電極(20a)が表面に形成された角形の
第２セラミック誘電体シート(20)と、 前記第１及び第２内部電極(10a,20a)の延びていない相
対向する２つの外周辺まで延び前記第１及び第２内部電
極(10a,20a)の延びている相対向する２つの外周辺とは
間隔をあけて第３内部電極(30a)が表面に形成された第
３セラミック誘電体シート(30)とを交互に積重ねて形成
された積層体(45)と、 前記積層体(45)の両側面にそれぞれ形成され前記第１及
び第２内部電極(10a,20a)に接続する平衡線路接続用の
一対の第１及び第２外部電極(41,42)と、 前記積層体(45)の別の両側面にそれぞれ形成され前記第
３内部電極(30a)に接続する接地用の第３外部電極(43)
とを備えた平衡線路用積層セラミックコンデンサ。1. A rectangular first ceramic dielectric sheet (10) extending to one outer periphery and having a first internal electrode (10a) formed on the surface thereof at a distance from the outer periphery and an opposite outer periphery.
A rectangular second ceramic dielectric sheet (20) having a second internal electrode (20a) formed on the surface thereof and extending to the outer periphery on the opposite side and spaced apart from the one outer periphery; And the two outer peripheries of the first and second internal electrodes (10a, 20a) that extend to the two outer peripheries of the second internal electrodes (10a, 20a) that do not extend and are opposed to each other. A laminated body (45) formed by alternately stacking a third ceramic dielectric sheet (30) having a third internal electrode (30a) formed on its surface, and both side surfaces of the laminated body (45). A pair of first and second outer electrodes (41, 42) for connecting balanced lines, which are respectively formed on the first and second inner electrodes (10a, 20a), and another of the laminated body (45). Third external electrode (43) for grounding, which is formed on both sides and is connected to the third internal electrode (30a)
A monolithic ceramic capacitor for balanced lines, which comprises:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4219719A JPH0653075A (en) | 1992-07-27 | 1992-07-27 | Laminated ceramic capacitor for balanced line |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4219719A JPH0653075A (en) | 1992-07-27 | 1992-07-27 | Laminated ceramic capacitor for balanced line |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0653075A true JPH0653075A (en) | 1994-02-25 |
Family
ID=16739902
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4219719A Withdrawn JPH0653075A (en) | 1992-07-27 | 1992-07-27 | Laminated ceramic capacitor for balanced line |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0653075A (en) |
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-
1992
- 1992-07-27 JP JP4219719A patent/JPH0653075A/en not_active Withdrawn
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| US7688568B1 (en) | 2008-10-10 | 2010-03-30 | Samsung Electro-Mechanics Co., Ltd. | Multilayer chip capacitor |
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| JP2020145460A (en) * | 2014-01-13 | 2020-09-10 | アップル インコーポレイテッドＡｐｐｌｅ Ｉｎｃ． | Acoustic noise cancellation of multi-layer capacitor |
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Legal Events
| Date | Code | Title | Description |
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| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19991005 |