JPH07240651A - Pie filter - Google Patents

Pie filter

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Publication number
JPH07240651A
JPH07240651A JP2812694A JP2812694A JPH07240651A JP H07240651 A JPH07240651 A JP H07240651A JP 2812694 A JP2812694 A JP 2812694A JP 2812694 A JP2812694 A JP 2812694A JP H07240651 A JPH07240651 A JP H07240651A
Authority
JP
Japan
Prior art keywords
capacitor
chip
circuit board
pie
ferrite
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2812694A
Other languages
Japanese (ja)
Inventor
Akira Uchida
彰 内田
Original Assignee
Mitsubishi Materials Corp
三菱マテリアル株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Materials Corp, 三菱マテリアル株式会社 filed Critical Mitsubishi Materials Corp
Priority to JP2812694A priority Critical patent/JPH07240651A/en
Publication of JPH07240651A publication Critical patent/JPH07240651A/en
Application status is Withdrawn legal-status Critical

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Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/181Printed circuits structurally associated with non-printed electric components associated with surface mounted components

Abstract

PURPOSE: To obtain a pie filter where packaging density is improved by arranging a chip capacitor incoporating plural capacitor elements on one side of a part interposed with a circuit board and arranging a ferrite chip based on the other side.
CONSTITUTION: Between two capacitor elements 10 and 11 incorporated in a chip capacitor 100, the inductor element 27 incorporated in a ferrite chip base 200 is arranged, and a pie filter circuit is formed as a whole. Thus, the ferrite chip bead 200 and the chip capacitor 100 are arranged at the correspondent location of the front and back surfaces of the circuit board and are connected to each other through holes 34a and 34b. As a result, the packaging space is saved by one capacitor as compared with a case where three elements of two capacitors and one ferrite based are arranged on the circuit board, the front and back surfaces of the circuit board are used so that a pie shape filter which is formed in a compact shape can be obtained.
COPYRIGHT: (C)1995,JPO

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【産業上の利用分野】本発明は、電子機器のノイズ対策等に用いられるパイ形フィルタに関する。 The present invention relates, on the pie-shaped filter used for noise suppression of electronic equipment.

【0002】 [0002]

【従来の技術】従来、電子機器の高周波ノイズ対策用としてコンデンサ,フェライトビーズ,T形EMIフィルタ等の電子部品が販売されているが、パイ(π)形のE Conventionally, a capacitor as a high-frequency noise suppression of electronic devices, ferrite beads, the electronic components such as a T-shaped EMI filters have been sold, pi (π) form of E
MIフィルタは販売されていない。 MI filter has not been sold. これはパイ形EMI This is pie-shaped EMI
フィルタの需要がないという理由ではなく、コンデンサを構成する誘電体とフェライトビーズを構成する磁性体を積層して同時に焼成すると誘電体と磁性体との収縮率の相違によりクラックが発生してしまう等、製造上の困難性やコスト等の理由によるものである。 Not because there is no demand for filters, such as cracks by shrinkage difference in the firing simultaneously by laminating magnetic body constituting the dielectric and ferrite bead constituting the capacitor dielectric and magnetic material occurs is due to reasons of difficulty and cost, etc. in manufacturing. このため、従来パイ形ノイズフィルタが必要な場合は、基板に2個のコンデンサと1個のフェライトビーズを配置してそれにより構成されるパイ形フィルタを使用していた。 Therefore, if the conventional pie-shaped noise filters required, thereby it was using pie-shaped filter formed by arranging the two capacitors and one ferrite bead to a substrate.

【0003】 [0003]

【発明が解決しようとする課題】このため、上記のように基板上に2個のコンデンサと1組のフェライトビーズを配置してパイ形フィルタを構成するのでは基板実装密度を上げられないという問題を抱えていた。 THE INVENTION Problems to be Solved Therefore, a problem that is of configuring the pie-shaped filter arranged two capacitors and a pair of ferrite beads on the substrate as described above not be increased substrate mounting density the I was having. 本発明は、 The present invention,
上記事情に鑑み、実装密度を向上させたパイ形フィルタを提案することを目的とする。 In view of the above circumstances, and an object thereof is to propose a pie-shaped filter with improved mounting density.

【0004】 [0004]

【課題を解決するための手段】上記目的を達成する本発明のパイ形フィルタは、 (1)回路基板 (2)その回路基板の一面に搭載された、複数のコンデンサ素子を内蔵してなるチップコンデンサ (3)その回路基板の他面に搭載された、回路基板のスルーホールを介してチップコンデンサと接続され上記複数のコンデンサ素子と共にパイ形フィルタ回路を形成してなるインダクタを内蔵したフェライトチップビーズ を備えたことを特徴とする。 Means for Solving the Problems] pie-shaped filter of the present invention to achieve the above object, (1) mounted on the circuit board (2) one surface of the circuit board, comprising an integrated plurality of capacitor elements chip capacitor (3) its other surface of the circuit board is mounted, the ferrite chip bead having a built-in inductor obtained by forming a pie-shaped filter circuit together with the plurality of capacitor elements are connected to the chip capacitor through the through holes of the circuit board characterized by comprising a.

【0005】 [0005]

【作用】本発明のパイ形フィルタは、上記のように回路基板を挟んだ一方に複数のコンデンサ素子を内蔵するチップコンデンサを配置し、他方にフェライトチップビーズを配置してパイ形フィルタを構成したため、コンデンサ1個分の実装密度を上げることができ、また回路基板の両面を使うことで小さくまとまったパイ形フィルタが構成される。 [Action] pie-shaped filter of the present invention, a chip capacitor incorporating a plurality of capacitor elements in one sandwiching the circuit board as described above is arranged, for configuring the pie-shaped filter ferrite chip bead is arranged on the other , it is possible to increase the mounting density equivalent to one capacitor and pie-shaped filter is constructed sewn small by using both sides of the circuit board.

【0006】 [0006]

【実施例】以下、本発明の実施例について説明する。 EXAMPLES Hereinafter, Examples of the present invention will be described. 図1は、2つのコンデンサ素子が内蔵されたチップコンデンサの各グリーンシートを示した図、図2はその外観斜視図、図3はその等価回路図である。 Figure 1 is a diagram of two capacitor elements showed the green sheets of the built-in chip capacitors, Fig. 2 is its perspective view, FIG. 3 is an equivalent circuit diagram. ここでは図示の4 4 shown in the drawings
枚のグリーンシート1〜4が用意される。 Like green sheet 1 to 4 are prepared for. それらのグリーンシート1〜4はポリエステルのベースシートに誘電体スラリーをドクターブレード法により印刷し乾燥することにより形成される。 These green sheets 1 to 4 are formed by drying printed by a doctor blade method a dielectric slurry on the base sheet of the polyester. ここで用いた誘電体材料は、P The dielectric material used here, P
bO,La 23 ,ZrO 2 ,TiO 2を湿式混合し、 bO, La 2 O 3, a ZrO 2, TiO 2 were wet-mixed,
1150℃で2時間焼成後湿式ミルで粉砕した平均粒径0.1μmの粉体であり、Pb 0.88 La 0.12 Zr 0.7 The average particle diameter 0.1μm of the powder was ground by a wet mill after 2 hours calcination at 1150 ℃, Pb 0.88 La 0.12 Zr 0.7 T
0.30.08の組成を有するものである。 and it has a composition of i 0.3 O 0.08.

【0007】それら4枚のグリーンシート1〜4のうち、グリーンシート2,3には、誘電体を印刷乾燥した後、さらに、それぞれ図示の形状となるように、導電性ペーストをドクターブレード法により印刷、乾燥し、これにより内部電極5,6a,6bが形成される。 [0007] Of these four green sheets 1-4, the green sheet 2, after printing and drying the dielectric, further, so that each the illustrated shape, the conductive paste by a doctor blade method printing, drying, and thereby the internal electrodes 5, 6a, 6b are formed. これらの内部電極5,6a,6bのうち誘電体を挟む内部電極5,6aのペア、内部電極5,6bのペアにより、それぞれ、図3に示す等価回路中のコンデンサ素子10,1 These internal electrodes 5, 6a, the internal electrode 5, 6a of the pair of sandwiching the dielectric of 6b, the pair of internal electrodes 5,6B, respectively, a capacitor element in the equivalent circuit shown in FIG. 3 10,1
1が構成される。 1 is configured.

【0008】以上のようにして形成された4枚のグリーンシート1〜4が互いに積層され、熱圧着により一体化された後、1300℃で1時間焼成され、焼結体が得られる。 [0008] are stacked above the four green sheets 1 to 4 are formed to each other, after being integrated by thermocompression bonding, is calcined for 1 hour at 1300 ° C., the sintered body is obtained. その焼結体をバレル研磨してその焼結体の側面から内部電極5,6a,6bを露出させ、それら内部電極5,6a,6bが露出した部分にAgを主成分とした導電性ペーストを塗布し、これにより、図2に示すように内部電極6a,6bとそれぞれ接続された電極7,8および内部電極5と接続された電極9a,9bを形成する。 As the sintered body by barrel polishing the sintered body of the internal from the side electrode 5, 6a, 6b to expose the, their internal electrodes 5, 6a, 6b a conductive paste mainly composed of Ag on the exposed portion coated, thereby, the internal electrodes 6a as shown in FIG. 2, 6b respectively connected electrodes 7,8 and the internal electrode 5 and the connected electrodes 9a, form a 9b. これにより、コンデンサ素子が2素子内蔵された図2に示す形状のチップコンデンサが完成する。 Thus, a chip capacitor having the shape shown in FIG. 2 where the capacitor element is built 2 element is completed.

【0009】図4は、フェライトチップビーズの各グリーンシートを示した図、図5はその外観斜視図、図6はその等価回路図である。 [0009] Figure 4 is a ferrite chip diagram showing respective green sheets of the bead, FIG. 5 is the perspective view, FIG. 6 is an equivalent circuit diagram. ここでは図示の3枚のグリーンシート21〜23が用意される。 Here, three green sheets 21 to 23 shown in the drawing is prepared is. それらのグリーンシート21〜23はポリエステルのベースシートに磁性体スラリーをドクターブレード法により印刷し乾燥することにより形成される。 These green sheets 21 to 23 is formed by drying is printed by a doctor blade method magnetic slurry to the base sheet of the polyester. ここで用いた磁性体材料は、Ni Magnetic material used in this case is, Ni
O,ZnO,CuO,Fe 23を湿式混合し、100 O, ZnO, CuO, the Fe 2 O 3 were wet-mixed, 100
0℃2時間焼成後、湿式ミルで粉砕した平均粒径0.1 After calcination 0 ° C. 2 h, the average particle size of 0.1 was ground by a wet mill
μmの粉体であり、Ni 0.14 Zn 0. 22 Cu 0.06 Fe 0.96 μm is the powder, Ni 0.14 Zn 0. 22 Cu 0.06 Fe 0.96
1.88の組成を有するものである。 And it has a composition of O 1.88.

【0010】それら4枚のグリーンシート21〜23のうち、グリーンシート22には、磁性体を印刷、乾燥した後、さらに図示の形状となるように、導電性ペーストをドクターブレード法により印刷、乾燥し、これにより内部電極24が形成される。 [0010] Of these four green sheets 21 to 23, the green sheet 22 printing, magnetic material, dried, as further be illustrated shape, the conductive paste by a doctor blade method, dried and, which internal electrode 24 is formed. この内部電極24はその周囲が磁性体で囲まれ、図6に等価回路とに示すインダクタ素子27を構成する。 The internal electrode 24 has its periphery surrounded by a magnetic material, constituting the inductor element 27 shown in the equivalent circuit in FIG.

【0011】以上のようにして形成された3枚のグリーンシート21〜23が互いに積層され、熱圧着により一体化された後、870℃2時間焼成され、焼結体が得られる。 [0011] are stacked above the three green sheets 21 to 23 are formed with each other, after being integrated by thermocompression bonding, calcined 870 ° C. 2 hours, the sintered body is obtained. その焼結体をバレル研磨してその焼結体の側面から内部電極24を露出させ、内部電極24が露出した部分にAgを主成分とした導電性ペーストを塗布し、これにより、図5に示すように、内部電極5と接続された電極25,26を形成する。 As the sintered body by barrel polishing to expose the internal electrode 24 from the side surface of the sintered body, a conductive paste mainly composed of Ag in a portion inside the electrode 24 is exposed is coated, thereby, in FIG. 5 as shown, to form electrodes 25 and 26 connected to the internal electrode 5. これにより、インダクタ素子が内蔵された図5に示す形状のフェライトチップビーズが完成する。 Thus, ferrite chip bead shape shown in FIG. 5 where the inductor elements are built are completed.

【0012】図7〜図9は、回路基板上にチップコンデンサ100とフェライトチッップビーズを配置した状態を示す、それぞれ、平面図、側面図、裏面図である。 [0012] Figures 7-9 illustrate a state of arranging the chip capacitor 100 and the ferrite chip-up beads on a circuit board, respectively, a plan view, a side view, a rear view. 回路基板30の表面30Aには図示の形状の信号用導体パターン31a,31bが形成され、裏面30Bには、図示の形状の、信号用導体パターン32a,32b、およびグランド用導体パターン33a,33bが形成されている。 Signal conductor pattern 31a of the shape shown on the surface 30A of the circuit board 30, 31b is formed on the back surface 30B, the shapes of the illustrations, the signal conductor patterns 32a, 32b, and the ground conductor pattern 33a, 33b is It is formed. 表面30Aの各信号用導体パターン31a,31 Each signal conductor pattern 31a on the surface 30A, 31
bと裏面30Bの各信号用導体パターン32a,33b Each signal conductor patterns 32a and b and back 30B, 33b
は、回路基板30に穿設された各スルーホール34a, , Each through-hole 34a bored in the circuit board 30,
34b内に充填された導体により、互いに接続されている。 The conductor filled in the 34b, are connected to each other. 回路基板30の表面30Aには、2つの信号用導体パターン32a,32bに跨がるようにフェライトチップビーズ200が配置され、各電極25,26と各信号用導体パターン32a,32bがそれぞれ半田接続されている。 On the surface 30A of the circuit board 30, the two signal conductor pattern 32a, 32b ferrite chip bead 200 is disposed so as to extend over the respective electrodes 25 and 26 and the respective signal conductor patterns 32a, 32b are soldered respectively It is. また回路基板30の裏面30Bには、2つの信号用パターン32a,32bと2つのグランド用導体パターン33a,33bに跨がるように2素子チップコンデンサ100が配置され、各電極7,8が各信号用導体パターン32a,32bにそれぞれ半田接続されるとともに、各電極9a,9bが各グランド用導体パターン3 On the rear surface 30B of the circuit board 30 also two signal patterns 32a, 32b and two ground conductor patterns 33a, 33b astride two device chip capacitors 100 are arranged, each electrode 7 and 8 each signal conductor pattern 32a, while being respectively soldered to 32b, each electrode 9a, 9b is conductive pattern 3 for each of the ground
3a,33bにそれぞれ半田接続されている。 3a, are respectively soldered to 33b.

【0013】図10は、図7〜図9に示すように接続されたチップコンデンサ100とフェライトチップビーズ200の等価回路図である。 [0013] Figure 10 is an equivalent circuit diagram of the chip capacitor 100 and the ferrite chip bead 200 connected as shown in FIGS. 7-9. チップコンデンサ100に内蔵された2つのコンデンサ素子10,11どうしの間に、フェライトチップビーズ200に内蔵されたインダクタ素子27が配置され、全体としてパイ形フィルタ回路が形成されている。 During and if the chip of two built in the capacitor 100 capacitor elements 10 and 11, an inductor element 27 incorporated in the ferrite chip bead 200 is arranged, pie-shaped filter circuit is formed as a whole.

【0014】この実施例に示すように、回路基板30の表面30Aと裏面30Bの対応する位置に、フェライトチップビーズ200とチップコンデンサ100を配置してスルーホール34a,34bで互いに接続したため、 [0014] As shown in this embodiment, the corresponding position of the surface 30A and rear surface 30B of the circuit board 30, a ferrite chip bead 200 and the chip through hole 34a by disposing the capacitor 100, since connected to each other at 34b,
コンデンサ2個とフェライトビーズ1個の3素子を回路基板に配置する場合と比べ、コンデンサ1個分の実装スペースが不要であると共に、回路基板の表裏を利用しコンパクトにまとまったパイ形フィルタが形成される。 Compared with the case of placing two capacitors and ferrite bead one 3 element to the circuit board, with mounting space for one piece capacitors are not necessary, pie-shaped filter together compactly by utilizing the front and back of the circuit board is formed It is.

【0015】 [0015]

【発明の効果】以上説明したように、本発明によれば、 As described in the foregoing, according to the present invention,
実装密度の高いパイ形フィルタが構成される。 High packing density pie-shaped filter is formed.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】図1は、2つのコンデンサ素子が内蔵されたチップコンデンサの各グリーンシートを示した図である。 FIG. 1 is a diagram showing respective green sheets of the chip capacitor in which two capacitor elements are built.

【図2】チップコンデンサの外観斜視図である。 2 is an external perspective view of the chip capacitor.

【図3】チップコンデンサの等価回路図である。 3 is an equivalent circuit diagram of the chip capacitor.

【図4】フェライトチップビーズの各グリーンシートを示した図である。 FIG. 4 is a diagram showing the green sheets of the ferrite chip beads.

【図5】フェライトチップビーズの外観斜視図である。 5 is a perspective view of a ferrite chip bead.

【図6】フェライトチップビーズの等価回路図である。 FIG. 6 is an equivalent circuit diagram of the ferrite chip beads.

【図7】回路基板上にチップコンデンサとフェライトチッップビーズを配置した状態を示す平面図である。 7 is a plan view showing a state of arranging the chip capacitor and the ferrite chip-up beads on a circuit board.

【図8】回路基板上にチップコンデンサとフェライトチッップビーズを配置した状態を示す側面図である。 8 is a side view showing a state of arranging the chip capacitor and the ferrite chip-up beads on a circuit board.

【図9】回路基板上にチップコンデンサとフェライトチッップビーズを配置した状態を示す裏面図である。 9 is a rear view showing a state of arranging the chip capacitor and the ferrite chip-up beads on a circuit board.

【図10】図7〜図9に示すように接続されたチップコンデンサとフェライトチップビーズの等価回路図である。 FIG. 10 is an equivalent circuit diagram of the connected chip capacitor and the ferrite chip bead as shown in FIGS. 7-9.

【符号の説明】 DESCRIPTION OF SYMBOLS

1,2,3,4,21,22,23 グリーンシート 5,6a,6b,24 内部電極 7,8,9a,9b,25,26 電極 10,11 コンデンサ素子 27 インダクタ素子 30 回路基板 30A 回路基板の表面 30B 回路基板の裏面 31a,31b,32a,32b 信号用導体パターン 33a,33b グランド用導体パターン 34a,34b スルーホール 100 チップコンデンサ 200 フェライトチップビーズ 1,2,3,4,21,22,23 green sheets 5, 6a, 6b, 24 internal electrodes 7,8,9a, 9b, 25,26 electrodes 10 and 11 the capacitor element 27 inductor 30 circuit board 30A circuit board surface 30B circuit board of the back surface 31a, 31b, 32a, 32b signal conductor patterns 33a, 33b ground conductor patterns 34a, 34b through hole 100 chip capacitors 200 ferrite chip bead

Claims (1)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 回路基板と、 前記回路基板の一面に搭載された、複数のコンデンサ素子を内蔵してなるチップコンデンサと、 前記回路基板の他面に搭載された、該回路基板のスルーホールを介して前記チップコンデンサと接続され前記複数のコンデンサ素子と共にパイ形フィルタ回路を形成してなるインダクタを内蔵したフェライトチップビーズとを備えたことを特徴とするパイ形フィルタ。 1. A circuit board, mounted on one surface of the circuit board, a chip capacitor formed by a plurality of built-in capacitor element, wherein mounted on the other surface of the circuit board, the through holes of the circuit board pie-shaped filter, characterized in that a ferrite chip bead which incorporates the inductor is connected to the chip capacitor by forming a pie-shaped filter circuit together with said plurality of capacitor elements through.
JP2812694A 1994-02-25 1994-02-25 Pie filter Withdrawn JPH07240651A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2812694A JPH07240651A (en) 1994-02-25 1994-02-25 Pie filter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2812694A JPH07240651A (en) 1994-02-25 1994-02-25 Pie filter

Publications (1)

Publication Number Publication Date
JPH07240651A true JPH07240651A (en) 1995-09-12

Family

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JP2812694A Withdrawn JPH07240651A (en) 1994-02-25 1994-02-25 Pie filter

Country Status (1)

Country Link
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US6373673B1 (en) 1997-04-08 2002-04-16 X2Y Attenuators, Llc Multi-functional energy conditioner
US6498710B1 (en) 1997-04-08 2002-12-24 X2Y Attenuators, Llc Paired multi-layered dielectric independent passive component architecture resulting in differential and common mode filtering with surge protection in one integrated package
US6509807B1 (en) * 1997-04-08 2003-01-21 X2Y Attenuators, Llc Energy conditioning circuit assembly
US6580595B2 (en) 1997-04-08 2003-06-17 X2Y Attenuators, Llc Predetermined symmetrically balanced amalgam with complementary paired portions comprising shielding electrodes and shielded electrodes and other predetermined element portions for symmetrically balanced and complementary energy portion conditioning
US6603646B2 (en) 1997-04-08 2003-08-05 X2Y Attenuators, Llc Multi-functional energy conditioner
JP2003530056A (en) * 2000-03-30 2003-10-07 ヴァレオ システム デシュヤージュ The apparatus of filtering and interference suppression for the motor
US6636406B1 (en) 1997-04-08 2003-10-21 X2Y Attenuators, Llc Universal multi-functional common conductive shield structure for electrical circuitry and energy conditioning
US6650525B2 (en) 1997-04-08 2003-11-18 X2Y Attenuators, Llc Component carrier
US6687108B1 (en) 1997-04-08 2004-02-03 X2Y Attenuators, Llc Passive electrostatic shielding structure for electrical circuitry and energy conditioning with outer partial shielded energy pathways
US6738249B1 (en) 1997-04-08 2004-05-18 X2Y Attenuators, Llc Universal energy conditioning interposer with circuit architecture
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US6331926B1 (en) 1997-04-08 2001-12-18 Anthony A. Anthony Paired multi-layered dielectric independent passive component architecture resulting in differential and common mode filtering with surge protection in one integrated package
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