JPH04162428A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH04162428A JPH04162428A JP28612990A JP28612990A JPH04162428A JP H04162428 A JPH04162428 A JP H04162428A JP 28612990 A JP28612990 A JP 28612990A JP 28612990 A JP28612990 A JP 28612990A JP H04162428 A JPH04162428 A JP H04162428A
- Authority
- JP
- Japan
- Prior art keywords
- film
- thickness
- wiring
- wirings
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims abstract description 9
- 239000002994 raw material Substances 0.000 claims abstract description 9
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 9
- 239000010703 silicon Substances 0.000 claims abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 8
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910000077 silane Inorganic materials 0.000 claims abstract description 5
- 229910052782 aluminium Inorganic materials 0.000 abstract description 19
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 19
- 239000007789 gas Substances 0.000 abstract description 14
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 abstract description 13
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 abstract description 12
- 238000002161 passivation Methods 0.000 abstract description 9
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 6
- 238000006243 chemical reaction Methods 0.000 abstract description 5
- 239000001272 nitrous oxide Substances 0.000 abstract description 4
- 229910021529 ammonia Inorganic materials 0.000 abstract description 3
- 229910000069 nitrogen hydride Inorganic materials 0.000 abstract description 3
- LFQCEHFDDXELDD-UHFFFAOYSA-N tetramethyl orthosilicate Chemical compound CO[Si](OC)(OC)OC LFQCEHFDDXELDD-UHFFFAOYSA-N 0.000 abstract description 3
- 230000006866 deterioration Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 239000011229 interlayer Substances 0.000 description 10
- 239000010410 layer Substances 0.000 description 7
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 5
- 229910052681 coesite Inorganic materials 0.000 description 4
- 229910052906 cristobalite Inorganic materials 0.000 description 4
- 229910052682 stishovite Inorganic materials 0.000 description 4
- 229910052905 tridymite Inorganic materials 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 1
- 238000001157 Fourier transform infrared spectrum Methods 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000002329 infrared spectrum Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000035699 permeability Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 150000003377 silicon compounds Chemical class 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特にパッシベー
ション膜また層間絶縁膜の形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming a passivation film or an interlayer insulating film.
従来、半導体装置のパッシベーション膜としては、リン
ガラス膜（ＰＳＧ膜）上にプラズマＣＶＤ法１
＋＋＋により成長したシリコン窒化膜（プラズ
マＳｉＮ膜）の２層構造の膜が用いられてきた。しかし
、この構造のパッシベーション膜では、高温熱処理によ
りＡ℃配線にボイドが発生し、微細な配線を有する近年
のＬＳＩには適さないことがわかってきた。そこで、こ
の構造の膜の代りにプラズマＣＶＤ法により成膜したシ
リコンオキシナイトライド膜（ＳｉＯｘ膜）を単層で用
いる方法が実施されている。５ｉＯＮ膜の成長方法は、
Ｓ ｉＨ４，Ｎ２０゜ＮＨ３を原料ガスとして用い、平
行平板電極間でか少ないため、下層のＡｊ２配線にボイ
Ｆが発生することもない。Conventionally, as a passivation film for semiconductor devices, plasma CVD method 1 was applied on a phosphorus glass film (PSG film).
A two-layer structure film of silicon nitride film (plasma SiN film) grown by +++ has been used. However, in the passivation film having this structure, voids are generated in the A.degree. C. wiring due to high-temperature heat treatment, and it has been found that the passivation film is not suitable for recent LSIs having fine wiring. Therefore, instead of a film having this structure, a method has been implemented in which a single layer of silicon oxynitride film (SiOx film) formed by plasma CVD is used. The growth method of 5iON film is as follows.
Since SiH4,N20°NH3 is used as the raw material gas and the amount is only small between the parallel plate electrodes, no void F is generated in the Aj2 wiring in the lower layer.
また、配線の微細化に伴ない平坦性が要求される層間絶
縁膜の形成方法としては、プラズマＣＶＤ法により形成
したシリコン酸化膜（プラズマＳ ｉ Ｏ２膜）上にシ
リコン化合物のアルコール溶液を塗布し、焼成すること
により形成した絶縁膜（ＳＯＧ膜）の」−に、再びプラ
ズマ酸化膜を成長する方法が一般的に用いられている。In addition, as a method for forming an interlayer insulating film that requires flatness as wiring becomes finer, an alcohol solution of a silicon compound is applied onto a silicon oxide film (plasma SiO2 film) formed by plasma CVD. Generally, a method is used in which a plasma oxide film is grown again on an insulating film (SOG film) formed by baking.
また、よりカバレジの良いプラズマＣＶＤ膜としてテト
ラエトキシシラン（ＴＥ０１）を原料としたシリコン酸
化膜（Ｔ Ｅ ＯＳ Ｓ １０２膜）を上下のプラズ
マ酸化膜として用いる方法も行われている。Furthermore, as a plasma CVD film with better coverage, a method is also used in which silicon oxide films (TEOS S 102 films) made from tetraethoxysilane (TE01) are used as the upper and lower plasma oxide films.
しかし、上述した従来の絶縁膜の成膜方法のうち、８１
ＯＮ膜をパッシベション膜として用いる場合は、下層の
′配線がより微細化し、配線間隔が狭くなってくるにつ
れ、配線側壁部の５ｉＯＮ膜の厚さが薄くなり、耐湿性
が劣化してしまうという問題点がある。However, among the conventional insulating film forming methods mentioned above, 81
When using an ON film as a passivation film, there is a problem that as the underlying wiring becomes finer and the spacing between the wiring becomes narrower, the thickness of the 5iON film on the side wall of the wiring becomes thinner and the moisture resistance deteriorates. There is a point.
またＳＯＧ膜上にプラズマ酸化膜（ＳｉＯ２）を形成す
る層間絶縁膜の形成方法では、ＳＯＧ膜が吸湿性を持つ
ため、上層配線金属としてＡβをスパッタ法により成膜
する際、下層配線との接続孔の側面に露出したＳＯＧ膜
から、アウトガス（水分）が発生して下層配線表面を酸
化し、接続孔部における配線の導通不良を引き起こしや
すいという問題点がある。開孔部のＳＯＧ膜が露出しな
いようにあらかじめエッチバックを行ったとしても、界
面を通してガスが放出され同様の不良が起きるため、塗
布−焼成後のＳＯＧ膜が大気中の水分を吸わない様に真
空中あるいは乾燥窒素中で保持する必要がある。In addition, in the interlayer insulating film formation method in which a plasma oxide film (SiO2) is formed on the SOG film, since the SOG film has hygroscopic properties, when Aβ is formed as the upper layer wiring metal by sputtering, it is difficult to connect to the lower layer wiring. There is a problem in that outgas (moisture) is generated from the SOG film exposed on the side surface of the hole, oxidizes the surface of the lower wiring, and tends to cause poor conduction of the wiring in the connection hole. Even if etchback is performed in advance to prevent the SOG film from being exposed in the openings, gas is released through the interface and similar defects occur. Must be kept under vacuum or dry nitrogen.
別の対策としては、上層のプラズマ５ｉ０２膜を比較的
多孔質の膜質とし、これを成膜した後熱処理を行い、Ｓ
ＯＧ膜中の水分を上層のプラズマ５１０２膜を通して逃
がしてやる方法がある。しかしプラズマＴＥＯ８Ｓ ｉ
０２膜ではそのような多孔質な膜質を得ようとすると
、膜中に５ｉ−ＯＨ結合を含む膜となってしまう。この
ような膜は、それ自身吸湿性を持つため、従来と同様の
導通不良や配線の腐食、さらにはＴＥ０１−３ｉ○２膜
自身のクラックの発生などを引き起こしやすいという欠
点がある。Another countermeasure is to make the upper plasma 5i02 film relatively porous, and then heat-treat it after it is formed.
There is a method in which the moisture in the OG film is allowed to escape through the upper plasma 5102 film. However, plasma TEO8S i
If an attempt is made to obtain such porous film quality in the 02 film, the film will end up containing 5i-OH bonds in the film. Since such a film itself has hygroscopic properties, it has the disadvantage of easily causing poor conduction, corrosion of wiring, and cracks in the TE01-3i○2 film itself, as in the conventional case.
本発明の半導体装置の製造方法は、半導体装置の絶縁膜
として、有機シランガスを原料に使ったプラズマＣＶＤ
法によりシリコンオキシナイトライド膜を形成するもの
である。The method for manufacturing a semiconductor device of the present invention is a plasma CVD method using an organic silane gas as a raw material to form an insulating film of a semiconductor device.
A silicon oxynitride film is formed by this method.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の第１の実施例を説明するための半導体
チップの断面図であり、本発明をパッシベーション膜に
適用した場合である。また第２図は実施例で用いたプラ
ズマＣＶＤ装置であり、反応室８内には加熱源１０上に
置かれた電極を兼ねる基板台１５と、これに対向して電
極板１３が設けられている。これら電極板には高周波電
源９が接続されており、反応室８は排出口１１を介して
真空ポンプ１２により真空になるように構成されている
。また、反応ガスは電極板１３の中央部のガス供給口１
４より供給される。FIG. 1 is a cross-sectional view of a semiconductor chip for explaining a first embodiment of the present invention, in which the present invention is applied to a passivation film. Further, FIG. 2 shows the plasma CVD apparatus used in the example, in which a substrate table 15 which also serves as an electrode placed on a heating source 10 is provided in the reaction chamber 8, and an electrode plate 13 is provided opposite to this. There is. A high frequency power source 9 is connected to these electrode plates, and the reaction chamber 8 is evacuated by a vacuum pump 12 via an outlet 11. In addition, the reaction gas is supplied to the gas supply port 1 in the center of the electrode plate 13.
Supplied from 4.
まずシリコン基板１に素子形成したのち、ＰＳＧ膜２を
介して幅１０μｍ２間隔０８〜１．４μｍのアルミ配線
３を形成する。このシリコン基板１を第２図に示したプ
ラズマＣＶＤ装置の基板台１５上にセットしたのち、電
極板１３に１３．６ＭＨｚ。First, elements are formed on a silicon substrate 1, and then aluminum interconnections 3 with a width of 10 μm and an interval of 08 to 1.4 μm are formed via a PSG film 2. After this silicon substrate 1 was set on the substrate stand 15 of the plasma CVD apparatus shown in FIG. 2, the electrode plate 13 was heated at 13.6 MHz.
５００Ｗ、基板台１５に２００ＫＨｚ、５００Ｗの電力
を与え、原料ガスとしてテトラメトキシシラン（ＴＭ０
１）６０ＳＣＣＭ、亜酸化窒素（Ｎ２０）１、 ＯＳ
ＬＭ、アンモニア（ＮＨ３）２．Ｏ８ＬＭをガス供給口
１４より反応室８内に流し、基板温度３００℃、 ２．
０Ｔｏｒｒのガス圧下でアルミ配線３上に厚さ約１．０
μｍの５ｉＯＮ膜４を形成した。A power of 500 W and 200 KHz was applied to the substrate table 15, and tetramethoxysilane (TM0
1) 60SCCM, nitrous oxide (N20) 1, OS
LM, ammonia (NH3)2. 2. Flow O8LM into the reaction chamber 8 from the gas supply port 14, and set the substrate temperature to 300°C.
Approximately 1.0 mm thick on aluminum wiring 3 under 0 Torr gas pressure.
A 5iON film 4 having a thickness of μm was formed.
このようにして得られた５ｉＯＮ膜４は、ステップカバ
レッジが良好で、アルミ配線３の間隔が狭くなっても゛
、アルミ配線側壁部の膜厚もあまり薄くなることはなく
、耐湿性に優れたパッシベーション膜を形成することが
できた。また、５ＩＨ４，Ｎ２０及びＮＨ’３の原料ガ
スで５ｉＯＮ膜を形成する従来例では、５ｉＯＮ膜を厚
く堆積するとアルミ配線間に空洞が形成されたが、本実
施例では空洞の発生は全くみられなかった。The 5iON film 4 obtained in this way has good step coverage, and even if the interval between the aluminum wiring lines 3 becomes narrow, the film thickness on the side wall of the aluminum wiring does not become too thin, and it has excellent moisture resistance. A passivation film could be formed. In addition, in the conventional example in which a 5iON film is formed using raw material gases of 5IH4, N20, and NH'3, cavities were formed between the aluminum wirings when the 5iON film was deposited thickly, but in this example, no cavities were observed. There wasn't.
第３図はアルミ配線間隔と、アルミ配線３表面及び側面
の５ｉＯＮ膜４の厚さの比ｂ／ａとの関係を示した図で
ある。アルミ配線間隔が１．０μｍの場合、Ｓ ｉＨｔ
を用いる従来例ではアルミ配線側面の５ｉＯＮ膜の厚さ
は表面の厚さに対し約５０％であったが、本実施例によ
れば８０％の厚さが得られている。FIG. 3 is a diagram showing the relationship between the aluminum wiring interval and the ratio b/a of the thickness of the 5iON film 4 on the surface and side surface of the aluminum wiring 3. When the aluminum wiring spacing is 1.0 μm, SiHt
In the conventional example using aluminum wiring, the thickness of the 5iON film on the side surface of the aluminum wiring was about 50% of the surface thickness, but according to this embodiment, the thickness was 80%.
また第３図に示したのと同一の試料を１２５℃２気圧の
条件でプレッシャークッカーテス） （ＰＣＴ）を行
ない、アルミ配線の腐食が始まる時間（故障開始時間）
を調べた。その結果を第４図に示す。゛第４図から明ら
かなように、実施例ではアルミ配線間隔が狭くなっても
耐湿性が劣化しないことが分かる。In addition, the same sample shown in Figure 3 was subjected to a pressure cooker test (PCT) at 125°C and 2 atm, and the time at which aluminum wiring begins to corrode (failure start time) was measured.
I looked into it. The results are shown in FIG. As is clear from FIG. 4, it can be seen that in the example, the moisture resistance does not deteriorate even if the aluminum wiring spacing becomes narrower.
第５図は本発明の第２の実施例を説明するための半導体
チップの断面図であり、本発明を層間絶縁膜に適用した
場合である。FIG. 5 is a cross-sectional view of a semiconductor chip for explaining a second embodiment of the present invention, in which the present invention is applied to an interlayer insulating film.
まず第５図に示すように、素子が形成されたシリコン基
板１上にＳｉＯ２等の絶縁膜２Ａを介してアルミ配線３
を形成したのち層間絶縁膜として厚さ０５μｍのプラズ
マＳ １０２膜５．平坦部での厚さ０．２μｍのＳＯＧ
膜６及び厚さ０．５μｍのよい。５ｉＯＮ膜４Ａの形成
は、第１の実施例と同様に行った。すなわち、原料ガス
としてテトラエトキシシラン（ＴＥ０１）５０ＳＣＣＭ
、亜酸化窒素（Ｎ２０）１．Ｏ３ＬＭ、アンモニア（Ｎ
Ｈ３） ２． ＯＳ ＬＭを反応室８に流し、２．０Ｔ
ｏｒｒのガス圧で平行平板電極に５０’ＯＷの電圧を与
えることにプラズマを発生させ、基板温度３００℃でＣ
ＶＤ成長を行った。First, as shown in FIG. 5, an aluminum wiring 3 is placed on a silicon substrate 1 on which an element is formed via an insulating film 2A such as SiO2.
5. After forming a plasma S102 film with a thickness of 05 μm as an interlayer insulating film. SOG with a thickness of 0.2μm at the flat part
The film has a thickness of 6 and a thickness of 0.5 μm. The 5iON film 4A was formed in the same manner as in the first example. That is, 50 SCCM of tetraethoxysilane (TE01) was used as the raw material gas.
, nitrous oxide (N20)1. O3LM, ammonia (N
H3) 2. Flow OS LM into reaction chamber 8, 2.0T
Plasma is generated by applying a voltage of 50'OW to the parallel plate electrodes at a gas pressure of orr, and C
VD growth was performed.
こうして得られた５ｉＯＮ膜４Ａ中のＳｌ−○Ｈ結合を
ＦＴＲＩ測定により調べた結果、ＳＯＧ膜の４０％程度
であることが確認された。また成膜後４００℃３０分の
熱処理を行なうことにより、ＳＯＧ膜６中の水分が５ｉ
ＯＮ膜４Ａを通して放出されるため、層間絶縁膜に接続
孔を形成し上層配線用のアルミをスパッタ法により成膜
する際、下層のアルミ配線表面が酸化されることがない
ので良好な歩留りを得ることができる。As a result of examining the Sl-○H bond in the 5iON film 4A thus obtained by FTRI measurement, it was confirmed that it was about 40% of that in the SOG film. In addition, by performing heat treatment at 400°C for 30 minutes after film formation, moisture in the SOG film 6 is reduced to 5i.
Since it is emitted through the ON film 4A, when forming connection holes in the interlayer insulating film and depositing aluminum for upper layer wiring by sputtering, the surface of the lower aluminum wiring is not oxidized, resulting in a good yield. be able to.
このＳＯＧ膜からのガス（水分）の透過性を調べるため
、実施例及び従来例としての次の４種類の膜をそれぞれ
８１基板上と、Ｓｉ基板の」二のＳＯＧ膜（０，：２μ
ｍ）ｌに０．５ μｍの厚さに形成した。すなわち試料
Ａ：プラズマ（Ｐ） −Ｔ Ｅ ＯＳ−３ｉＯＮ膜、試
料Ｂ：プラズマ（Ｐ） −Ｔ Ｅ ＯＳ−８ｉＯ２膜、
試料Ｃ：プラズマ（Ｐ）−ＴＥ０１−８ｉＣｈ膜（多孔
質）、試料Ｄ：プラズマ（Ｐ）−８１０２膜である。In order to investigate the permeability of gas (moisture) from this SOG film, the following four types of films were prepared as examples and conventional examples, one on an 81 substrate, and the other on a Si substrate (0,:2μ).
m)l to a thickness of 0.5 μm. That is, sample A: plasma (P) -TE OS-3iON film, sample B: plasma (P) -TE OS-8iO2 film,
Sample C: Plasma (P)-TE01-8iCh film (porous), Sample D: Plasma (P)-8102 film.
８１基板上の試料膜をリファレンスにＳＯＧ膜上の試料
膜のＦＴＩＲスペクトルを測定すると、ＳＯＧ膜のＩＲ
スペクトルが得られるが、この時のＳ １−ＯＨ吸収ピ
ークの大きさを、ＳＯＧ膜単層のＩＲスペクトルにおけ
るＳ １−ＯＲピークとの比で表わし第６図に示す。第
６図に形成直後と、４００℃３０分後の結果を示すが、
試料Ｂ、Ｄでは５ｉ−ＯＨが熱処理によりあまり減って
いないのに対し、試料Ａ、Ｃではほとんど消えている。When measuring the FTIR spectrum of the sample film on the SOG film using the sample film on the 81 substrate as a reference, the IR of the SOG film is
A spectrum is obtained, and the magnitude of the S 1-OH absorption peak at this time is expressed as a ratio to the S 1-OR peak in the IR spectrum of the single layer SOG film, and is shown in FIG. Figure 6 shows the results immediately after formation and after 30 minutes at 400°C.
In Samples B and D, 5i-OH did not decrease much due to heat treatment, whereas in Samples A and C, it almost disappeared.
次に試料Ａ−Ｄの膜を含む層間絶縁膜を２層配線の層間
絶縁膜として用い、５０００個の接続孔が直列に並んだ
パターンを形成してその良品率を調べた。その結果を第
７図に示す。接続孔の径を１．０μｍ口で比較すると、
良品率１００％を達成できだのは試料Ａを含む層間絶縁
膜のみであった。Next, an interlayer insulating film containing the films of samples A to D was used as an interlayer insulating film for two-layer wiring, a pattern in which 5000 connection holes were arranged in series was formed, and the yield rate was examined. The results are shown in FIG. Comparing the diameter of the connection hole with a 1.0 μm opening,
Only the interlayer insulating film containing sample A was able to achieve a non-defective rate of 100%.
以上説明したように本発明は、有機シランを原料とした
Ｓｉ□Ｎ膜を絶縁膜として形成するため、この５ｉＯＮ
膜をパッシベーション膜として用いる場合は、配線間隔
が微細になっても配線側壁部の膜厚が薄くなることはな
く、耐湿性が劣化しないので、半導体装置の信頼性を向
上させることができる。As explained above, in the present invention, in order to form a Si□N film made of organic silane as a raw material as an insulating film, this 5iON
When the film is used as a passivation film, even if the wiring spacing becomes fine, the film thickness on the side wall of the wiring does not become thinner, and the moisture resistance does not deteriorate, so that the reliability of the semiconductor device can be improved.
また５ｉＯＮ膜をＳＯＧ膜上に形成し層間絶縁膜として
用いる場合は、後の熱処理によりＳＯＧ膜中の水分をＳ
ｉ ＯＨ膜を通して放出することができるので、接続
孔においてＳＯＧ膜からのガスを原因とする導通不良が
発生することがなくなるため、安定した高い歩留りで半
導体装置を製造することができる。また、有機シランを
原料とするため、カバレジが良く、平坦性が向上するの
で、上層配線の断線やエツチング残りを低減できるとい
う効果もある。In addition, when a 5iON film is formed on an SOG film and used as an interlayer insulating film, the moisture in the SOG film is removed by the subsequent heat treatment.
Since it can be released through the i OH film, conduction defects caused by gas from the SOG film will not occur in the connection holes, so semiconductor devices can be manufactured with a stable high yield. Furthermore, since organic silane is used as a raw material, coverage is good and flatness is improved, which has the effect of reducing disconnections and etching residues in upper layer wiring.
第１図は本発明の第１の実施例を説明するための半導体
チップの断面図、第２図は実施例に使用したプラズマＣ
ＶＤ装置の構成図、第３図及び第４図はアルミ配線間隔
と５ｉＯＮ膜厚比及び故障開始時間との関係を示す図、
第５図は本発明の第２の実施例を説明するための半導体
チップの断面図、第６図及び第７図は、評価用試料と８
１−○Ｈピーク比及び良品率との関係を示す図である。
１・・・・・・シリコン基板、２・・・・・・ＰＳＧ膜
、２Ａ・・・・・・絶縁膜、３・・・・・アルミ配線、
４，４Ａ・・・・・・Ｓｉ’ＯＮ膜、５・・・・・・プ
ラズマ５ｉＯＪ！ｉＷ：、６・・・・・・５ＯＧＩｌｕ
。
代理人 弁理士 内 原 晋FIG. 1 is a cross-sectional view of a semiconductor chip for explaining the first embodiment of the present invention, and FIG. 2 is a plasma C
The configuration diagram of the VD device, Figures 3 and 4 are diagrams showing the relationship between aluminum wiring spacing, 5iON film thickness ratio, and failure start time,
FIG. 5 is a cross-sectional view of a semiconductor chip for explaining the second embodiment of the present invention, and FIGS.
It is a figure showing the relationship between the 1-○H peak ratio and the non-defective product rate. 1... Silicon substrate, 2... PSG film, 2A... Insulating film, 3... Aluminum wiring,
4,4A...Si'ON film, 5...Plasma 5iOJ! iW:,6...5OGIlu
. Agent Patent Attorney Susumu Uchihara
Claims (1)
する半導体装置の製造方法において、前記絶縁膜は有機
シランガスを原料とするシリコンオキシナイトライド膜
であることを特徴とする半導体装置の製造方法。1. A method of manufacturing a semiconductor device in which an insulating film is formed on a semiconductor substrate by a plasma CVD method, wherein the insulating film is a silicon oxynitride film using organic silane gas as a raw material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28612990A JPH04162428A (en) | 1990-10-24 | 1990-10-24 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28612990A JPH04162428A (en) | 1990-10-24 | 1990-10-24 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04162428A true JPH04162428A (en) | 1992-06-05 |
Family
ID=17700307
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28612990A Pending JPH04162428A (en) | 1990-10-24 | 1990-10-24 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04162428A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6372668B2 (en) * | 2000-01-18 | 2002-04-16 | Advanced Micro Devices, Inc. | Method of forming silicon oxynitride films |
| JP2007324616A (en) * | 2007-07-25 | 2007-12-13 | Macronix Internatl Co Ltd | Passivation structure for flash memory and method for manufacturing the same |
| JP2015529852A (en) * | 2012-09-03 | 2015-10-08 | 東方電気グループ（宜興）Ｍａｇｉ太陽エネルギー科技有限公司 | Method for manufacturing anti-reflection coating having anti-PID effect |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01239940A (en) * | 1988-03-22 | 1989-09-25 | Seiko Epson Corp | Semiconductor device |
| JPH01260833A (en) * | 1988-04-11 | 1989-10-18 | Fujitsu Ltd | Vapor growth method of insulating film |
| JPH0439934A (en) * | 1990-06-05 | 1992-02-10 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
-
1990
- 1990-10-24 JP JP28612990A patent/JPH04162428A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01239940A (en) * | 1988-03-22 | 1989-09-25 | Seiko Epson Corp | Semiconductor device |
| JPH01260833A (en) * | 1988-04-11 | 1989-10-18 | Fujitsu Ltd | Vapor growth method of insulating film |
| JPH0439934A (en) * | 1990-06-05 | 1992-02-10 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6372668B2 (en) * | 2000-01-18 | 2002-04-16 | Advanced Micro Devices, Inc. | Method of forming silicon oxynitride films |
| JP2007324616A (en) * | 2007-07-25 | 2007-12-13 | Macronix Internatl Co Ltd | Passivation structure for flash memory and method for manufacturing the same |
| JP2015529852A (en) * | 2012-09-03 | 2015-10-08 | 東方電気グループ（宜興）Ｍａｇｉ太陽エネルギー科技有限公司 | Method for manufacturing anti-reflection coating having anti-PID effect |
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