JPH04160564A - Information processor - Google Patents

Abstract

PURPOSE:To accelerate the processing speed by starting the following scalar main storage access processing without waiting for the end detection report of the preceding main storage access processing from a vector control part in accordance with the indication from instruction information by a scalar control part. CONSTITUTION:A vector processing part 3 is provided with an instruction which starts the main storage access processing from a scalar processing part 2 even on the way of the processing of coincidence between data in a main storage part 1 and that in a buffer storage part 22 during storage of vector data to the main storage part 1. When a programmer or a compiler recognizes that scalar data related to a scalar data read instruction following a vector data storage instruction is data other than data in the vector data storage area of this preceding vector data storage instruction, the scalar data read instruction is set as the instruction, which does not wait for the completion of the processing of coincidence between the main storage and the buffer storage, to eliminate unnecessary wait without breaking the sequence of processing. Thus, the processing speed is accelerated.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an information processing device, and in particular to an information processing device having a vector processing section and a scalar processing section, in particular information processing from a preceding vector processing section to a main storage section. The present invention relates to an information processing device that can guarantee access and order of access processing from a subsequent scalar processing unit to a main storage unit.

[Conventional technology]

Conventionally, this type of information processing device consists of a main memory section, a scalar processing section, and a vector processing section. It has a buffer storage unit as a copy of the data.

Access from this scalar processing section to the main memory section is processed via the buffer memory section. In other words, when accessing the main memory from the scalar processing unit, it is first checked whether a copy of the data to be accessed is registered in the buffer storage unit, and if it is registered, this data is accessed; In some cases, by accessing the main memory, the time required to access the main memory section is apparently shortened.

Also, when accessing the main memory from the vector processing unit, the processing target is vector data, and the processing unit is - times, which is large.
As with scalar data, when data is registered in the buffer memory, much of the previously registered data is erased, which may reduce the buffer memory usage efficiency. Therefore, access from the flat file processing section to the main storage section is performed directly to the main storage section without going through the buffer storage section.

In an information processing device with such a configuration, in the process of storing data from the scalar processing unit to the main memory unit, data is stored in both the buffer memory unit and the main memory unit, so there is a gap between the main memory unit and the buffer memory unit. In the process of storing data from the processing unit to the main memory unit, the buffer memory unit is used as an intermediary in this process. Therefore, if vector data is stored in an area of the main memory that has a gap in the buffer memory, a data mismatch/match will occur between the main memory and the buffer memory in that memory area. . For example, consider a case where processing as shown in FIG. 2(a) is performed. In the process of transferring scalar data d to scalar I and sister D-1 in command 1), if the data is not registered in the buffer storage unit, the data d1. A data block B1 of a predetermined size containing d is read from the main memory and registered in the buffer memory, and at the same time the target data d]
- is transferred to the scalar register (Figure 2 (1) ))
.

Then, in instruction (2), vector data V1 is converted to the data d.
1 is stored in the area containing 1, the state shown in Figure 2 (C) occurs, and a situation occurs in which part of the contents of Cheetah block B1 (the part of vector data V) is different between the main memory and the buffer memory. arise.

In this state, if instruction (3) accesses again the scalar data d1 that was accessed in instruction <1), then the data d1
remains as valid data in the memory, and the data itself is read out, so the result of the vector data storage process of instruction (2) is no longer reflected.

Therefore, in the process of storing data directly to the main memory without going through the buffer memory, as in instruction (2), the address information at the time of storing the vector data is sent to the buffer memory, and the data is stored in the buffer memory. Among the data stored in the vector data storage area, a process is executed to invalidate the block 1 hook data that includes the data corresponding to the vector data storage area.

After executing the above invalidation process, when instruction (3) is executed, the state is similar to the state shown in the second [☆i (+)), and the target scalar data is not stored in the buffer memory. Since the data does not exist and reading starts from the main memory, it is possible to read the data stored by instruction (2).

In other words, in conventional information processing devices, when storing data from the vector processing unit to the main memory unit, the main memory unit and the buffer memory unit perform data matching processing (for example, data matching processing corresponding to the vector data storage area). It is necessary to execute invalidation processing of data in the buffer storage section), and the scalar processing section waits for access to the main storage section of t) until the matching processing is completed.

[Invention or solution L - problem to be solved]

However, in many cases, the hexadecimal data area and the scalar data area in the main memory are separated (I), and the data from the hexadecimal processing section described in 7-1 to the main memory is separated. It is rare that the scalar processing unit does not read the stored result by a subsequent instruction, and it is possible to logically determine whether or not the preceding vector storage area is to be read by a subsequent scalar instruction (from the software). However, in the above-mentioned conventional information processing apparatus, even when reading scalar data after vector data storage processing, which clearly does not require waiting, activation is continued until the matching process between the main memory and the buffer memory is completed. This had the disadvantage of causing unnecessary waiting.

[Means to solve the problem]

The information processing device of the present invention has a main memory section, a scalar processing section, and a vector processing section, and further includes a vector control section including means for detecting the end of access processing from the solid one hell processing section to the main memory section, and a vector control section that includes instruction information. and a control section that controls to start the subsequent scalar main memory access processing without waiting for the completion report of the preceding main memory access processing from the solid one hell control section.

〔Example〕

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows the configuration of an embodiment of the present invention. In FIG. 1, one embodiment of the present invention shows a main memory section 1. In an information processing apparatus including a scalar processing section 2 and a vector processing section 3, a main storage section 1 receives requests from the scalar processing section 2 and the vector processing section 3;
and a main memory control section] 2 that controls access to the memory section 11.

The scalar processing unit (SU) 2 is a processing unit that executes scalar data processing, decodes instructions, and creates control signals that control the arithmetic unit (not shown), main storage unit 1, vector processing unit 3, etc. Command processing unit 2 that changes the flow of transmission and processing
1 and a buffer memory section 22 for storing a copy of the data stored in the main memory section 1 and shortening the apparent access time to the main memory section 1.

The hexagonal processing unit (VU) 3 is a processing unit that executes processing of vector data, and has a vector register unit 31 that stores vector data.

Next, the operation of an embodiment of the present invention will be described using as an example a process in which a scalar load instruction follows a vector spread instruction (vector data instruction: abbreviated as VSC), which has the most significant effect. Here, the VSC instruction refers to an instruction for storing each element of data stored in a vector register into the main memory by using a corresponding element of data stored in another vector register as an address. First, the instruction processing unit 21■
When an SC command is detected, the controller 3 notifies the solid 1-hell processing unit 3 of the activation of SC processing, the data register number, and the address register number through the control line 100.

Upon receiving this notification, the vector processing unit 3 sends an SC request, data to be stored, and storage address to the main storage unit 1 through control lines 101. Data line 102, address line 103-
At the same time, the buffer storage section 22 in the scalar processing section 2 is also notified of the same address information through the address line 103-b. When the main memory control unit 1-2 receives the VSC request, it issues a control instruction to the memory unit 1 to store the corresponding data using the address information sent at the same time, and executes the VSC process.

On the other hand, when the buffer storage unit 22 receives the address from the address line 103-b, it uses the address to search whether data of the same address is registered in the M@ storage,
If registered, the data is invalidated. As mentioned in the prior art, this is because data in the main memory and buffer memory become inconsistent due to the data stored in the main memory by SC processing, so the buffer memory where the data before update remains The data inconsistency is resolved by invalidating the data.

During this invalidation operation, the buffer memory section 22 communicates with the instruction control section 21 through the status report line 104, and at that point, the buffer memory section 22
2 continues to notify that it is being disabled.

Next, when the instruction processing unit 21 detects a scalar load instruction as a subsequent instruction while invalidating the VSC instruction, if the instruction is a vector processing Wait, ), the instruction processing unit 21 uses the status report line 104 is monitored, and while the buffer storage unit 22 is in the process of invalidation processing, the activation of the subsequent 5LDW instruction is controlled to be suppressed, and the scalar load instruction is controlled to suppress the activation of the preceding vector data storage processing described in the claims of the present invention. Irrespective of this, the SLD NW command is activated without looking at the information on the reporting line 104.

After the instruction is activated, the 5LDW and 5LDNW operations are the same, and the instruction processing unit 21 sends the scalar load request and the address of the request to the request line respectively]05. It is sent to the buffer storage section 22 through the address line 106. When the M storage unit 22 receives the request, it searches whether the data is registered in the buffer storage unit, returns the data if it is registered, and returns the data if it is not registered. Request line to storage section]07. A request is issued by placing a scalar load request and the address of the request on the address line 1.08.

Furthermore, as a specific example in which the present invention is effective, in a case where the process handling the squirrel 1-vector processing unit is in a loop, the process of storing the result of the calculation in the process main body into the main memory unit using the vector diffusion instruction at the end is performed. After that, control variables may be loaded in order to perform calculations on loop variables, and at this time, the area in main memory that stores the calculation results of the main body of processing and the area in main memory that stores control variables are , - Since the first one is different, as shown in Figure 3, conventionally, until the last vector spreading instruction of the loop and the accompanying invalidation process of the buffer storage unit are completed, the command for controlling the next loop is not executed. Although the arithmetic processing could not be started, the present invention makes it possible to execute the loop control processing in parallel with the last vector spread instruction processing of the previous loop, thereby increasing the speed of the divided processing performed in parallel.

〔Effect of the invention〕

As explained above, in the present invention, the vector processing section
By providing an instruction to start main memory access processing from the scalar processing section, even if the data matching process between the main storage section and the N-coincidence storage section is in progress while the vector is being stored in the main memory section, the vector Regarding a scalar data read instruction following a data storage instruction, if the programmer or compiler recognizes that the scalar data is data outside the preceding vector data storage area, the scalar data read instruction is transferred to the main memory/buffer described above. By using a type of instruction that does not wait for the completion of memory matching processing, there is an effect that unnecessary waiting can be eliminated and processing can be speeded up without losing the order of processing.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing an information processing device that is an embodiment of the present invention, and FIGS. 2(a) to (c) are diagrams explaining the meaning of data matching processing between the main storage section and the buffer storage section. , Figure 3 (a>
3(b) is a diagram showing a conventional example, and FIG. 3(b) is a diagram showing an example to which an embodiment of the present invention is applied. DESCRIPTION OF SYMBOLS 1... Main memory section, 2... Scalar processing section, 3... Vector processing section, 11... Memory section, 12... Main memory control section, 21... Instruction processing section, 22...・Buffer memory unit,
31...Vector register section.

Claims (1)

[Claims] In an information processing device consisting of a main storage section, a scalar processing section, and a vector processing section, the vector control section including means for detecting the end of access processing from the vector processing section to the main storage section and the main storage section from the scalar processing section A scalar control unit that controls memory access processing is provided, and the scalar control unit executes subsequent scalar main memory access processing according to instructions from command information without waiting for a preceding main memory access processing completion detection report from the vector control unit. An information processing device characterized by controlling the information processing device to start.