JPH04160565A - Information processor - Google Patents

Abstract

PURPOSE:To increase the processing speed by controlling the wait for access to a main storage by information of a flag indicating that the main storage access processing from a following scalar processing part should be started without waiting for the end of the access processing from a preceding vector processing part to the main storage part. CONSTITUTION:A vector processing part 3 is provided with an instruction which starts the main storage access processing from a scalar processing part 2 even on the way of the processing of coincidence between data in a main storage part 1 and that in a buffer storage part 22 during storage of vector data to the main storage part 1. When a programmer or a compiler recognizes that scalar data related to a scalar data read instruction following a vector data storage instruction is data other than data in the vector data storage area of this preceding vector data storage instruction, the scalar data read instruction is set as the instruction, which does not wait for the completion of the processing of coincidence between the main storage and the buffer storage, to eliminate unnecessary wait without breaking the sequence of processing. Thus, the processing speed is increased.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an information processing device, and more particularly, to an information processing device having a vector processing section and a scalar processing section, in which access from a preceding vector processing section to a main memory section is performed. The present invention also relates to an information processing apparatus that guarantees the order of access processing from a subsequent scalar processing unit to a main storage unit.

[Conventional technology]

Conventionally, this type of information processing device consists of a main memory, a scalar processing section, and a vector processing section. It has a buffer storage section as a copy of the data in the main memory.

Access from this scalar processing section to the main memory section is processed via the buffer memory section. In other words, when accessing the main memory from the scalar processing unit, it is first checked whether a copy of the data to be accessed is registered in the buffer storage unit, and if it is registered, this data is accessed and the registered data is registered. If the main memory is not available, the main memory is accessed, thereby reducing the time it takes to access the main memory.

In addition, when accessing the main memory from the vector processing unit, the processing target is vector data, and the processing unit - times is large, so if data is registered in the buffer memory like scalar data, it will not be registered before. Since much of the previously stored data will be erased, there is a possibility that the buffer memory usage efficiency will decrease. Therefore, the vector processing section accesses the main memory directly without going through the buffer memory.

In an information processing device having such a configuration, in the process of storing data from the scalar processing unit to the main memory unit, data is stored in both the buffer memory unit and the main memory unit. However, in the process of storing data from the vector processing unit to the main memory, the buffer memory is not used in the process as described above, so the data is not copied to the buffer memory. When vector data is stored in a main storage area that has a main storage area, a data mismatch occurs between the main storage area and the buffer storage area.

For example, consider a case where processing as shown in FIG. 2(a) is performed. In the process of loading scalar data d1 to the scalar register with instruction (1), if the data is not registered in the buffer storage, a data block B1 of a predetermined size containing the data d1 is read from the main storage. , and at the same time as registering it in the buffer storage unit, transfers the target data d+ to the scalar register. (Figure 2b) Then, in command (2), vector data ■1 is transferred to the data d.
When stored in an area containing 1, the state shown in FIG. 2(C) occurs, and a part of the contents of data block B1 (the part of vector data vI) is different between the main memory and the buffer memory. .

In this state, if instruction (3) accesses again the scalar data d1 that was accessed in instruction (1), then the data d1
remains as valid data on the buffer memory, and the data itself is read out, so the result of the vector data storage process of instruction (2) is no longer reflected.

Therefore, in the process of storing data directly to the main memory without going through the buffer memory, as in instruction (2), the address information at the time of storing the vector data is sent to the buffer memory, and the data is stored in the buffer memory. Among the data contained in the vector data storage area, the processing for validating the data of the block containing the data corresponding to the vector data storage area is executed.

After executing the above invalidation process, when instruction (3) is executed, the state is similar to the state shown in FIG. 2(b),
Since the target scalar data does not exist in the buffer storage section and reading starts from the main storage section, it becomes possible to read out the data stored by instruction (2).

In other words, in conventional information processing devices, when storing data from the vector processing unit to the main memory unit, the main memory unit and the buffer memory unit perform data matching processing (for example, data matching processing corresponding to the vector data storage area). Invalidation processing of data in the buffer storage section) needs to be executed, and access to the main storage section from the scalar processing section is made to wait until the matching processing is completed.

[Problem to be solved by the invention]

However, in many cases, the area for vector data and the area for scalar data in main memory are separated, and the scalar processing unit reads the result of data storage from the preceding vector processing unit to the main memory with a subsequent instruction. Further, it is possible to logically (from software) determine whether or not the preceding vector storage area is to be read by a subsequent scalar instruction.

However, in the above-mentioned conventional information processing apparatus, even when scalar data is continuously generated after vector data storage processing, which clearly does not require waiting, activation is delayed until the matching process between the main memory and the buffer memory is completed. This had the disadvantage of causing unnecessary waiting because the user had to wait for the call to be made.

[Means to solve the problem]

The information processing device of the present invention includes a main memory, a scalar processing section,
It consists of a vector processing unit, and is set/reset by instruction information in the scalar processing unit, and the main memory from the subsequent scalar processing unit is It has a flag indicating that access processing can be started, and a control unit that controls waiting for access to the main memory based on the information of the flag.

〔Example〕

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows the configuration of an embodiment of the present invention. In FIG. 1, one embodiment of the present invention is an information processing device composed of a main memory section 1, a scalar processing section 2, and a vector processing section 3, where the main memory section 1 includes a memory section 11 for storing instructions and data. , Squash processing section 2. The main memory control section 12 receives requests from the vector processing section 3 and controls access to the memory section 11.

The scalar processing unit (SU) 2 is a processing unit that executes scalar data processing, decodes instructions, and creates control signals to control the arithmetic unit (not shown), main storage unit 1, vector processing unit 3, etc.・A buffer memory for shortening the apparent access time to the main memory 1 by holding a copy of the data stored in the command processing unit 21 and the main memory 1 to transmit or change the flow of processing. The instruction control section 21 further includes a flag register 23 that can be set/reset by an instruction.

When the flag is in the set state, the instruction control unit 21 activates the subsequent scalar load instruction without waiting for the completion of the invalidation process associated with the preceding vector data storage instruction, and sets the flag 23 in the reset state. If so, control is performed so as to wait for the completion of the invalidation process associated with the preceding vector data storage instruction and activate the subsequent scalar load instruction, as in the past.

The vector processing unit (VU) 3 is a processing unit that executes processing of vector data, and has a vector register unit 31 that stores vector data. - On the other hand, in order to control the flag register 23, the compiler or programmer determines whether or not the scalar data to be loaded is data within the data storage area by the preceding VSC (vector scatter instruction) processing.

As a result, if it is determined that the data is within the area or cannot be determined, only the scalar load instruction is directly incorporated into the instruction string. In this case, the performance is the same as before.

On the other hand, if the data area check described above determines that the scalar load data to be loaded is outside the data storage area due to the preceding VSC processing, the compiler or programmer sets the flag register 23 before the scalar load instruction. Generate an instruction sequence that incorporates the instructions to do so.

Next, the operation of this embodiment will be described using as an example a process in which a scalar load instruction follows a vector spread instruction (vector scatter instruction: abbreviated as VSC), which has the most significant effect.

Here, the vSC instruction refers to an instruction for storing each element of data stored in a vector register into the main storage section by using a corresponding element of data stored in another vector register as an address.

First, when the instruction processing section 21 detects a VSC instruction, it notifies the vector processing section 3 of the activation of the VSC processing, the data register number, and the address register number through the control line 100.

Upon receiving the notification, the vector processing unit 3 sends the vSC request, the data to be stored, and the storage address to the main storage unit 1 through the control lines 101. Data line 102, address line 10
3-a, and the same address information is also notified to the buffer storage unit 22 in the scalar processing unit 2 through the address line 103-b. When the main memory control unit 12 receives the VSC request, it issues a control instruction to the memory unit 11 to store the corresponding data using the address information sent at the same time, and executes the VSC process.

On the other hand, when the buffer storage unit 22 receives the address from the address line 103-b, it uses the address to search whether data with the same address is registered in the buffer storage,
If registered, the data is invalidated. As mentioned in the prior art section, this is because the data in the main memory and buffer memory become inconsistent due to the data stored in the main memory by SC processing, so the buffer memory where the data before update remains By invalidating the data on the other side, the inconsistency of the data is resolved.

During this invalidation operation, the buffer storage unit 22 is operated by the instruction control unit 2j-
The buffer storage unit 22 continues to be notified through the [2 status report line 104 that the buffer storage unit 22 is currently undergoing invalidation work.

Next, when the instruction processing unit 21 detects a ``J-code'' instruction in a subsequent instruction while invalidating the VSC instruction, the instruction processing unit 21 checks the flag register 23 (12) and determines that the flag is in the reset state. If so, the status report line 104 is monitored, and while the buffer storage unit 22 is in the process of invalidation, control l-7 is performed to suppress activation of the subsequent SLD instruction, and the flag register 23 is set to If the status is 1-1, the information on the status report line 104 will be sent to the corresponding S L, I
) activates the command.

After the instruction is activated, the command processing Elf1 section 21 sends the request for the request and the address of the request to the line storage section 22 through the /noest line 105 and the address line 10f3, respectively. When the buffer memory 1a fls 22 receives and pays the request, it searches whether or not the gutter is registered in the buffer memory, and if it is registered, returns 01, the data is returned, and if it is not registered, The request line 107 and the address line 108 are respectively multiplied by the swash load request and the address of the request to issue a request.

A specific example in which the present invention is effective is a case where processing that handles list vector data is in a loop, and the processing body stores the result of (1, After processing, control variables may be loaded in order to perform calculations on loop variables. Since :r rear in memory is different from 1.3 in the - shell, conventionally, as shown in FIG. The arithmetic processing for controlling the next loop could not be started until J! was completed, but with the present invention, the CC silk control processing can be executed in parallel with the last vector spread instruction processing of the previous loop. It is possible to do this, and the processing speed is increased by the amount of parallel execution.

〔Effect of the invention〕

As explained in Part 1, 4: The present invention provides a method for storing vector data in the main memory, even if data is being merged between the main memory and the buffer memory. By providing a command to start main memory access processing from the vector processor, the programmer, compiler, or Eve can use the vector processor to access data that is outside the storage area of the preceding vector processor. If it is recognized, the above-mentioned main memory e
By arranging the completion of the buffer memory matching process on evening and eve, when even samurai do not agree, unnecessary waiting can be eliminated without losing the order of the process, and the process can be speeded up. Toi・
5 effects.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an information processing device according to an embodiment of the present invention, and FIGS. 2(a) to 2(c) show data matching processing between the main memory section and the buffer memory section. 3(a,) are diagrams showing a conventional example, and FIG. 3(b) is a diagram illustrating the meaning of 19. to which an embodiment of the present invention is applied. This figure does not show an example. 1...Main memory section, 2...Scalar part ■1 part, 3...
Flat 1 - roll processing section, IJ-... memory section, 12...
The above-mentioned armpit control unit, 2J... instruction processing unit, 22... buffer storage unit, 23... flag register, 31 river vector register unit.

Claims (1)

[Claims] In an information processing device comprising a main memory, a scalar processing section, and a vector processing section, information is set/reset in the scalar processing section by instruction information, and is used to control access processing from the preceding vector processing section to the main memory. A flag indicating that it is possible to start main memory access processing from a subsequent scalar processing unit without waiting for completion, and a control unit that controls waiting for access to the main memory based on information of the flag. An information processing device characterized by: