JPH04159886A - Video signal processor - Google Patents

Abstract

PURPOSE:To display reproduced signals on a monitor screen at various tape speeds by fixing the running speed of a magnetic tape and correcting the relative speed between the running speed of the magnetic tape and the rotating speed of a cylinder at the time of quick-traversing reproduction and rewinding reproduction. CONSTITUTION:When a magnetic tape 5 is run at a high speed, signals obtained from speed detectors 13 and 14 are inputted to capstan control/driving circuit 16 to control a capstan motor 8 so that the running speed of the tape 5 can be fixed to a constant speed. In addition, the relative speed between a cylinder 2 and tape 5 is read out from a ROM 18 and compared with the signals of a speed and phase detectors 3 and 4 and the rotating speed of the cylinder 2 is controlled to obtain the same relative speed value as that of the ROM 18 by means of a cylinder control/driving circuit 15 so that the horizontal feedback period of reproduced signals can become the same as that of the normal reproduction time. Thus the relative speed between the cylinder 2 and tape 5 is corrected even when the tape 5 is run at a high speed. Therefore, the horizontal feedback period of the reproduced signals can be maintained under the same condition and picture can be reproduced normally even when the tape 5 is run at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a video signal processing device for displaying signals on the screen of a video tape recorder even when running at high speed.

[Conventional technology]

In a conventional video tape recorder, when the tape is fully loaded into a rotating cylinder and run at high speed, the vertical and horizontal frequencies of the reproduced signal change depending on the running speed of the magnetic tape and the rotational speed of the cylinder. Therefore, up to a certain tape speed, the playback signal processing section can separate the synchronization signal and display the playback signal on the screen, but beyond a certain speed, the synchronization separation cannot be performed and the screen shows a vertical or horizontal flow. occurred, and the image could not be viewed as normal.

FIG. 3 is a block diagram showing the configuration of the main parts of a conventional video tape recorder. In this figure, a rotating spatula l'l is attached to a symmetrical position on a rotating cylinder 2, and a speed detector 34 and a phase detector 4 are provided around the rotating cylinder 2 to detect its rotational speed. and magnetic tape 5
is pulled out from the tape cassette, and the running speed is controlled by the pinch roller 6 and capstan 7. 8 is a capstan motor, the rotational speed of which is detected by a speed detector 9. Further, a control head 10 is provided close to the traveling path of the magnetic tape 50. On the other hand, inside the tape cassette, there is a supply reel 11 and a take-up reel 12.
are provided, and speed detectors 13, 14 are provided on each side thereof.

The rotating cylinder 2 is controlled by a cylinder control/drive circuit 15 which controls the rotational speed of the cylinder based on signals from a speed detector 39 and a phase detector 4. The capstan motor 8 also has a speed detector 9 and a control head 10.
Its rotational speed is controlled by a signal from a speed detector 13.14 and a speed detector 13.14. The signal from the rotary head 1 is outputted to the outside via the reproducing circuit 17.

Now, in the video signal processing device of the video tape recorder configured as described above, during normal playback, the speed detector 31
The signal obtained from the phase detector 4 is applied to a cylinder control/drive circuit 15, which compares it with its internal reference speed to generate a voltage to control the cylinder 2, causing the cylinder 2 to rotate at a constant speed.

On the other hand, the speed detection signal obtained from the speed detector 9 and the regeneration control signal obtained from the controller rad 10 are given to the cab scan control/drive circuit 16, and are compared with the internal reference speed to control the capstan motor 8 and control the capstan motor 8. Rotate stun 7 at a constant speed. In this way, the magnetic tape 5 and the rotating cylinder 2 are controlled to have a constant relative speed, and the signal obtained from the rotating head 1 is transmitted to the reproducing circuit 1.
7, the signal is demodulated and output, and displayed on a television receiver.

Next, in the case of high-speed rewinding, the pinch roller 6 and capstan 7 are separated, and the capstan motor 8 is rotated to wind the magnetic tape 5 onto the take-up reel 12 at high speed. In this case, the speed detector 1 of the supply reel 11
3 and the speed detection signal obtained from the speed detector 14 of the take-up reel 12 is applied to the capstan control/drive circuit 16 to drive the capstan motor 8 so that the tape speed of the magnetic tape 5 is constant. . When fully loaded and running at high speed, the rotary cylinder 2 must be rotated or else the magnetic tape 5 will be wrapped around the cylinder 2. In this case, since images cannot be normally output to the television screen, the rotary cylinder 2 is rotated in free run.

[Problem to be solved by the invention]

However, in such conventional video tape recorders, when the magnetic tape is run at high speed, the rotating cylinder 2
When rotated at approximately the same speed as normal playback, the horizontal frequency of the playback signal changes.

At this time, similarly to special playback, if the relative speed between the rotary cylinder 2 and the magnetic tape 5 is corrected so that the horizontal frequency becomes a predetermined frequency, the vertical frequency will change. Therefore, even if the reproduced signal is directly displayed on a television receiver, a vertical or horizontal flow will occur on the screen, resulting in the problem that the reproduced signal cannot be reproduced on a normal screen.

The present invention has been made in view of the problems of conventional video signal processing devices, and is a technical endeavor to enable normal reproduction of images on the screen of a television receiver even when driving at high speed. Take it as a challenge.

[Means to solve the problem]

The invention of claim 1 of the present application provides a video signal for reproducing the video signal recorded on the magnetic tape by disposing a pair of rotary heads on a rotary cylinder for reading a video signal from a magnetic tape, and by alternately switching the rotary heads. The processing device includes a capstan control/drive means that keeps the tape running speed constant by detecting the rotational speed from the take-up reel and the supply reel during high-speed running and controlling the capstan motor, and a cylinder during high-speed running. a cylinder control/driving means for detecting the rotational speed of the rotary head and controlling the relative speed of the rotary cylinder and the magnetic tape to be the same speed as normal reproduction based on the detection signal; and a video signal reproduced by the rotary head. a first synchronization separation circuit that separates a horizontal synchronization signal from a horizontal synchronization signal; an A/D converter that converts the video signal reproduced from the rotary head into a digital video signal; a memory that holds the digital video signal; and a horizontal synchronization signal of the video signal. and a synchronization signal generation circuit that generates a vertical synchronization signal, the outputs of the first synchronization separation circuit and the synchronization signal generation circuit, and the switching signal of the rotary head. /D
A control unit that writes the digital video signal of the converter and reads the written video signal by controlling the read address of the memory based on the synchronization signal of the synchronization signal generation circuit; D to convert to analog signal
The device is characterized in that it includes a /A converter and a mixing circuit that superimposes an analog video signal converted by a D/A converter on a video synchronization signal.

Further, in the invention of claim 2 of the present application, the control section includes a first H-direction address counter that counts a predetermined clock and is reset by a horizontal synchronization signal obtained from the first horizontal synchronization signal, and a first horizontal synchronization counter. A direction counter that counts the horizontal synchronization signal obtained from the signal and is reset by the switching signal of the head, and ■ The pulse of the horizontal synchronization signal obtained from the first horizontal synchronization signal is thinned out and output based on the counted value of the direction counter. and a first circuit that counts the output of the thinning circuit.
A second H direction address counter that counts a predetermined clock and is reset by a horizontal synchronization signal output from a synchronization signal generation circuit, and a horizontal synchronization signal obtained from a second synchronization separation circuit. Count V
A second direction address counter that stops counting when the maximum count value of the direction counter is reached, and a count value of the first H direction atj/counter and the first V direction address counter when writing to memory. The present invention is characterized in that it has an address switching circuit that switches the address signal to output the counted values of the second H-direction address counter and the second {circle around (2)}-direction address counter to the memory during reading.

Furthermore, in the invention of claim 3 of the present application, the synchronization signal ordering circuit is a second synchronization separation circuit that separates the horizontal and vertical synchronization signals of the second video signal given from the outside, and the mixing circuit is a second synchronization signal ordering circuit that separates the horizontal and vertical synchronization signals of the second video signal given from the outside. It is characterized in that an analog video signal converted by a D/A converter is superimposed on the synchronization signal.

[Function] According to the present invention having such characteristics, the horizontal synchronization signal obtained as a playback signal by controlling the running speed of the tape and the rotational speed of the cylinder is normally The frequency is controlled to be the same as when playing.

Then, when writing the reproduced video signal to the memory, lines are thinned out and written to the memory, and at the time of reproduction, the video signal written to the memory is based on the address data separated by the second video signal. 2, the signal is read out from the memory, the signal is converted to an analog signal, and the signal is superimposed on the second video signal and output.

〔Example〕

FIG. 1 is a block diagram showing the configuration of a video signal processing device according to an embodiment of the present invention. In this figure, the same parts as those in the conventional example described above are given the same reference numerals, and detailed explanation will be omitted. In this embodiment as well, the rotary head l is attached to a symmetrical position of the rotary cylinder 2, and the magnetic tape 5 pulled out from the tape cassette is wound around it and runs at a constant speed, and at the same time the rotary cylinder 2 is rotated. By this means, signals are written from or reproduced from the rotary head l. In this embodiment as well, the rotational speed of the rotary cylinder 2 is controlled by the cylinder control/drive circuit 15, and the capstan motor 8 is controlled by the cab scan control/drive circuit 16.

The capstan motor 8 is connected to the reel 1 together with the capstan 7.
1 and 12 to rotate.

In this embodiment, a one-way only memory 18 (ROM) is connected to the cylinder control/drive circuit 15 for holding a reference value for correcting the relative speed. Further, the reproduced signal obtained from the reproducing circuit 17 is sent to the first synchronization separation circuit 19. The signal is applied to an A/D converter 20 and a signal switching circuit 21. The synchronization separation circuit 19 separates the horizontal synchronization signal of the reproduced signal,
The output is given to the control section 22. The reproduction circuit 17 is 2
A switching signal for switching the outputs of the two rotary heads 1 is given to the control section 22 as a vertical reference signal (2). This video signal processing device also has an input terminal 23 to which a second video signal is applied from a tuner or the like. The input terminal 23 is connected to the input terminals of a second synchronous separation circuit 24 and a mixing circuit 25. The synchronization separation circuit 24 separates the horizontal and vertical synchronization signals of the second video signal, and its output is given to the control section 22. Further, the A/D converter 20 converts the reproduction signal obtained from the reproduction circuit 17 into a digital signal, and its output is given to the memory 26 via the control section 22. The memory 26 stores the digital signal obtained from the A/D converter 20 according to the control pulse given from the control section 22, or reads out the signal and supplies it to the D/A converter 27 via the control section 22. . The D/A converter 27 converts this signal into an analog signal and supplies it to the mixing circuit 25.

The mixing circuit 25 superimposes the video signal obtained from the D/A converter 27 on the synchronization signal of the second video signal, thereby providing the signal to the signal switching circuit 21 as a composite video signal. The signal switching circuit 21 outputs a reproduction signal to a monitor (not shown) by switching the signals of the reproduction circuit 17 and the mixing circuit 25.

FIG. 2 is a block diagram showing the detailed configuration of the control section 22. As shown in FIG. In this figure, the clock generator 31 is connected to the horizontal synchronization signal H separated from the synchronization separation circuit 19 and to the regeneration circuit 17.
Rotating head switching signal (vertical synchronization signal) given by
), and based on these signals, generates pulses (RAS, CAS, DT, WE, etc.) that control the memory 26, and also outputs a clock signal and horizontal synchronization signal that operate the address counter. The first H-direction address counter 32 counts clocks at a frequency corresponding to the sampling number of one horizontal scanning line held in the memory 26, for example, 13°5 MHz or 14.3 MHz, and the first H-direction address counter 32 counts clocks at a frequency corresponding to the sampling number of one horizontal scanning line held in the memory 26. The output is given to the data 7-der 33 and address conversion circuit 34. (2) The direction counter 35 is a counter that counts horizontal synchronizing signals and is reset by a -rad switching signal. The frequency of this reset signal is 60Hz during normal playback, but because the relative speed with the tape is corrected, it may be higher than this during fast forward playback, for example 9Hz.
5Hz, and lower than this during rewind playback, for example 2Hz.
47. ■The output of the direction counter 35 is the thinning circuit 3
6 and the read system clock generator 1 noter 37. The thinning circuit 36 thins out the pulses of the 15.75 KHz source clock signal based on the count value of the direction counter 35 and supplies the pulses to the first direction address counter 38. Decide the thinning position. - The direction address counter 38 is a write-side counter that counts the clock from the thinning circuit 36 and generates a vertical address for the memory 26, and its output is sent to the decoder 33 and the address switching circuit 3.
given to 4. The decoder 33 generates a clamp pulse that eliminates burst signals from the input signal of the A/D converter,
It generates a signal for clamping the input signal.

On the other hand, the read system clock generator 37 inputs the horizontal and vertical synchronization signals of the second video signal outputted from the synchronization separation circuit 24, the source clock, and the count output of the direction counter 35, and receives pulses (SC, SOE) for controlling the memory. etc)
It also generates an 11-direction address counter 39. ■Clock signal for operating the direction address counter 40.

Generates horizontal synchronization signal. H direction address counter 39
is a counter that counts clocks with a frequency corresponding to the number of samples of one horizontal scanning line and is reset by a horizontal synchronizing signal, and its output is given to the address switching circuit 34 and the decoder 41. A direction address counter 40 counts horizontal synchronizing signals and outputs a vertical address of the memory 26, and its output is given to an address switching circuit 34 and a decoder 41.

The decoder 41 generates pulses for switching between the output signal from the memory 26 and the second video input signal, and crank pulses for making these signals have the same potential. Further, the address switching circuit 34 switches the address of the memory 26 when writing and reading from the memory.

Further, the output of the A/D converter 20 is given to a bit converter 42. The bit converter 42 converts the bit configuration of the applied digital signal and transmits it to the memory 26. Further, the signal read from the memory 26 is given to the bit inverter 43, where the bit configuration is inversely converted and the signal is sent to the D/A converter 27.
can be conveyed to.

Next, the operation of this embodiment will be explained. During normal reproduction, the same operation as in the conventional example is performed, and the signal switching circuit 21 outputs the signal from the reproduction circuit 17 as it is. Now, when running at high speed, the pinch roller 6 and the capstan 7 are separated and the capstan motor 8 is rotated at high speed, so that the magnetic tape 5 is transferred to the supply reel or the take-up reel 12.
is being wound at high speed. In this case, the signals obtained from the speed detectors 13 and 14 are sent to the capstan control/drive circuit 1.
6 to control the capstan motor 8 so that the tape running speed of the magnetic tape 5 is constant. Furthermore, the relative speed between the cylinder 2 and the magnetic tape 5 is read out from the ROM 1B and compared with the signal from the speed detector 32 and the phase detector 4 so that the horizontal feedback period of the reproduction signal is the same as during normal reproduction.
The rotational speed of the cylinder 2 is controlled by the cylinder control/drive circuit 5 so as to be part of the value of OM1B.

In this way, even during high-speed running, the horizontal feedback period of the reproduced signal can be kept the same as in normal reproduction by correcting the relative speed between the cylinder 2 and the magnetic tape 5.

In this controlled state, the signal obtained from the rotary head 1 is reproduced by the reproduction circuit 17.

A part of this reproduced signal is then given to the synchronization separation circuit 19, where the horizontal synchronization signal is separated and given to the control section 22. On the other hand, the second video signal from the tuner etc. is sent to the synchronous separation circuit 24.
The vertical and horizontal synchronizing signals are separated by and applied to the control section 22. Now, when writing to the memory 26, the clock generated by the write system clock generator 31 is counted by the H-direction address counter 32, and the H-direction address is given to the address switching circuit 34 by resetting it for each horizontal synchronization signal. The direction counter 35 also counts up every horizontal synchronization signal and is reset every time the head switching signal changes. Since the relative speed of cylinder 2 is corrected, in the case of rapid traverse, the rotational speed of cylinder 20 will be higher than the normal rotational speed, and the frequency of the head switching signal will be high, for example 951 (z). The count value of 35 is smaller than the normal number of horizontal scanning lines, for example, 0 to 165 is counted repeatedly.In addition, in the case of rewinding, the rotational speed of cylinder 2 is slower than the normal rotational speed, and the head The frequency of the switching signal is low, for example 24 &.Therefore, the V-direction counter has a larger count value than usual, for example, it repeatedly counts from 0 to 656.Then, the thinning circuit 36 uses the count value of the V-direction counter and Based on the size to be displayed, the pulses of the source clock, 15.759 Hz, are thinned out and applied to the V direction address counter, and the maximum count value of the ■ direction address counter is kept below 262.In this way, V
The number of lines to be thinned out is determined by the thinning circuit 36 based on the count value of the direction counter 35 and the displayed size, and
A clock for operating the direction address counter 38 is generated. In this way, by controlling the address in the {circle around (2)} direction when writing to the memory 24, the screen can be reduced in the vertical direction. For example, if the tape is running in the fast forward direction, all inputs can be stored in memory even if the tape is running in the fast forward direction, but if the tape is running in the rewinding direction, it is sufficient to store all inputs in the memory in the 1 screen or 2 screen display. The number of lines to be thinned out differs depending on the display case.

Next, the operation when reading signals from the memory 26 will be explained. The read system clock generator 37 uses the horizontal and vertical synchronization signals of the second video signal and the source clock to generate an H direction address counter 39° ■ direction address counter 40
and generate memory control signals. The H direction address counter 39 counts up using a clock generated by the input clock, and is reset every horizontal synchronization signal. This clock changes depending on the display size.

For example, when displaying on the entire screen, the write system and read system clocks in the H direction are the same, and when displaying on a partition screen, the read system clock has twice the frequency of the write system clock. (2) The direction address counter 40 counts up every horizontal synchronization signal. When the tape running direction is the fast forward direction, the rotation period of the rotary cylinder 2 becomes shorter, so the number of lines within one vertical period becomes smaller than in the case of normal playback. Therefore, in the read system clock generator 37, when the maximum count value of the direction counter 35 is reached, the count of the direction address counter 40 is stopped. Further, the decoder 41 switches the clock of the D/A converter 27 and the signal of the mixing circuit 25 to create and output a signal. The address switching circuit 34 switches each address for each mode and outputs it to the memory 26.

On the other hand, the reproduced signal converted into digital data by the A/D converter 20 has its bit configuration switched by the bit converter 42 of the control section 22, and is input to the memory 26 according to the selected address and control signal. Then, each control signal generated by the read system and the switched address are outputted from the memory 26, and outputted to the D/A converter 27 via the bit inversion circuit 43. The D/A converter 27 converts this digital data into an analog signal and synthesizes it with the synchronization signal of the second video signal, thereby superimposing the reproduced signal on the signal with the normal synchronization signal, and switching the signal using the signal switching circuit 21. and then output it to the TV screen. In this way, the screen can be displayed normally on the monitor without any blanking even during fast-forward playback and double-back playback.

Although this embodiment shows a reproduction signal superimposed on the second video signal, a synchronization signal may be created within the control section 22 and added to the reproduction signal.

Although correction in the V direction is realized by controlling addresses, it can also be realized by line interpolation of data.

〔Effect of the invention〕

As explained in detail above, according to the present invention, the traveling speed of the magnetic tape is kept constant during fast-forward playback and rewind playback,
By correcting the relative speeds of the magnetic tape and the cylinder, it is possible to display reproduction signals at various tape speeds on the monitor screen.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the overall configuration of the first embodiment of the present invention, FIG. 2 is a block diagram showing the detailed configuration of the control section of this embodiment, and FIG. 3 is the entire conventional video signal processing device. FIG. 2 is a block diagram showing the configuration. 1--One-rotation head, 2--One-rotation cylinder, 3--11--Speed detector, 4--
- Phase detector, 5...- Magnetic tape,
6--Pinch roller, 7--Capstan, 8--111--Capstan motor,
9--speed detector, 10--1-control head, 11--1 supply side reel,
12.---- Winding side reel, 13.14.
-1111 speed detector, 15-1111 cylinder control/drive circuit, 16--capstan control/drive circuit, 17-...-regeneration circuit, 18,
---ROM, 19---Synchronization separation circuit, 20---A/D converter, 21------
-Signal switching circuit, 22--1--control section, 24
・-1---Synchronization separation circuit, 25-...Mixing circuit,
26--Memory, 27--D/A converter, 31--Write clock generator, 3
2.39----H direction address counter, 33.4
1-...--Decoder, 34-m-Address switching circuit, 35--■Direction counter, 36--
Thinning circuit, 37.--Read system clock generator, 38, 40--V direction address counter. Patent applicant Matsushita Electric Industrial Co., Ltd.

Claims (3)

[Claims] (1) A video signal processing device that reproduces video signals recorded on a magnetic tape by disposing a pair of rotary heads for reading video signals from a magnetic tape on a rotary cylinder and alternately switching the rotary heads, the device comprising: A capstan control/drive means that detects the rotational speed of the take-up reel and supply reel during high-speed running and controls the capstan motor to keep the tape running speed constant; and a capstan control/drive means that detects the rotational speed of the cylinder during high-speed running. , cylinder control/driving means for controlling the relative speed of the rotary cylinder and the magnetic tape to be the same speed as normal playback based on the detection signal; and a horizontal synchronization signal from the video signal reproduced by the rotary head. a first synchronization separation circuit that separates the signals; and A that converts the video signal reproduced from the rotary head into a digital video signal.
a /D converter, a memory that holds a digital video signal, a synchronization signal generation circuit that generates horizontal and vertical synchronization signals for the video signal, and outputs of the first synchronization separation circuit and the synchronization signal generation circuit and the rotation. A head switching signal is applied, and while interpolating a vertical synchronization signal to be written into the memory, the A is written into the memory.
a control unit that writes a digital video signal of the /D converter and controls a read address of the memory based on a synchronization signal of the synchronization signal generation circuit to read the written video signal; and a control unit that reads the written video signal from the memory. a D/A converter that converts the converted digital signal into an analog signal; and a mixing circuit that superimposes the analog video signal converted by the D/A converter on a video synchronization signal. Signal processing device. (2) The control unit includes: a first H direction address counter that counts a predetermined clock and is reset by a horizontal synchronization signal obtained from the first horizontal synchronization signal; and a first H-direction address counter that is reset by a horizontal synchronization signal obtained from the first horizontal synchronization signal. a V-direction counter that counts horizontal synchronization signals and is reset by a head switching signal; and a thinning device that thins out and outputs pulses of the horizontal synchronization signal obtained from the first horizontal synchronization signal based on the counted value of the V-direction counter. a first V-direction address counter that counts the output of the thinning circuit; and a second H-direction address counter that counts a predetermined clock and is reset by a horizontal synchronization signal output from the synchronization signal generation circuit.
a second V-direction address counter that counts horizontal synchronization signals obtained from the second synchronization separation circuit and stops counting when the maximum count value of the V-direction counter is reached; When writing, the count values of the first H-direction address counter and the first V-direction address counter are stored in the memory, and when reading, the count values of the second H-direction address counter and the second V-direction address counter are stored in the memory. an address switching circuit that switches the address signal to be output;
The video signal processing device according to claim 1, characterized in that it has: (3) The synchronization signal generation circuit receives a second synchronization signal from the outside.
a second synchronization separation circuit that separates horizontal and vertical synchronization signals of the video signal, and the mixing circuit superimposes the analog video signal converted by the D/A converter on the synchronization signal of the second video signal. Claim 1 characterized in that
Or the video signal processing device according to 2.