JP3126290B2 - Video signal processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-standard video signal generated by a special reproduction of a video and the like, wherein a video signal in which the cycle of a vertical synchronizing signal changes is output to a television receiver (hereinafter referred to as TV). And a video signal processing apparatus for securing a stable video.

[0002]

2. Description of the Related Art In recent years, video applications have been proposed not only for simple TV time shift and software viewing, but also for a new way of enjoying by special reproduction. What is reproducible is required.

[0003] A conventional video signal processing apparatus will be described below. Conventionally, as this type of video signal processing apparatus, for example, an apparatus disclosed in Japanese Patent Application Laid-Open No. 4-326272 has been proposed. Hereinafter, the configuration will be described with reference to FIGS. 4 and 5. FIG. 4 is a block diagram showing the configuration of this conventional video signal processing device, and FIG.
FIG. 3 is a configuration diagram showing a head configuration of FIG. In FIG. 4, the rotary cylinder 8 is provided with two sets of reproducing heads for standard reproduction and triple mode reproduction. Standard playback head SP1,
SP2 and triple-mode playback heads EP1 and EP2 are:
The two heads SP1, SP2 and EP1, EP2 of each set are attached to the positive and negative azimuth angles with respect to each other. Further head EP
1 and EP2 are arranged at a distance corresponding to twice the horizontal period (hereinafter, referred to as H) with respect to the heads SP2 and SP1, respectively.

[0004] The operation of the conventional video signal processing apparatus configured as described above will be described below with reference to FIGS. 4 and 5. Referring to FIG. 4, a conventional video signal processing apparatus uses a reproducing head SP1, SP2 and EP1,
The reproduction signal from EP2 is output to switch circuit 2 via reproduction amplifiers 1S and 1E, respectively. These reproduced signals are switched by the switch circuit 2 and supplied to the video signal demodulation circuit 4, and the demodulated video signal is supplied to the field memory 6 through the A / D converter 5. As a result, the video signals are respectively stored at predetermined addresses, and the stored video signals are sequentially read out and taken out to the output terminal 10 through the D / A converter 9. Further, the above-described head switching signal and address reset signal are supplied to the memory control circuit 11, and a write control signal for the field memory 6 is formed.

When a reproduction signal is output in combination with a head having a slightly shifted mounting position and a different azimuth angle at the time of still image reproduction or variable speed reproduction, a slight mounting position deviation (2H) between the heads causes A time lag of the generated video signal occurs. This deviation can be eliminated by controlling the write address of the field memory 6, and a good reproduction signal can be obtained.

[0006]

However, in the above-described conventional configuration, as shown in FIG.
However, there is a problem that the cost is so large that it cannot be introduced into a product of a popular machine class.

SUMMARY OF THE INVENTION The present invention has been made to solve such a conventional problem, and has a relatively simple structure, in which the period of the vertical synchronizing signal is fixed and the image signal can be stabilized. It is an object to provide a processing device.

[0008]

According to a first aspect of the present invention, there is provided a signal reproducing means for outputting a non-standard video signal in which a period of a vertical synchronizing signal repeatedly varies with three or more fields as one pattern, and a non-standard video signal. A pseudo vertical synchronizing signal generating means for generating a pseudo vertical synchronizing signal at a predetermined timing, a signal synthesizing means for synthesizing a pseudo vertical synchronizing signal and a non-standard video signal, Delay amount control means for controlling the delay amount for each field of the non-standard video signal in accordance with the position of the pseudo vertical synchronization signal so that the period of the synchronization signal is constant; and non-standard in accordance with the output of the delay amount control means Delay means for delaying the video signal by an integral multiple of the horizontal synchronizing signal period in field units.

According to a second aspect of the present invention, there is provided a signal reproducing means for outputting a non-standard video signal in which a period of a vertical synchronizing signal repeatedly varies with three or more fields as one pattern, and a constant period of the non-standard video signal. Delay amount control means for controlling the delay amount for each field of the non-standard video signal,
Delay means for delaying the non-standard video signal by an integral multiple of the horizontal synchronizing signal period in field units in accordance with the output of the delay amount control means; and a non-standard video signal at a predetermined timing of the video signal output by the delay means. Pseudo vertical synchronization signal generating means for generating a pseudo vertical synchronization signal having a constant period equal to the average period, and signal synthesizing means for synthesizing the pseudo vertical synchronization signal by the pseudo vertical synchronization signal generating means with the video signal output from the delay means. It is characterized by having.

[0010]

According to the first aspect of the present invention having such a feature, the period of the vertical synchronizing signal is 3 fields or more and 1
A video signal that repeatedly fluctuates as a pattern has an average period equal to the average period, generates a pseudo vertical synchronizing signal at a predetermined timing, and combines the pseudo vertical synchronization signal with a non-standard video signal by a signal combining unit. The delay amount is controlled by the delay amount control means so that the period variation of the vertical synchronizing signal is constant, and the delay amount is controlled by the delay means. Here, it is assumed that the generation timing of the pseudo vertical synchronizing signal is set so that the vertical synchronizing signal has a fixed period after the delay.

According to the second aspect of the present invention, the non-standard video signal is delayed by controlling the delay amount so as to make the cycle constant, and the pseudo vertical synchronizing signal having a constant cycle equal to the average cycle of the non-standard video signal. Are generated by the pseudo vertical synchronizing signal generating means, and are synthesized by the delay output and the signal synthesizing means. By doing so, the period of the vertical synchronizing signal becomes constant for each field, so that it is possible to eliminate the vertical swing of the image on the TV screen and the horizontal swing of the screen corner.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the video signal processing device according to the first embodiment of the present invention. In the figure, the description of the same components as the conventional example is omitted. In FIG. 1, a capstan 13 contacts and feeds a tape 12 recorded in a standard mode. The FG 14 outputs an FG signal having a frequency proportional to the rotation speed of the capstan 13. The capstan drive circuit 15 causes the capstan 13 to generate torque according to a torque command from the control circuit 20. The CTL head 16 detects a control signal recorded at equal intervals on the tape 12 and outputs a CTL signal. The PFG 18 outputs a PFG signal in which a signal indicating the rotation phase of the cylinder 8 is superimposed on a signal having a frequency proportional to the rotation speed of the cylinder 8. The cylinder drive circuit 17 generates torque in the cylinder 8 according to a torque command from the control circuit 20. The control circuit 20 outputs a torque command for controlling the rotation of the cylinder 8 based on the PFG signal to the cylinder drive circuit 17, and outputs the FG signal and the CT signal.
A torque command is output to the capstan drive circuit 15 so that the tape 12 is fed at a predetermined speed and phase using the L signal. Further, the control circuit 20 controls the HS for switching the head according to the tape feeding phase and the rotation phase of the cylinder at that time.
It outputs a W signal and a delay command d. The pseudo vertical synchronizing signal generation circuit 21 generates a pseudo vertical synchronizing signal b in accordance with an instruction from the control circuit 20. This pseudo vertical synchronizing signal is a signal having the same constant period as the average H number of each field determined by the reproduction speed at the time of reproduction. The signal synthesis circuit 22 synthesizes the video signal a output from the video signal demodulation circuit 4 and the pseudo vertical synchronization signal b. The delay circuit 23 delays the video signal up to 3H in accordance with the delay command d output from the control circuit 20. The TV 19 is a display device that displays the delayed signal e on the screen.

The operation of the video signal processing apparatus according to the present embodiment configured as described above at the time of 4/3 speed reproduction will be described with reference to FIGS. Tape 12 is capstan 13
Thus, the signal is sent at 4/3 times the speed of the standard mode while maintaining the relationship between the HSW signal and the CTL signal in the phase relationship shown in FIG. At this time, the output of the four heads SP1, SP2, EP1, EP2 attached to the cylinder 8 is selected by the switch circuit 2 by two HSW signals shown in FIG. Since the head having the maximum output is selected as the switch circuit 2, the heads EP1, EP2, EP in FIG.
2, SP1, SP2, SP1,..., Are output as signals which are repeated in units of 6 fields as one pattern.
This signal is input to the video signal demodulation circuit 4 and the video signal a
Is converted to The pseudo vertical synchronizing signal generation circuit 21 is shown in FIG.
A pseudo vertical synchronization signal is generated at the timing shown in FIG.
The signal is transmitted to the signal synthesizing circuit 22 together with the demodulated video signal a. The signal synthesizing circuit 22 synthesizes these signals and supplies a synthesized signal c to the delay circuit 23. The delay circuit 23 delays by a predetermined time for each field according to the delay command d in FIG.

Here, the reproduced video signal will be described in more detail. The head selected from the four heads at the timing shown in FIG.
FIG. 2 shows a state where 0 is traced. In this figure, when the tape 12 is fed at 4/3 times the speed of the standard mode, the position where the head traces the lower end of the track is shifted from the center of the track, so that the reproduction timing of the vertical synchronizing signal is delicate. It can be seen that it changes. In the standard mode recording of the VHS format, the lower end position of each track is shifted by 1.5H as shown in FIG. Here, the average H number (X) between the vertical synchronizing signals when the tape is sent at n times speed can be obtained by equation (1), where K is the deviation of the lower end position between the tracks. However, the unit is [H] and the video signal is NTSC. X = 262.5−K (n−1) (1) That is, in the case of 4/3 times the speed of the standard mode, K = 1.5,
Since n = 4/3, the average H number is 262H.
In FIG. 3, the time between the broken lines is the average H number. 3
In the double mode reproduction, K is 0.5.

[0015] The standard reproducing heads SP1 and SP2
Considering 2H, which is the amount of displacement between the mounting positions of the triple-mode playback heads EP1 and EP2, the generation timing of the vertical synchronization signal is shifted by a maximum of 3H as shown in the demodulated video signal in FIG. 3A. FIG. 3b shows the pseudo vertical synchronization signal. Here, in FIGS. 3A and 3B, α indicates the delay of the synchronization signal of the demodulated video signal a with respect to the control signal CTL of the first field having six fields as one pattern, and β indicates the demodulated signal of FIG. 3A. 3 shows a time difference between the pseudo vertical synchronizing signal generated by the pseudo vertical synchronizing signal generation circuit 21 and the synchronizing signal. Due to the difference between the average H number and the vertical synchronization signal, the H number between the vertical synchronization signals changes from 259H to 263H, as shown in FIG. Also, as shown in FIG. 3B, the period of the pseudo vertical synchronization signal is changed with six fields as one pattern. Assuming that the phase difference between the video signal and the vertical synchronization signal in the first field of this pattern is β, the phase difference for each field is β, β +
0.5H, β, β, β + 0.5H, β, and the average period of the pseudo vertical synchronization signal is equal to the average H number of the vertical synchronization signal, ie, 2
62H. Then, a delay is performed for each field of the video signal a by the number H shown in FIG. By doing so, the H number between the vertical synchronization signals is constant at 262H as shown in FIG. In this way, so that the period after the delay is constant,
The generation timing of the pseudo vertical synchronization signal is selected in advance.

As described above, according to the embodiment of the present invention, 4
By delaying each field of the video signal a output at the time of / 3x speed reproduction by 3H, 3H, 2H, 1H, 1H, 0H, the H number between the vertical synchronization signals can be kept constant, and the vertical synchronization signal can be maintained. Vertical fluctuations and horizontal fluctuations at the corners of the screen, which are caused by the periodic fluctuations of the TV image.

Further, in this embodiment, the number of Hs between vertical synchronization signals can be all shifted by 0.5H from the number of Hs of the standard signal (262.5H). A stable TV image can be secured without erroneous discrimination even in a TV that discriminates a standard signal.

In this embodiment, the tape speed is 4/4 of the standard mode.
Although the triple speed is described, the H number between the vertical synchronization signals can be kept constant by appropriately selecting the delay time at other speeds. That is, as shown in Tables 1 and 2, tapes recorded in the standard mode were set to 2/3 times speed, 3
Even in the case of reproducing at / 4 times speed, 5/4 times speed, and 3/2 times speed, by selecting the delay time and the time difference between the reproduced video signal and the pseudo vertical synchronizing signal as shown in the table, the H between the vertical synchronizing signals can be obtained. The number can be constant.

[Table 1]

[Table 2]

In the case of a tape reproduced in the 3 × mode, even when the tape is reproduced at 2/3 × speed, 3/4 × speed, 5/4 × speed, 4/3 × speed and 3/2 × speed, the delay time and the reproduced image By selecting the time difference between the signal and the pseudo vertical synchronization signal as shown in the table, the H number of the vertical synchronization signal can be kept constant.

[Table 3]

[Table 4]

[Table 5]

The control circuit 20 stores such a delay amount pattern corresponding to the reproduction speed, reads out this signal in synchronization with the HSW signal, and supplies the read out signal to the delay circuit 23 to thereby suppress the fluctuation of the vertical synchronization signal. Shall be suppressed. In this way, it is possible to greatly reduce the vertical swing of the TV image and the horizontal swing of the screen corner with an extremely simple configuration.

In this embodiment, the delay circuit 23 is used for reproducing the standard reproducing heads SP1 and SP at the time of reproducing a still image or reproducing at double speed.
It can also be used for the purpose of correcting the amount of displacement between the mounting positions of the P2 and the triple-mode playback heads EP1 and EP2, and can significantly improve the performance of the VTR with a slight increase in cost.

In this embodiment, the control circuit 20 can be realized by software in a microcomputer or a digital signal processor. In this case, the control circuit can be realized without increasing the cost of the control circuit section. .

The pseudo vertical synchronizing signal generating circuit 21 and the signal synthesizing circuit 22 used in the present embodiment
Are used at the time of reproducing a still image, so that cost increase does not occur in most cases.

In this embodiment, the video signal demodulation circuit 4
Although the video signal a and the pseudo vertical synchronizing signal b demodulated in the above are synthesized and then delayed by the delay circuit 23, a method of synthesizing the video signal and then synthesizing it into a pseudo vertical synchronizing signal having a fixed period may be considered. The method is not limited to the present embodiment.

Further, in the present embodiment, the position at which the pseudo vertical synchronizing signal is input is fixed for each field. However, this can be moved forward and backward by fine adjustment as in the case of reproducing a still image, so that more TVs can be used. It is also conceivable that a stable image can be secured by using the method described above, and the method is not limited to this embodiment.

[0026]

As described above, according to the present invention, the H number between the vertical synchronization signals can be made completely constant. Therefore, a video signal processing device capable of completely eliminating the vertical swing of a TV image and the horizontal swing of a screen corner and securing a stable image even in a TV in which a standard signal is distinguished from a non-standard signal. And its practical effect is great.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a video signal processing device according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a head trace in the embodiment.

FIG. 3 is a timing chart showing video signal processing contents of the embodiment.

FIG. 4 is a block diagram showing a configuration of a conventional video signal processing device.

FIG. 5 is an explanatory view showing a head configuration of a cylinder.

[Explanation of symbols]

 2 switch circuit 4 video signal demodulation circuit 8 cylinder 12 tape 13 capstan 16 CTL head 19 TV 20 control circuit 23 delay circuit a, e video signal d delay command

──────────────────────────────────────────────────の Continued on the front page (72) Yoshitomi Nagaoka 1006 Kadoma Kadoma, Kadoma City, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. (72) Inventor Yutaka Ota 1006 Kadoma Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd. (56) References JP-A-4-326272 (JP, A) JP-A-7-87356 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 5/91-5 / 956 H04N 5/06-5/10

Claims (12)

(57) [Claims] 1. A signal reproducing means for outputting a non-standard video signal in which the period of a vertical synchronizing signal repeatedly fluctuates with three or more fields as one pattern, an average period equal to the average period of the non-standard video signal, Pseudo vertical synchronizing signal generating means for generating a pseudo vertical synchronizing signal at the timing of: signal synthesizing means for synthesizing the pseudo vertical synchronizing signal and the non-standard video signal; and making the period of the pseudo vertical synchronizing signal constant. A delay amount control unit that controls a delay amount for each field of the non-standard video signal according to the position of the pseudo vertical synchronization signal; and the non-standard video signal in units of fields according to an output of the delay amount control unit. A video signal processing device comprising: delay means for delaying by a time that is an integral multiple of the horizontal synchronization signal period. 2. A signal reproducing means for outputting a non-standard video signal in which a period of a vertical synchronizing signal repeatedly fluctuates with three or more fields as one pattern, and the non-standard video signal so as to make the period of the non-standard video signal constant. Delay amount control means for controlling a delay amount of each field of a signal; delay means for delaying the non-standard video signal by an integral multiple of a horizontal synchronizing signal period in field units according to an output of the delay amount control means A pseudo vertical synchronizing signal generating means for generating a pseudo vertical synchronizing signal having a constant period equal to the average period of the non-standard video signal at a predetermined timing of the video signal output by the delay means; and the pseudo vertical synchronizing signal generating means. And a signal synthesizing means for synthesizing the pseudo vertical synchronizing signal according to (1) with the video signal output from the delay means. 3. The delay amount control means according to claim 1, wherein said delay amount control means controls a delay time in a standard mode.
3H, 3H, 2H, 3H, 3H, 2H,
3. The video signal processing device according to claim 1, wherein the video signal processing device controls so as to delay 1H, 1H, and 0H. 4. The delay amount control means according to claim 2, wherein
3H, 3H, 3H, 3H,
3. The video signal processing device according to claim 1, wherein the video signal processing device controls so as to delay 0H, 1H, and 1H. 5. The delay amount control unit according to claim 3, wherein the delay amount control unit controls a delay in a standard mode.
For non-standard video signals reproduced at / 4x speed, 2H, 2H, 3H,
3. The video signal processing device according to claim 1, wherein the video signal processing device controls so as to delay 3H, 0H, 0H, 1H, and 1H. 6. The delay amount control means according to claim 5, wherein
For non-standard video signals reproduced at / 4x speed, 3H, 3H, 2H,
3. The video signal processing device according to claim 1, wherein the video signal processing device controls so as to delay 2H, 1H, 1H, 0H, and 0H. 7. The delay amount control means according to claim 3, wherein
3H, 3H, 2H, 3H, 3H, 2H,
3. The video signal processing device according to claim 1, wherein the video signal processing device controls so as to delay 1H, 1H, and 0H. 8. The non-standard video signal reproduced at 2/3 × speed of the 3 × speed mode, wherein the delay amount control means sets 2H, 2H, 2H for each field in units of 6 fields.
3. The video signal processing device according to claim 1, wherein the video signal processing device controls so as to delay H, 2H, 0H, and 0H. 9. The delay amount control means controls a non-standard video signal reproduced at a 3/4 speed in a 3 × speed mode in units of 8 fields by 2H, 2H, 2
3. The video signal processing device according to claim 1, wherein the video signal processing device controls so as to delay H, 2H, 2H, 3H, 0H, and 0H. 10. The non-standard video signal reproduced at 4/3 × speed in the 3 × speed mode, wherein the delay amount control means performs 2H, 2H, 2
3. The video signal processing device according to claim 1, wherein the video signal processing device controls so as to delay H, 2H, 2H, 1H, 0H, and 0H. 11. The non-standard video signal reproduced at 4/3 × speed in the 3 × speed mode, wherein the delay amount control means sets 2H, 2H, 2H for each field in units of 6 fields.
3. The video signal processing device according to claim 1, wherein the video signal processing device controls so as to delay H, 2H, 0H, and 0H. 12. The non-standard video signal reproduced at 3/2 × speed in a 3 × speed mode, wherein the delay amount control means performs 2H, 2H, 2
3. The video signal processing device according to claim 1, wherein the video signal processing device controls so as to delay H, 0H, 2H, 2H, 2H, and 0H.