JPH04159660A - Sector mark detection device - Google Patents

Abstract

PURPOSE:To enable a highly reliable sector mark detection to be made by generating a pseudo sector mark accurately corresponding to an original position even for an erroneous detection of the sector mark. CONSTITUTION:A sector mark SM of each sector where tracks are divided and an address mark AM are detected by detection circuits 2 and 1. The SM detection signal determines if reading of an address data after AM is possible through a CRC check circuit 3, an address read state signal generation circuit 7, a counter, a sector interval long latch circuit 14 etc. If it is determined that reading is possible, a pseudo SM is interpolated through a counter reset reinforcement circuit 15, a complement circuit 18, a counter etc. at an SM detection interval of a sector where the address belongs to. A start signal generation circuit 4 monitors an output of the SM detection circuit 2 and then outputs the pseudo SM signal as the SM detection signal if there is not output, thus enabling a pseudo mark to be generated at an original position even in the case of an erroneous detection of SM and the SM to be detected accurately.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a sector mark detection device for an optical disk device that detects the starting points of a plurality of sectors formed on a recording track of an optical disk as a disc-shaped recording medium.

[Prior Art] In an optical recording/reproducing device, a disc-shaped recording medium (hereinafter referred to as
(called ``optical disks'') are widely used.

In a recording/reproducing apparatus that records or reproduces information using the disc-shaped recording medium, information data is recorded along concentric or spiral tracks of the optical disc. In this case, each track is divided into multiple sectors and used as data processing units.

That is, when recording or reproducing information on an optical disc, when controlling random access and single read/write,
A mark indicating the starting point of one recording layer is attached, and this recording unit is called a sector, and this mark is also called a sector mark.

The sector mark is useful not only for the above control but also for facilitating timing control during data reading and writing, and for making detection of periodic signals more reliable.

As described above, sector marks are effective for access control and signal detection during reading or writing, but the reliability of their detection must be sufficiently high. By the way, in optical discs, it is difficult to sufficiently reduce defects in the recording film, noise, etc., and it is necessary to create an apparatus that can tolerate errors of about 10-5 to 10-6 in terms of bit error rate.

Among the above errors, burst errors are more problematic than random errors.

The reliability of recorded/reproduced data is improved by adding an error correction code. Furthermore, burst errors can be dispersed by using an interleaving method that records data in a distributed manner, and even fairly long burst errors can be dealt with.

However, this method cannot be applied to sector mark detection, and therefore cannot be put to practical use unless some improvement is made to increase reliability.

For this reason, the notation t! shown in JP-A No. 61-5476! Devices use methods such as gates to prevent erroneous detection of sector marks. However, if the rotational error of the optical disk is large, the gate width must be wide, and if we consider the case where marks cannot be detected continuously, the gate width must be even wider. Considering this, it is impossible to prevent erroneous detection near sector marks.

Therefore, in the conventional example disclosed in Japanese Patent Application Laid-Open No. 60-201573, as shown in FIG. If no sector mark is detected at the end of this period, a pseudo sector mark signal is generated, and a composite sector mark signal is generated by combining the sector mark signal and the pseudo sector mark signal. A method of using the sector mark signal instead of the sector mark signal has been adopted.

[Issue 1i to be solved by the invention] However, in the method disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 60-201573, due to the deterioration of data recording quality, for example There was a possibility that a recorded signal in a place other than a sector mark could be mistaken for a sector mark.If such a misidentification occurs, the pseudo sector mark generation means for generating a pseudo sector mark may be This synchronizes with the sector mark detection signal, and a pseudo sector mark, like "bo" shown in the figure, is generated at a point completely unrelated to the original sector mark, resulting in an incorrect position (" c6) is interpolated.

The present invention has been made in view of the above-mentioned circumstances, and it is possible to create a pseudo sector mark that accurately corresponds to the position where the sector mark is originally located, without losing the timing even when the sector mark is erroneously detected as described above. It is an object of the present invention to provide a sector mark detection device that can generate highly reliable sector mark detection.

Means for Solving Problem c] In order to achieve the above object, the sector mark detection device according to the present invention is divided into a plurality of sectors, and each sector has a sector mark indicating a sector start position and address data of each sector. sector mark detection means for detecting the sector mark from a playback signal of a recording track on which an address mark indicating a recording start position is recorded and outputting a sector mark detection signal; and detecting the address mark of each sector from the playback signal. a readability determining means for determining whether the address data following the address mark is correct or not and determining whether the address data can be read; and a sector to which the address determined to be readable by the readability determining means belongs. sector mark interpolation means for outputting a pseudo sector mark signal based on sector mark detection timing; and sector mark interpolation means for monitoring the output of the sector mark detection means, and interpolating the pseudo sector mark signal to the sector when the sector mark detection signal is not output. sector mark detection signal output means for outputting a mark detection signal.

[Operation] According to the present invention, a pseudo sector mark signal is generated based on the sector mark detection timing of the sector whose address data is confirmed to have no error by the address data readability determining means, and the pseudo sector mark signal is generated when the sector mark is not detected. Therefore, when the sector mark detection signal is not output, the pseudo sector mark signal or the sector mark detection signal is output in place of the sector mark detection signal.

Therefore, even if a sector mark is erroneously detected, a pseudo sector mark signal that is not synchronized with the sector mark detection signal is output, making it possible to interpolate the pseudo sector mark at the position where the sector mark is originally located. .

[Example code] Examples of the present invention will be described below.

FIG. 1 is a diagram showing a pseudo sector mark generation circuit of a data recording/reproducing apparatus according to the present invention. This pseudo sector mark generation circuit receives a reproduction signal a as shown in FIG. 3 from an optical disk reproduction circuit (not shown), an address mark detection circuit 1,
The data is input to a sector mark detection circuit 2 and a CRC check circuit 3. Address mark detection circuit 1 detects an address mark (AM) from reproduced signal a, and outputs an address mark detection signal S to CRC check circuit 3. The sector mark detection circuit 2 detects a sector mark from the reproduced signal a, and sends the sector mark detection signal d to the start signal generation circuit 4.
Output to. The CRC check circuit 3 determines whether or not there is an error in the address data in the reproduced signal a based on the generation timing of the address mark detection signal S, and generates an address data read enable signal C if there is no error.

The start signal generation circuit 4 to which the sector mark detection signal d is supplied outputs a first counter start signal f to the first counter 5 based on the sector mark detection signal d and the pseudo sector mark signal e, and generates a composite sector mark signal P (not shown). Output to external circuit. The first counter 5 receives the first counter start signal f at its reset terminal, is reset as the first counter reset signal, and starts counting. 1st
The decoder 6 receives the count value of the first counter 5, and
When the count value reaches the respective decoded value, an address mark detection gate signal 0 is output to the address mark detection circuit 1, and a timing signal g is generated.

Address read state signal generation circuit 7 generates an address read state signal that rises in response to address data read enable signal C and falls in response to timing signal k, which will be described later. The AND circuit 8 receives the address read status signal and the timing signal g, and outputs a predetermined signal based on the logical condition that the timing signal g is output (high level) when the address read status signal is being output (high level). (high level). A second counter reset circuit 9 and a latch signal generation circuit 10 are connected to the output side of the AND circuit 8, respectively.

The second counter reset circuit 9 outputs a second counter reset signal j for resetting a second counter, which will be described later, according to the timing of the output signal of the AND circuit 8. Furthermore, when address data can be read in two consecutive sectors, the latch signal generation circuit 10 latches the value of a second counter (described later) in a sector interval length latch circuit (described later) according to the timing of the output signal of the AND circuit 8. outputs a latch signal i for

The OR circuit 11 outputs a predetermined signal (low level) according to a logic condition when a second counter reset signal j or a second counter reset interpolation signal m (described later) is output (high level). The output of this OR circuit] 1 is the output of the second counter 1
It is input to the reset terminal of No.2. The second counter 12 is reset by the logic circuit 11 and outputs a count value A. The second decoder 13 to which this count value A is applied outputs a timing signal k to the address read state signal generation circuit 7 when the count value of the second counter 12 reaches a predetermined decoded value. The sector interval length latch circuit 14, which receives the count value A and the latch signal i, holds the count value A of the second counter 12 at the timing of the latch signal 1 and outputs it as the sector interval length B. The second counter reset interpolation circuit 15 outputs a second counter reset interpolation timing signal g from the sector interval length B and the count value A of the second counter. This second counter reset interpolation timing signal g is input to one input terminal of the AND circuit 16. The other input terminal of the AND circuit 16 receives the address read status signal logically inverted by the inverter 17, and takes the logical conditions of the output signal of the inverter 17 and the second counter reset interpolation timing signal g.
The second counter reset interpolation signal m is output to the OR circuit 11. Further, the complement circuit unit 8 calculates the complement of the sector interval length B1, and transfers the third counter start value C to the third decoder 1.
Output to 9. The third decoder 9 receives a timing signal n when the second counter count value A or a predetermined decode value is reached.
is generated and output to the third counter 20. This third counter 20 is loaded with a third count start value C by the timing signal n, and the count value is transferred to the fourth decoder 2.
Output to 1. When the count value of the third counter 20 reaches a predetermined decode value, the fourth decoder 21 generates a pseudo sector mark signal e and outputs it to the start signal generation circuit 4. The pseudo sector mark generation circuit is configured as described above.

Next, the operation of this embodiment will be explained with reference to FIGS. 2 and 3.

In the pseudo sector mark generation circuit, various signals bp are generated based on the timing chart shown in FIG. It is assumed that the operation of this embodiment starts from a predetermined sector N, and that the address data of the immediately preceding sector N-1 cannot be read, and that the address data read enable signal C is not output.

The pseudo sector mark generation circuit generates a reproduced signal a shown in FIG.
A sector mark detection circuit 2 detects a sector mark from the sector mark detection circuit 2 and generates a sector mark detection signal d. This sector mark detection signal d is applied to the start signal generation circuit 6. Along with this, the start signal generation circuit 6 outputs the first counter start signal f, and as a result, the first counter 5 starts (timing tl). Further, the start signal generation circuit 4 outputs the sector mark detection signal d as a composite sector mark signal P, and also outputs a suspected sector mark signal as a sector mark detection signal when no sector mark is detected in the next sector. In addition, the first counter 5 is 1
It is a counter whose length is less than a sector, and it self-stops after counting up. In ml decoder 6, the first
The count value of the counter 5 is decoded and an address mark detection gate signal 0 is generated. When an address mark is detected while the address mark detection gate signal 0 is being output, the address mark detection circuit 1 generates an address mark detection signal S and outputs it to the CRC check circuit 3. CR
The C check circuit 3 determines whether or not address data can be read based on the generation timing of the address mark detection signal C, and outputs an address data readable signal C in accordance with the determination result. In other words, when the address data readable signal C is output, it means that the sector mark detection signal in that sector is not erroneously detected.

Furthermore, the address data is attached with an error correction code for determining whether or not it can be read, and is recorded in advance at the time of disk production so that it can be confirmed whether or not the read sector is the corresponding sector. The CRC check circuit 3 that performs this is a known technology. Furthermore, in this embodiment, since three pieces of address data are recorded in one sector, the address of the sector can be confirmed three times.

Address read state signal generation circuit 7, which has received address data read enable signal C, raises address read state signal C and opens the gate of AND circuit 8.

Based on the timing signal g output from the first decoder 6, the second counter reset circuit 9 outputs a second counter reset signal j to reset the second counter 12. Further, when the address read state signal is rising, the gate of the AND circuit 16 is closed and the second counter reset interpolation signal m is not output (timing t2).

The latch signal generation circuit 10 outputs the latch signal i when address data can be read in two consecutive sectors, but as shown in the initial assumption here, the address data read signal C is not output in the previous sector N-1. Because it is not possible to read address data in two consecutive sectors,
The latch signal generation circuit 10 does not output the latch signal i, and the value held by the sector interval length latch circuit 14 does not change.

When the count value of the second counter 12, which is reset at timing t2, reaches a predetermined value, the second decoder 13 applies a timing signal k, and the address read state signal generation circuit 7 receives the timing signal k. Lower the address read status signal. The third decoder 19
When the count value of the counter 12 reaches a predetermined value, the timing signal n is output, and the third counter start value C of the complement circuit 18 is loaded into the third counter 20.
0 starts. The second counter 12 has a length of one sector or more, and is reset once per sector by either the second counter reset signal j or the second counter reset interpolation signal m, but continues to perform the counting operation. The fourth decoder 21 outputs a pseudo sector mark e when the count value of the third counter 20 reaches a predetermined decode value, but as shown in FIG. 2, a sector mark was also detected in the next sector N+1. , the pseudo sector mark is not output as a composite sector mark P.

The operation in sector N+1 is performed at timing t in FIG.
Sectors up to 5 are the same as sector N. At timing t5, the latch signal generation circuit 10 outputs the address data read status signal for sector marker N+1 and two consecutive sectors, so the latch signal i is output based on the timing signal g, and the count value A of the second counter is output. is latched. The output timing of the latch signal i at this time is configured to be outputted one clock earlier than the second counter reset signal j outputted from the second counter reset circuit 9. For this reason, the count value A held by the latch signal i is
This is the actual measured value of the sector mark interval. The count value A is set to the sector interval length B by the sector interval length latch circuit 14.
and is output to the second counter reset interpolation circuit 15 and complement circuit 18. The complement circuit 18 calculates the complement of the sector interval length B and loads it into the third counter 20 as the third counter start value C using the timing signal n generated by the third decoder 19.

As a result, when the sector interval length B fluctuates due to uneven rotation of the optical disk, etc., when the sector interval length B is long,
When the third counter start value C becomes small and the sector interval length is short, the start value C of the third counter 20 becomes large, and a pseudo sector mark e is always generated by the fourth decoder 21 at the position where a sector mark should normally exist. . Note that the decoded value of the fourth decoder 21 is the value obtained by calculating the sector interval length B and adding the distance between timings t6 and 17 to the third counter start value C, assuming that there is no rotational fluctuation of the optical disc. . Therefore sector N+21. :Even if the sector mark detection signal d is not generated at timing t7
In this case, it becomes possible to output a composite sector mark signal P using the pseudo sector mark signal e.

Since no sector mark is detected in sector N+2, the start signal generation circuit 4 outputs the composite sector mark signal P at timing t7 due to the pseudo sector mark e, and at the same time generates the first counter start signal f and starts the first counter start signal f.
Start counter 5. The first decoder 6 generates an address mark gate signal 0 according to the count value of the first counter 5, but no address mark is detected and FIG.
As shown, since the address mark detection signal is not generated strongly, the address read enable signal C from the CRC check circuit 3 is not outputted, and even if the timing signal g from the first decoder 5 is generated, the address reading state is not reached. The signal generating circuit 7 does not raise the address read status signal and remains low. This closes the gate of the AND circuit 8 and no longer receives the timing signal g, and at the same time, the address read status signal opens the gate of the AND circuit 16 via the inverter 17. The AND circuit 16 receives the second counter reset interpolation timing signal g. Second counter reset interpolation circuit 15i1, previous sector N+1
The sector interval length latch circuit 141 compares the held sector interval length B with the count value A of the second counter 12, and when they match (timing t8), outputs the second counter reset interpolation timing signal p. As described above, since the gate of the AND circuit 16 is open at this time, the second counter reset interpolation signal m is generated, and the second counter 12 is thereby reset. At timing 19, when the third decoder 19 generates the timing signal n, the third counter start value C, which is the complement of the safety interval length B held in sector N+1 (-), is loaded into the third counter 20. The third counter 20 starts, and when the count value of the third counter 20 reaches a predetermined decode value, the fourth decoder 21 outputs a pseudo sector mark e, and at this time, the sector mark of the N+3 sector is not detected. Therefore, the start signal generation circuit 6 outputs the composite sector mark signal P from the pseudo sector mark eH to the external circuit (not shown) and at the same time generates the first counter start signal f to start the first counter. .

As a result of these operations, sector N+2. Sector mark interpolation 1 using the pseudo sector mark e of N+3, since the address data is counted based on the sector mark detection timing of sector N+1 where the address data can be detected, there is no deviation from the original position, and it is not shown in the figure. The source of the composite sector mark signal P, sector N+1. N+2
It is effective as a reference signal for reading data thereafter.

As described above, according to this embodiment, the CRC check circuit 3 confirms that there are no errors in the address data, and if two consecutive sectors of address data are error-free and can be read, the latch signal generation circuit 10 outputs the address data. The actual measured value of the sector mark interval of sectors N and N+1 is held by the latch signal i, and the sector mark generation timing of the sector is confirmed to be readable for the address data before the corresponding sector where no sector mark was detected. A counter started based on the above is operated repeatedly at the sector mark interval, and is used as a reference counter for generating pseudo sector marks, so even if a sector mark is detected incorrectly, a pseudo sector mark can be output at the position of a regular sector mark. Moreover, by interpolating sector marks, data recording/reproduction in the data section can be performed efficiently.

[Effects of the Invention] As detailed above, according to the present invention, even when a sector mark is erroneously detected, the timing does not go out of order, and a pseudo sector mark that accurately corresponds to the position where the sector mark is originally located can be generated. Thus, it is possible to provide a sector mark detection device that can realize extremely reliable sector mark detection.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a pseudo sector mark generation circuit of a sector mark detection device according to this embodiment, FIG. 2 is a diagram showing a time chart of the pseudo sector mark generation circuit, and FIG. 3 is an explanatory diagram of the operation of the same embodiment. , FIG. 4 is a diagram for explaining the problems of the conventional sector mark detection device. DESCRIPTION OF SYMBOLS 1... Address mark detection circuit, 2... Sector mark detection circuit, 3... CRC check circuit, 4... Start signal generation circuit, 5... First counter, 6...
1st decoder, 7... Address read state signal generation circuit, 8.16... AND circuit, 9... Second counter reset circuit, 10... Latch signal generation circuit, 11.
...OR circuit, 12...second counter, 13...
Second decoder, 14...Sector interval length latch circuit, 1
5. Second counter reset interpolation circuit, 17. Atsushi Tsuboi, Patent Attorney

Claims (2)

[Claims] (1) Detecting sector marks from a playback signal of a recording track that is divided into multiple sectors and in each sector has a sector mark indicating the sector start position and an address mark indicating the recording start position of address data of each sector. sector mark detection means for outputting a sector mark detection signal; and sector mark detection means for detecting the address mark of each sector from the reproduction signal and determining whether the address data following the address mark is correct or not, and whether or not the address data can be read. a sector mark interpolation means that outputs a pseudo sector mark signal based on a sector mark detection timing of a sector to which an address determined to be readable by the readability determination means belongs; A sector mark comprising sector mark detection signal output means for monitoring the output of the detection means and outputting the pseudo sector mark signal as the sector mark detection signal when the sector mark detection signal is not output. Detection device. (2) The sector mark interpolation means has means for measuring the sector mark interval of two consecutive sectors whose address data is determined to be readable by the readability determining means, and for holding the sector mark interval. 2. The sector mark detection device according to claim 1, wherein the sector mark interval is used for the sector mark detection timing.