JPH04157571A - Inter-flip-flop gate number rule analysis system for logic circuit - Google Patents

Abstract

PURPOSE:To use this system in a logical circuit of large scale without receiving limitation on the scale of the logical circuit capable of performing analysis by providing a logical circuit connection information storage means which stores the logical circuit connection information of the logical circuit in a functional descriptive unit(module) unified logically. CONSTITUTION:The system is constituted by providing an in-block gate number information storage means 1, the logical circuit connection information storage means 2, a hierarchical control means 3, a logical circuit inter-F/F gate number rule analysis means 4, an in-block gate number information automatic generating means 5, and a logical circuit inter-F/F gate number rule analysis result output means 6. The in-block gate number information storage means 1 stores gate number information that becomes a fundamental element in inter-F/F gate number rule analysis at the logical circuit at every block, and the logical circuit connection information storage means 2 stores the logical circuit connection information of the logical circuit of large scale in the functional descriptive unit(module) unified logically. In such a way, it is possible to analyze the inter-F /F gate number rule of even the logical circuit of large scale.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for analyzing the number of gate stages between flip-flops (hereinafter referred to as FF) in a logic circuit.

[Conventional technology]

The conventional logic circuit F/F gate stage number rule analysis method uses an in-block gate stage number information storage means, and a logic circuit connection that is stored only in one layer instead of in logically organized functional description units (modules). The device includes an information storage means, a logic circuit F/F gate stage number rule analysis means, and a logic circuit F/F gate stage number rule result output means.
Since a large capacity memory is required to store the logic circuit connection information in order to perform the inter-F gate stage number rule analysis, the scale of the logic circuit that can be analyzed is limited.

[Problem to be solved by the invention]

In the conventional logic circuit F/F gate stage number rule analysis method described above, logic circuit connection information is stored in only one layer, and logic circuit F/F gate stage number rule analysis for large-scale logic circuits is not possible. Since a large capacity memory is required to store the logic circuit connection information, there is a drawback that the scale of the logic circuit that can be analyzed is limited.

An object of the present invention is to provide a logic circuit F that can be used even for large-scale logic circuits without limiting the scale of logic circuits that can be analyzed.
An object of the present invention is to provide a gate stage number rule analysis method between /F.

[Means to solve the problem]

The F/F gate stage number rule analysis method for a logic circuit according to the present invention includes an in-block gate stage number information storage means for storing gate stage number information for each block, which is basic in the F/F gate stage number rule analysis for a logic circuit; Logic circuit connection information storage means for storing logic circuit connection information of a large-scale logic circuit in logically organized functional description units (modules), and modules existing in the logic circuit connection information storage means in lower hierarchy modules; Logic circuit connection information for one module in the logic circuit connection information storage means selected by the hierarchy control means and stored in the in-block gate stage number information storage means. Selected by the logic circuit F/F gate stage number rule analysis means that analyzes the gate stage number rule between the F/Fs of the logic circuit based on the gate stage number information for each block and specifies the part that is the target of the error, and the hierarchical control means. One module is regarded as one block based on the logical circuit connection information for one module in the logic circuit connection information storage means and the gate stage number information for each block stored in the in-block gate stage number information storage means. gate stage number information automatic generation means for generating stage number information and storing it in the in-block gate stage number information storage means; and the logic circuit F.
Logic circuit F/F gate stage number rule analysis result output means for outputting information on a part targeted by an error specified by the F/F gate stage number rule analysis means.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of the present invention. The in-block gate stage number information storage means 1 stores gate stage number information for each block, which is the basis for the F/F gate stage number rule analysis in logic circuits, and the logic circuit connection information storage means 2 stores logic circuit connections of large-scale logic circuits. Information is stored in logically organized functional description units (modules).

The hierarchy control means 3 controls the modules existing in the logic circuit connection information storage means 2 to process the modules from the lower hierarchy, and the logic circuit F/F gate stage number rule analysis means 4 is selected by the hierarchy control means 3. The number of gate stages between F and F of the logic circuit is determined from the logic circuit connection information for one module in the logic circuit connection information storage means 2 and the gate stage number information for each block stored in the in-block gate stage number information storage means 1. Perform rule analysis and specify the part that caused the error.

The gate stage number information automatic generation means 5 generates logic circuit connection information for one module in the logic circuit connection information storage means 2 selected by the hierarchy control means 3 and for each block stored in the in-block gate stage number information storage means 1. Gate stage number information is generated based on the gate stage number information in which one module is regarded as one block, and is stored in the gate stage number information storage means 1 in the block, and the gate stage number rule analysis result output means 6 between logic circuit F/Fs Interval gate stage number rule analysis means 4
Outputs information about the part that caused the error specified in .

FIG. 2, FIG. 3, and FIG. 4 are diagrams showing one embodiment of the present invention.

FIG. 2 shows a logic circuit diagram that is a target of the logic circuit F/F gate stage number rule analysis. Logic circuit connection information storage means 2
stores the logic circuit connection information of the logic circuit diagram 7 in logic circuit diagrams 8, 9, and 10 of logically organized functional description units (modules).

The details of each F/F symbol 57,58 in module 8 are enclosed by dotted lines in module 7.

FIG. 3 shows that the hierarchical control means 3 is connected to the logic circuit connection information storage means 2.
Logic circuit F/F gate stage number rule analysis for module 9 in the order of 9.10.8 4.1. Analysis of logic circuit F/F gate stage number rule for module 10 4.2. Logic circuit F/F gate stage number rule analysis 4.3 for module 8, module 9
automatic generation of gate stage number information in a block for module 5.1, automatic generation of gate stage number information in a block for module 10, automatic generation of gate stage number information in a block for module 10, and output of gate stage number rule analysis results between logic circuits F/F for module 9.10 in the lower hierarchy 6.
1 is a diagram showing the flow of controlling the process of outputting the logic circuit F/F gate stage number rule analysis result 6.2 for the upper layer module 8.

FIG. 4 shows the gate stage number information of the block stored in the in-block gate stage number information storage means 1, the 65th group shows the initial gate stage number information of each block as the initial state storage information, and the 66th group shows the in-block gate stage number. Automatic information generation 5
Group 66 is a diagram showing the gate stage number information of the module block 57 generated by the in-block gate stage number information automatic generation means 5.

The logic circuit F/F gate stage number rule analysis means 4 is a module 9 stored in the logic circuit connection information storage means 2.
Analyzing the number of gate stages between logic circuits F/F using the logic circuit connection information and the gate stage number information for each block stored in the in-block gate stage number information storage means 1 (4
,1).

If the number of gate stages between F/F is set to 3 or more,
The number of gates between the output terminal 30 of the F/F symbol 15 and the input terminal 31 of the F/F symbol 16 is insufficient.
The input terminal 31 of the /F symbol 16 is designated as the error target part.

The in-block gate stage number information automatic generation means 5 combines the logic circuit connection information of the module 9 stored in the logic circuit connection information storage means 2 and the in-block gate stage number information storage means 1.
Based on the gate stage number information for each block stored in the block, gate stage number information is generated in which the modules 9 shown in the group 66 in FIG. Then, the logic circuit connection information of the module 10 stored in the logic circuit connection information storage means 2 and the number of gate stages in a block information storage means 1 are stored.
Analysis of gate stage number rules between logic circuits F/F for logic circuits based on gate stage number information for each block stored in
4.2) Automatic generation of information on the number of gate stages in a block (5゜2)
).

Finally, from the logic circuit connection information of the module 8 stored in the logic circuit connection information storage means 2 and the gate stage number information for each block stored in the in-block gate stage number information storage means 1, the logic circuit for the highest level logic circuit is determined. Perform inter-F/F gate stage number rule analysis (4, 3).

If the number of gate stages between F/F is set to 3 or more,
F/F in the lower hierarchy within the output terminal 60 of the F/F symbol 57
The number of gates between the output terminal 29 of the symbol 15 and the input terminal 49 of the F/F symbol 17 in the lower hierarchy in the input terminal 62 of the F/F symbol 58 and the F/F in the lower hierarchy in the output terminal 61 of the F/F symbol 57 Output terminal 32 of F symbol 16
and F/F symbol 58 input terminal 63 lower layer F/
The number of gates between the input terminals 50 of the F symbol 18 is insufficient, and the output terminal 60 of the F/F symbol 57 is
The output terminal 29 of the F/F symbol 15 in the inner lower layer and the F/F symbol 15
49 input terminals of the F/F symbol 17 in the lower hierarchy in the input terminal 62 of the F symbol 58 and the output terminal 32 of the F/F symbol 16 in the lower hierarchy in the output terminal 61 of the F/F symbol 57 and the F/F symbol 58 The area between the terminals of the F/F symbol 18 in the lower hierarchy within the input terminal 63 of is designated as the error target part.

Output the logic circuit F/F gate stage number rule analysis result (6, 1) for the lower layer modules 9 and 10, and
F/F symbol 1 from output terminal 3o of /F symbol 15
6 outputs information about the connection between the input terminal 27 of the external input terminal 12 of the input terminal 31 and the output terminal 30 of the F/F symbol 15, and connects the logic circuit F/F to the upper layer module 8.
Output the analysis result of the gate stage number rule (6, 2),
F/F in the lower hierarchy within the l power terminal 60 of the F/F symbol 57
The output terminal 29 of the symbol 15, the input terminal 62 of the F/F symbol 58, the 49 input terminals of the F/F symbol 17 in the lower hierarchy, and the output terminal 61 of the F/F symbol 57 in the lower hierarchy F/F symbol 1 in the lower hierarchy within the output terminal 32 and the input terminal 63 of the F/F symbol 58
Outputs information between terminals of 8.

〔Effect of the invention〕

By employing the configuration described above, the present invention has the effect that the scale of the logic circuit to be analyzed is not limited, and therefore the F/F gate stage number rule can be analyzed even for large-scale logic circuits. .

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG.
FIG. 4 is a diagram showing details of this embodiment. 1... Boo, internal gate stage number information storage means, 2.
...Logic circuit connection information storage means, 3. Hierarchical control means, 4. Inter-logic circuit F/F gate stage number rule analysis means, 5. Intra-block gate stage number information automatic generation means, 6.
. . . Logic circuit F/F gate stage number rule analysis result output means, 7 to 10 . . . Logic circuit diagram (module).

Claims (1)

[Scope of Claims] Intra-block gate stage number information storage means for storing, for each block, gate stage number information that is basic in the analysis of the gate stage number rules between flip-flops in a logic circuit; a logic circuit connection information storage means for storing in function description units (modules); a hierarchy control means for controlling modules existing in the logic circuit connection information storage means so that processing is performed from a module in a lower hierarchy; Based on the logic circuit connection information for one module in the logic circuit connection information storage means selected by the control means and the gate stage number information for each block stored in the in-block gate stage number information storage means, the number of gate stages between the flip-flops of the logic circuit is determined. logic circuit flip-flop inter-gate stage number rule analysis means for performing gate stage number rule analysis and specifying a portion subject to an error; and one module's worth of logic in the logic circuit connection information storage means selected by the hierarchy control means. A gate that generates gate stage number information regarding one module as one block from circuit connection information and gate stage number information for each block stored in the in-block gate stage number information storage means and stores it in the in-block gate stage number information storage means. It is characterized by comprising: means for automatically generating stage number information; and means for outputting analysis result of gate stage number rule between logic circuit flip-flops for outputting information on a part targeted for error specified by the gate stage number rule analysis means between logic circuit flip-flops. An analysis method for the number of gate stages between flip-flops in a logic circuit.