KR0152710B1 - Control circuit of parallel neural network board for interfacing with at-bus - Google Patents

Abstract

The present invention relates to a control circuit of a parallel neural network board for controlling a large parallel processor system using an AT-bus of an IBM-PC, comprising 16 digital neural chips having a lattice structure and each having a specific address. IBM-PC which controls the number of processor boards 11 and the local bus communication between the neural chips in the processor board 11 and the global bus communication between the processor boards using a specific address assigned to each of the processor boards 11. It provides a control circuit of a parallel neural network board for mounting on the AT-Bus, characterized in that it provides an eclectic control structure for efficiently controlling a large-scale processor in a single processor system IBM-PC, including (10), The corresponding selected processor board address is assigned to the lower four bits of the address bus and the lower four bits of the data bus. A first comparator configured to compare the data with the data bus of the address bus outputted from the transmission means, and to output a result; A register for storing an address value of a corresponding board when the comparison data output from the first comparator is true; And a second comparator configured to compare a data stored in the register with an address value of a predetermined board, and output a board to be selected. Provide a circuit.

Description

Control circuit of parallel neural network board for mounting on AT-Bus

1 is the configuration of the whole system.

2 is an operation flowchart of a control circuit.

3 is a control circuit for board selection.

4 is a control circuit for chip and processor selection.

5 is a control circuit for on-line communication.

* Explanation of symbols for main parts of the drawings

10: IBM-PC 11: Chapter 8 Processor Boards

12, 15: digital nerve chip 13: local bus

14 global bus 30 NAND circuit

32: AT address bus 33, 41: AT data bus

36, 37: 4-bit comparator 38, 40, 50, 51: D-type flip-flop

54: power buffer

The present invention relates to a control circuit of a parallel neural network board for controlling a large parallel processor system using the AT bus of the IBM-PC.

In general, neural network models are the basic structures used when designing systems that resemble the human brain and nerve cells.

The system composed of such neural networks has non-deterministic characteristics like the human brain, so it can recognize slightly wrong or similar inputs.

Therefore, it is evaluated that it is very useful for image recognition and natural language processing in the field of artificial intelligence due to the above-mentioned features.

However, there are disadvantages in that it is not suitable for general calculations or logical inferences, and it has disadvantages in that large data processing is required.

In particular, the present theoretically suggests a sufficient possibility, but due to the limitations of large-scale data processing in real system implementation, a lot of difficulties in the system implementation.

In order to solve the above problems and implement a neural network system, a more detailed implementation of hardware is required, and most of the hardware adopts a digital method.

While the digital method described above has the advantage of being stable and easy to implement, it has a disadvantage that it is difficult to utilize parallelism, which is an advantage for neural networks.

In order to overcome the shortcomings of the digital method, a multiprocessor should be used, but this has a disadvantage in that control of the system is difficult.

However, the necessity of the control of the system has been the main concern of the neural network system since the necessity of using multiple processors is necessary for the large data processing required by the neural network.

As described above, an object of the present invention is to implement a neural network processor board using multiple processors to simulate a large scale neural network model and various neural network models in real time. It is to provide a control circuit of a parallel neural network board for mounting on AT-Bus.

A feature of the present invention for achieving the above object is, in the neural network system, consisting of 16 digital neural chips having a lattice structure, each of which has a predetermined number of processor boards 11 and the processor board 11 In the single processor system IBM-PC including the IBM-PC (10) for controlling the local bus communication between the nerve chip in the processor board 11 and the global bus communication between the processor board using a specific address assigned to each) To provide a metrology control structure for efficiently controlling a large processor.

Another feature of the present invention for achieving the above object is made of 16 digital nerve chips having a lattice structure, each of which is given to a predetermined number of processor boards 11 and processor boards 11 each having a specific address. In a neural network system having an IBM-PC 10 that controls local bus communication between neural chips in the processor board 11 and global bus communication between processor boards using an address, the address of the selected processor board is AT. Transmission means for carrying on the lower four bits of the address bus and the lower four bits of the data bus on the bus; A first comparator for comparing the data of the address bus output from the transmission means with the data bus and outputting a result; A register for storing an address value of a corresponding board when data output from the first comparator is true; And a second comparator for outputting that the board is selected by comparing the data stored in the register with an address value of a predetermined board.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

First, look at the prerequisites for achieving the object of the present invention.

First, a single processor, IBM-PC, must be able to effectively control a processor board with multiple processors.

Otherwise, the performance of the IBM-PC will depend on the performance of the processor board, effectively avoiding parallelism.

Second, the processor board is composed of 16 digital neural chips, digital neural chips, and digital neural chips consisting of four neural processors. So we can do the same or different operations on each neural processor.

Or, optionally, the processor may be stopped and only a specific processor may be operated.

In addition, some programs can be uploaded to finish the operation, and then only certain processors can upload and use other data or other programs.

The present invention configured to satisfy the above conditions and to control the multiple processors at high speed will be described below.

1 shows the configuration of a neural network system.

The system consists of an IBM-PC 10 and up to eight processor boards 11.

The number of processor boards is variable so only one can be used.

Each processor card has its own address, which is controlled by the IBM-PC.

The processor board 11 has 16 digital nerve chips, and the implemented operation is as follows.

The neural chip communicates data between neural processors (or between digital neural chips) on-line using the local bus 13 and off-line using the global bus 14. Up / down loading IBM-PC and data (including programs) in line.

Neural processors can communicate online to exchange data between processors, taking advantage of parallel processors.

In the on-line state, data communication is possible between the neural processor of one of the processor boards and the IBM-PC, and has an additional local bus 15 for this purpose.

This feature allows you to transfer the data you need from the outside to the processor board, and vice versa.

One digital neural chip has four digital neural processors (16)

It is a single-chip multiple processor (94, patent application 32940).

2 shows an operation flowchart of a processor board.

It shows the operation of the processor board in the initial 20 degree state.

For normal operation, the processor board, the digital nerve chip, and the processor must be selected in order, after which the up / down loading of data including the program takes place.

Through this process, the processor board program can be normally executed.

21 shows that after performing normal operation in step 20, the processor board can be hierarchically controlled so that other programs or other data can be repeatedly uploaded and used only on a specific board, chip, or processor.

This process is not effective and does not take advantage of multiple processors and spends a lot of time controlling the processor.

An example of the operation is as follows.

After the program execution of 20 is completed, all the conditions are the same as before. If you select only the board, select the board in the flow chart of 21 and if necessary, download the data (program) and then execute the program.

You don't have to choose chips, processors, etc.

As another example, if only the processor is selected again on the same board, the processor may be selected without performing the board selection and if necessary, after downloading data (program), the program may be executed.

3 is a circuit for selecting a processor board, the operation of which is as follows.

Select the processor board address in advance on the processor board.

The value 31 is the hardware chosen address on the board.

The maximum number of processor boards that can be controlled by the IBM-PC is 8, and a 4-bit board address 31 is required.

If addressed, the lower four bits (32) of the address bus and the lower four bits (33) of the data bus on the AT-bus of the IBM-PC carry the same value.

That is, the same value as that of the address 31 of the predetermined processor board is sent from the address bus 32 and the data bus 33 of the AT-bus.

In this case, the signal 35 is first outputted through the comparator 36, and the control signal capable of storing the address value of the board in the register 38 by using the nand gate 30 by using the signal. To store the same address value in register 38.

This value then enters comparator 37 and the address value 31 of the predetermined board is compared to generate a signal 34 indicating that the board has been selected.

If the IBM-PC generates a different value on the address bus and data bus than the board's address value (31), the processor board cannot be selected.

4 is a circuit for selecting a digital neural chip on a processor board and four neural processors on a digital neural chip. The register 40 for selection 42 of the digital neural chip on the processor board and selection 43 of the neural processor on the digital neural chip is shown.

The signal 44 for storing in the receiver 40 is generated using the 34 signal.

That is, the signal 44 is generated only when the processor board is selected first.

The digital neural chip on the processor board is selected respectively, and the signal 43 for selecting the neural processor is selected by being connected to all the digital neural chips on the processor board.

In doing so, it simply controls the entire processor without having to select all neural processors. If a neural chip is not selected, the neural processor does not operate even when the neural chip is selected.

5 shows a circuit for data communication between a neural processor and an IBM-PC in an on-line state.

The signal used here is based on the signal from the digital nerve chip, so you can refrain from the patent.

These circuits allow for on-line reads of data from the processor and external data to the processor board.

The time spent for this communication depends on the operating speed of the neural chip.

Features of the control circuit according to the present invention designed as described above are as follows.

1. Using the AT-bus from IBM-PC, a single processor system, can effectively control a large parallel processor system.

2. Using the method of instrumentally controlling the processor board, select the processor board first, the digital nerve chip second, and the neural processor, as shown in 20.

3. When the processor board is controlled by this structure, the system can be used while the data is uploaded and downloaded while arbitrarily selecting only the processor board or digital neural chip or neural processor necessary for performing the repetitive operation, thereby simplifying the control. have.

4. The control circuit can upload / download data (program) between the processor board and IBM-PC in the off-line state by using the above hierarchical control method.

5. In the on-line state, there is a circuit for data communication with a neural processor using an AT-bus.

Claims (4)

In the neural network system, the processor board is formed by using a predetermined number of processor boards 11 each having a specific address and a specific address assigned to each of the processor boards 11 having a grid structure having 16 digital neural chips. A hierarchical control structure for efficiently controlling a large-scale processor in a single processor system, IBM-PC, including the IBM-PC (10) that controls local bus communication between neural chips and global bus communication between processor boards in (11). The control circuit of the parallel neural network board for mounting on the AT-Bus, characterized in that provided. 2. The neural chip of claim 1, wherein the neural chip communicates data between neural processors (or digital neural chip) in an on-line state using a local bus, and communicates with the IBM-PC in an off-line state using a global bus. A control circuit of a parallel neural network board for mounting on an AT-Bus, characterized by uploading and downloading data. The control circuit of claim 1, wherein the digital neural chip is a single chip multiprocessor composed of four neural processors. It consists of 16 digital neural chips having a lattice structure, and each of the neural chips in the processor board 11 by using a predetermined number of processor boards 11 and a specific address assigned to each of the processor boards 11 each having a specific address. In a neural network system having an IBM-PC 10 that controls local bus communication between the bus and global bus communication between the processor boards, the address of the selected processor board is assigned to the lower four bits of the address bus and the data bus on the AT-bus. Transmission means for carrying on the lower four bits of the transmission unit; A first comparator for comparing the data of the address bus output from the transmission means with the data bus and outputting a result; A register for storing an address value of a corresponding board when the comparison data output from the first comparator is true; And a second comparator configured to compare a data stored in the register with an address value of a predetermined board, and output a board to be selected. Circuit.