JP2009038079A - Designing method and designing device for semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a designing method and a designing device for a semiconductor integrated circuit that generate an arrangement and wiring result such that yield improvement processing of precision level differing with areas on a chip is easily applied. <P>SOLUTION: The designing method includes an initial arrangement step of initially arranging a semiconductor integrated circuit according to chip information, a chip area division step of dividing the semiconductor chip into a plurality of areas, a timing criticality calculation step of calculating timing criticality based upon the chip information, and a yield improvement processing precision level setting step of setting a precision level of yield improvement processing for each of the divided areas based upon the timing criticality calculated in the timing criticality calculation step. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a design method and design apparatus for a semiconductor integrated circuit, and more particularly to a design method and design apparatus for designing a semiconductor integrated circuit in consideration of manufacturability of the semiconductor integrated circuit.

  When manufacturing semiconductor integrated circuits, optical proximity correction (OPC) and chemical mechanical polishing (CMP) of wiring metal are used as techniques for increasing the manufacturing yield by controlling the wiring shape change during wiring pattern exposure. For example, dummy metal insertion has been proposed to realize wafer flattening during chemical mechanical polishing / planarization.

  The optical proximity effect correction is performed in order to maintain the shape at the bent portion of the wiring, and the bent portion is made larger than the straight portion. The dummy metal is inserted in order to prevent the wiring structure from being varied by CMP, and the dummy metal is inserted in order to make the wiring density in a predetermined region constant.

  Originally, it is desirable to determine the degree of shape correction and the degree of dummy metal insertion when designing a semiconductor integrated circuit by simulating an exposure simulation and a CMP process, but this requires a huge amount of processing time. For this reason, it is common to prepare a predetermined rule in consideration of the shape of the adjacent wiring in advance, and perform wiring shape correction and dummy metal insertion after the layout wiring design based on this rule. At this time, it is difficult to apply different rules depending on the location on the chip because the complexity of processing increases, and the same rule is generally applied to the entire chip.

  FIG. 8 is a diagram illustrating an example in which the manufacturing facilitation technology is applied to the layout wiring design, and is a diagram illustrating the layout wiring design when a path between the flip-flops 201 is formed.

  A path 209 including three gate elements 205 is formed in the region 206, a path including three gate elements 205 and a path 210 including one gate element 205 are formed in the region 207, and two gates are formed in the region 208. A path including the element 205 is formed. The bent portion of the path is a corrected wiring 204 that has been corrected, and a dummy metal 203 is inserted to keep the wiring density constant.

  The same rule is applied to the entire chip in the yield improvement processing such as the wiring shape correction processing and dummy metal insertion processing. Here, for simplicity, a path with a large number of logic gate elements between flip-flops is a path with a large delay. A path with a large delay is also called a path with a critical timing or a path with a high timing criticality. Hereinafter, the flip-flop is also called FF.

  The same rule is applied to the processing for each area 206-208. For this reason, when it is assumed that the process for the path including two gate elements is an appropriate process, the path 209 including three gate elements is a path in which a process for improving the yield is insufficient, and a path including one gate element. 210 is a path in which excessive processing for improving yield is performed.

  In recent fine manufacturing processes, it is necessary to perform shape correction and metal insertion in consideration of not only adjacent wiring shapes but also a wider range of peripheral wiring shapes. However, it is practically impossible to prepare the rules for shape correction and metal insertion in advance considering all the arrangement and wiring patterns because the number of rules becomes enormous. As a countermeasure to this problem, there is a method of performing optimal shape correction and metal insertion by capturing the influence of surrounding wiring shape more widely and accurately by using simple models of exposure simulation and CMP process simulation at the time of design. Although being introduced, it is difficult to apply this method to the entire surface of the chip in terms of calculation time.

  Originally, the timing criticality of the path between flip-flops in the chip varies depending on the location on the chip, and it is not necessary to perform the manufacturing yield improvement process with the same rule or the same simulation model on the entire chip. In other words, high-accuracy rules or simulation models are applied to areas related to critical paths where manufacturing variations have a significant impact on yield, while manufacturing yields using conventional simple rules are applied to areas that do not include critical paths. It is sufficient to perform the improvement process.

  As described above, performing the manufacturing yield improvement process on the entire chip with the same rule or the same simulation model may lead to the result that the yield improvement process becomes excessive or insufficient depending on the location on the chip. There is sex. Based on such an idea, Patent Document 1 (Japanese Patent Laid-Open No. 2006-252544) discloses a technique for locally changing the yield improvement processing rules based on the placement and routing results.

Further, in Patent Document 2 (Japanese Patent Laid-Open No. 2007-12687), after the placement and wiring design, the chip area is divided into a lattice shape, the manufacturability is evaluated, and the yield improvement rule is applied to the low reliability area. There has been proposed a method of resetting and performing relocation wiring design.
JP 2006-252544 A JP 2007-12687 A

  As described above, it is impossible to express the behavior of recent fine process wiring exposure and CMP processing by one simple rule in the yield improving process in which one conventional simple rule is applied to the entire surface of the chip. Therefore, there is a problem that a sufficient yield improvement effect cannot be obtained in terms of accuracy.

  Yield improvement processing based on a highly accurate simulation model is being introduced, but such a method is difficult to apply to the entire surface of the chip in terms of processing time.

  Based on the result of placement and routing, the method to locally change the yield improvement processing method, or the chip area is divided into a grid and the manufacturability is evaluated, and the yield improvement rule is applied to the area with low reliability. Methods have been proposed to reset and place and route designs again. In these methods, as shown in FIG. 9, there are mixed timing critical paths and non-critical paths in the entire chip. If distributed, the area where the rule is changed locally, or the area where the relocation wiring design is performed will cover the entire chip surface, so the yield improvement processing based on a highly accurate simulation model is limited to the area. There is a problem that it is difficult to apply limitedly or to divide a chip area and apply a yield improvement process with a different accuracy level for each area. .

  Let us consider a state in which paths with critical timing are dispersed in a plurality of areas, using the example shown in FIG.

  A region 1001 in FIG. 9 includes a path including three gate elements, a region 1002 includes two paths including two gate elements, and a region 1003 includes a path including two gate elements. Shall be formed.

  FIGS. 10A to 10C are diagrams showing path delay distributions when the yield improvement processing with the same accuracy is applied to the regions 1001 to 1003. In each figure, the vertical axis represents the number of paths between FFs, and the horizontal axis represents the delay amount of paths between FFs. Each region has the same timing constraint because the yield improving process with the same accuracy is applied. Further, the delay amount is maximized when the number of paths between FFs is a predetermined number, and a normal distribution is achieved in which the number of paths at the delay amount is maximized.

  Originally, high-accuracy yield improvement processing to suppress variation is applied to paths with critical timing, and low-accuracy yield improvement processing is appropriately applied to paths with non-critical timing. However, in the conventional design method, as shown in FIG. 10, since timing critical paths are distributed in each region, it is necessary to apply yield improvement processing with the same accuracy over the entire chip surface. However, there is a possibility that the yield improvement processing may be excessive or insufficient due to the inter-flip-flop path, or a huge processing time is required.

  The present invention has been made in view of the problems of the conventional techniques as described above, and does not use the same rule or simulation model for the entire surface of the chip, but improves the yield at different accuracy levels depending on the area on the chip. It is an object of the present invention to provide a semiconductor integrated circuit design method and design apparatus that generate a placement and routing result that is easy to apply processing.

A method for designing a semiconductor integrated circuit according to the present invention includes a semiconductor integrated circuit on a semiconductor chip based on chip information including component information, wiring connection information, and timing constraints between flip-flops in a semiconductor integrated circuit to be designed. A method of designing a semiconductor integrated circuit for designing a circuit,
An initial placement step for initial placement of the semiconductor integrated circuit based on the chip information;
A chip area dividing step of dividing the semiconductor chip into a plurality of areas;
A timing criticality calculating step for calculating a timing criticality based on the chip information for each of the regions divided in the chip region dividing step;
Yield improvement processing accuracy level setting step for setting the accuracy level of the yield improvement processing based on the timing criticality calculated in the timing criticality calculation step for each of the divided areas;
including.

A semiconductor integrated circuit design apparatus according to the present invention includes a semiconductor integrated circuit on a semiconductor chip based on chip information including component information, wiring connection information, and timing constraints between flip-flops in a semiconductor integrated circuit to be designed. A semiconductor integrated circuit design apparatus for designing a circuit,
Initial placement means for performing the initial placement of the semiconductor integrated circuit based on the chip information;
Chip area dividing means for dividing the semiconductor chip into a plurality of areas;
Timing critical degree calculating means for calculating a timing critical degree based on the chip information for each of the areas divided by the chip area dividing means,
Yield improvement processing accuracy level setting means for setting the accuracy level of the yield improvement processing based on the timing criticality calculated by the timing criticality calculation means for each of the divided areas;
including.

  According to the above invention, the chip is divided into a plurality of areas, the target timing criticality of each area is set according to the placement and routing result, and the criticality of the flip-flop path included in each area is set in the area. Placement and routing and physical synthesis are performed so as to approach the set target timing criticality. Placement and routing and physical synthesis with the target timing step and target timing criticality of the region as constraints are repeated alternately, and finally the target timing criticality of each region and the timing criticality of the flip-flop paths included in that region are determined. The process ends when the error is within the allowable range. As a result, the chip is divided into a plurality of areas having different timing criticalities, and each flip-flop path that matches the timing criticality of the area is arranged in each area. That is, as shown in FIG. 2, the paths between the flip-flops are classified according to the timing criticality and are aggregated and arranged by region. As a result, the path delay distribution of each region is adapted to the target timing criticality set for each region as shown in FIG. 3, and the yield improvement processing with different accuracy levels depending on the regions on the chip is applied. Is possible.

  According to the present invention, a chip is divided into a plurality of areas, different timing criticalities are assigned to the respective areas, and the placement and routing in which the criticality of the inter-flip-flop path included in each area falls below the timing criticality of the corresponding area Can be generated, and it is possible to apply the yield improvement processing with different accuracy levels suitable for the corresponding timing criticality for each region.

  Next, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of an embodiment of a design apparatus according to the present invention.

  In this embodiment, a chip information input unit 101, a gate initial arrangement unit 102, a timing analysis unit 103, a gate timing critical degree calculation unit 104, a chip area division unit 105, a timing critical degree calculation unit 106 for each area, Target timing criticality assignment means 107, timing error determination means 108 for each area, gate destination area setting means 109, gate relocation means 110, rephysical synthesis means 111 for each area, and yield improvement processing accuracy for each area The level setting means 112 is comprised.

  The present embodiment is configured by a general computer including a control device, a storage device, an input device, and a display device. These parts are not shown. Each of the above means is constructed and controlled on a storage device such as a ROM or a RAM by a control device that operates according to a program stored in the storage device.

  Each of the above-described means generally operates as follows.

  The chip information input unit 101 stores information (chip data) related to the gate level netlist of the semiconductor integrated circuit chip to be designed together with path delay constraint information between flip-flops (specifically, gate initial arrangement unit). 102).

  The gate initial arrangement means 102 is a component in an integrated circuit chip based on chip data received from the chip information input means 101 (specifically, component information and connection information between components) and path delay constraint information between flip-flops. (Logic gates and flip-flops) are arranged in the chip arrangement area, and an initial arrangement result is generated. As a means for generating this arrangement, an existing arrangement means that has been proposed in the past can be used.

  The timing analysis unit 103 calculates a path delay between flip-flops based on the initial arrangement result. The timing analysis means 103 can be an existing timing analysis means that has been proposed conventionally.

  The gate timing criticality calculating means 104 calculates the timing criticality of each gate on the path based on the path delay result between the flip-flops. Specifically, for example, a high timing critical degree is assigned to a gate on a path having a high timing critical degree.

  The chip area dividing means 105 sets a dividing line that divides the entire chip area where the logic gates and flip-flops are temporarily arranged into a plurality of lattice-shaped areas (lattices). The size of the grid is given from the outside by the designer.

  The timing criticality calculation means 106 for each region calculates the timing criticality of each region based on the timing criticality of the gate included in the corresponding region. Specifically, for example, an average value of the timing criticality of the gates included in the corresponding region is assigned as the timing criticality of the corresponding region.

  Based on the timing criticality of each area, the target timing criticality allocating means 107 for each area sets a target timing criticality that serves as an index for subsequent rearrangement and rephysical synthesis in each area. Specifically, for each region, a value obtained by multiplying the timing criticality of the corresponding region by a certain value is set as the timing constraint of the corresponding region.

  The timing error determination unit 108 for each region calculates an error between the target timing criticality of each region and the current timing criticality. If the error is smaller than the threshold, the yield improvement processing accuracy level setting unit 112 for each region Pass the area division information and the current timing criticality of each area. If the error is larger than the threshold value, the target timing critical degree and the current timing critical degree are transferred to the gate movement destination setting means 109 or the re-physical synthesis means 111 of each area.

  The gate movement destination area setting means 109 sets the movement destination area of each gate based on the target timing criticality of each area and the current timing criticality of each gate. Specifically, for each gate, an area where the target timing criticality is close to the current timing criticality of the gate and the distance from the current position of the gate is close is the movement destination area of the gate.

  The gate rearrangement unit 110 rearranges the gates in consideration of the gate destination areas obtained by the gate destination area setting unit 109 in addition to the connection relation between the gates.

  The re-physical synthesis unit 111 for each area performs physical synthesis (combination optimization of arrangement and logic change) again based on the target timing criticality set for each area. As the rephysical synthesis means, conventionally proposed rephysical synthesis means can be used.

  Yield improvement processing accuracy level setting means 112 for each region is a means (not shown) for setting the required yield improvement processing accuracy level for each region based on the timing criticality of each region and performing subsequent yield improvement processing. Pass information. Conventionally proposed means can be used for the yield improving process itself.

  Next, the operation of this embodiment will be described with reference to FIGS.

  By the chip information input means 101, the gate initial arrangement means 102 is inputted with information (chip data) on the gate level netlist of the semiconductor integrated circuit chip to be designed and timing constraint information between the flip-flops. The means 102 (specifically, the storage device) outputs an initial arrangement result in which the logic gates and flip-flops in the integrated circuit chip are arranged in the chip arrangement area.

  FIG. 2 is a diagram showing an output example of the initial placement result 601 output by the gate initial placement means 102. The initial arrangement result 601 becomes an input for the subsequent arrangement improving means.

  In FIG. 2, the numbers associated with each gate indicate the timing criticality, and the greater the timing criticality, the more critical the timing is, that is, the greater the delay is on the path.

  The timing analysis unit 103 and the gate timing criticality calculation unit 104 analyze the inter-flip-flop path delay on the chip and calculate the timing criticality of each gate described above. Assuming that the number of logic gate stages between the flip-flops is three, the timing critical degree is 3 for the gates on the path with the logic gate stage number 3, the criticality is 2 for the gates on the path with the number of logic gate stages 2. A criticality of 1 is assigned to a gate on a path having a stage number of 1. When the path is complicatedly involved, the gate timing criticality calculation means 104 can use the existing means already proposed.

  Next, according to the path delay between flip-flops and the timing criticality of each gate, the chip area dividing means 105, the timing criticality calculating means 106 for each area, and the target timing criticality assigning means 107 for each area are used to set the path. A region to be arranged is determined.

  FIG. 3 is a diagram illustrating an example of a path arrangement area. As shown in FIG. 3, the chip area is divided, and the criticality and target timing criticality index of each area are set. As the criticality level, an average value of criticality levels of the logic gates included in each area is set as the timing criticality level of the corresponding area. The target timing criticality index is calculated based on the current timing criticality. Here, the current timing criticality is used as it is as the target timing criticality index.

  A timing criticality level 3 and a target timing criticality index 3 are set for the area 701 shown in FIG. Timing criticality 2.5 and target timing criticality index 2.5 are set for area 702, and timing criticality 2 and target timing criticality index 2 are set for area 703.

  The timing error determination means 108 of each area compares the initial placement result 601 shown in FIG. 2 with the criticality degree of each area of each placement area shown in FIG. If the threshold value is smaller than the predetermined threshold value, the current timing criticality level is transferred to the yield improvement processing accuracy level setting unit 112 of each area. If the threshold value is larger than the predetermined threshold value, the target timing criticality level is To the destination setting unit 109 or the re-physical synthesis unit 111 of each area.

  If the threshold value for error determination is 0, there is a gate having a criticality different from the target timing criticality index of the region in the region 702 in FIG. It is transferred to the re-physical synthesis means 111 of the area.

  When the data is transferred from the timing error determination unit 108 of each area to the gate movement destination area setting unit 109, the gate movement destination area setting unit 109 sets the current belonging area and adjacent to each gate. Among the areas to be processed, the area where the target timing criticality index is closest to the gate timing criticality is set as the movement destination of each gate.

  FIG. 4 is a diagram showing the setting of the movement destination of each gate by the gate movement destination area setting means 109.

  In FIG. 4, the region 701 is set as the destination of the logic gate and flip-flop on the path of the logic gate stage number 3 in the region 702, and the destination of the logic gate and flip-flop on the path of the logic gate stage number 1 in the region 702 is set. An area 703 is set. The other logic gates and flip-flops move to the current area.

  The gate rearrangement unit 110 rearranges the gates in consideration of the gate destination areas set by the gate destination area setting unit 109 in addition to the connection relationship between the gates.

  In FIG. 4, the attractive force from the region 701 is applied to the gate on the path of the logic gate stage number 3 in the region 702, and the attractive force from the region 703 is applied to the gate on the path of the logic gate stage number 1 in the region 702. Rearrange the entire surface. An attractive force from the region to which the current region belongs is applied to gates other than the gates on the path of the logic gate stage number 3 and 1 in the region 702.

  FIG. 5 is a diagram showing the result of the rearrangement by the gate movement destination area setting unit 109 and the gate rearrangement unit 110.

  As shown in FIG. 5, a path with three logic gate stages is arranged in the area 701, and a path with one logic gate stage and two logic gate stages is arranged in the area 703. If this result is passed again from the timing analysis means 102 to the gate movement destination area setting means 109, the area 702 is set as a movement destination candidate at the gate on the path having the gate stage number 1 in the area 703 shown in FIG. The other gate moving destination candidate areas are the same as the areas to which the current gate belongs.

  In this state, when the rearrangement of the entire chip surface is performed again, as shown in FIG. 6, the target timing criticality index of each area and the timing criticality of the gates arranged in the corresponding area are matched. The timing error determination means 108 of each area determines that the arrangement improvement processing is completed, and the area division result and the target timing criticality index of each area are passed to the yield improvement processing accuracy level setting means 112 of each area.

  The yield improvement processing accuracy level setting means 112 for each region sets the yield improvement processing accuracy level for each region based on the target criticality index for each region. That is, a high-accuracy yield improvement processing accuracy level is set for the region 701 with a high target criticality index, and a low-accuracy yield improvement processing accuracy level is set for the region 703 with a low target criticality index. However, an intermediate yield improvement processing accuracy level is set in these intermediate regions 702.

  When the data is transferred from the timing error determination unit 108 of each area to the re-physical synthesis unit 111 of each area, the re-physical synthesis unit 111 of each area is set by the target timing criticality assignment unit 107 of each area. Using the target timing criticality as a timing constraint, re-physical synthesis (combination optimization of arrangement and logic change) is performed for each region.

  In the 5-pass arrangement area shown in FIG. 3, the area 701 has a target timing criticality level 3, the area 702 has a timing criticality level 2.5, and the area 703 has a target timing criticality level 2. In this state, When rephysical synthesis is performed for each area by the rephysical synthesis unit 111 for each area, as shown in FIG. 9, the path included in the area 1001 has a timing criticality level 3 and the path included in the area 1002 has a timing criticality level 2 The timing criticality of the path included in the area 1003 may be 2.

  As shown in FIG. 6, the yield improvement processing accuracy level setting unit 112 for each region sets the yield improvement processing accuracy level for each region according to the current timing criticality. In FIG. 6, the area 701 is assigned a high accuracy level, the area 702 is assigned a low accuracy level, and the area 703 is assigned a medium accuracy level. Chip information input means 101, gate initial arrangement means 102, timing analysis means 103, gate timing criticality calculation means 104, chip area dividing means 105, timing criticality calculation means 106 for each area, target timing criticality allocation for each area Means 107, timing error determination means 108 for each area, gate destination area setting means 109, gate relocation means 110, re-physical synthesis means 111 for each area, and yield improvement processing accuracy level setting means 112 for each area. Assign different timing criticality to each area, and create placement and routing that makes the criticality of the path between flip-flops included in each area less than or equal to the timing criticality of the corresponding area. Suitable for It is possible to apply the yield enhancement of different accuracy levels.

  FIGS. 7A to 7C are diagrams illustrating path delay distributions when the yield improving process with the accuracy according to the timing critical degree described above is applied to the regions 701 to 703.

  Different maximum delays are set for the paths arranged in the areas 701 to 703, and the arrangement design is performed so as to be within this maximum delay.

  Note that the timing error determination unit 108 of each region compares the initial placement result 601 with the criticality of each region of each placement region and the target timing criticality index, and the difference between them is greater than a predetermined threshold value. The target timing criticality is transferred to the gate movement destination setting unit 109 or the re-physical synthesis unit 111 of each area. It is good also as delivering to the physical synthesis means 111 alternately.

  Also, a second threshold value is set, and when the difference between the initial placement result 601 and the criticality of each area of each placement area and the target timing criticality index is larger than the second threshold value, the gate movement destination setting means 109 If it is small, it may be transferred to the re-physical synthesis unit 111 of each area, or vice versa.

It is a block diagram which shows the structure of one Example of the design apparatus by this invention. It is a figure which shows the example of an output of the initial arrangement result 601 which the gate initial arrangement means 102 outputs. It is a figure which shows an example of the arrangement | positioning area | region of a path | pass. It is a diagram showing the setting of the movement destination of each gate by the gate movement destination area setting means 109. It is a figure which shows the result of the rearrangement by the gate movement destination area | region setting means 109 and the gate rearrangement means 110. FIG. It is a figure which shows the rearrangement result of the whole chip surface. (A)-(c) is a figure which shows path delay distribution when the yield improvement process of the precision according to the timing critical degree mentioned above is applied with respect to the area | regions 701-703 in FIG. It is a figure which shows an example which applied the manufacture simplification technique to the layout wiring design. It is a figure which shows the state from which a critical path | route and a non-critical path | route are mixed and distributed in the whole chip | tip. (A)-(c) is a figure which shows path delay distribution when the yield improvement process of the same precision is applied with respect to the area | regions 1001-1003 in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Chip information input means 102 Gate initial arrangement means 103 Timing analysis means 104 Gate timing critical degree calculation means 105 Chip area division means 106 Timing critical degree calculation means for each area 107 Target timing criticality assignment means for each area 108 Timing error determination means 109 Gate destination area setting means 110 Gate relocation means 111 Rephysical synthesis means for each area 112 Yield improvement processing accuracy level setting means for each area

Claims (10)

A semiconductor integrated circuit design method for designing a semiconductor integrated circuit on a semiconductor chip based on chip information including component information, wiring connection information, and timing constraints between flip-flops in a semiconductor integrated circuit to be designed Because
An initial placement step for initial placement of the semiconductor integrated circuit based on the chip information;
A chip area dividing step of dividing the semiconductor chip into a plurality of areas;
A timing criticality calculating step for calculating a timing criticality based on the chip information for each of the regions divided in the chip region dividing step;
Yield improvement processing accuracy level setting step for setting the accuracy level of the yield improvement processing based on the timing criticality calculated in the timing criticality calculation step for each of the divided areas;
A method for designing a semiconductor integrated circuit including: The method for designing a semiconductor integrated circuit according to claim 1,
Target timing criticality assignment step that is performed after the timing criticality calculation step and sets a target timing criticality index for each region based on the timing criticality of each region calculated in the timing criticality calculation step When,
Timing error determination step for determining whether the error of the timing criticality and the target timing criticality index is larger than a predetermined threshold for each of the regions,
This is performed when it is determined in the timing error determination step that the error between the timing criticality and the target timing criticality index is larger than a predetermined threshold, and the timing critical of gates arranged in each region A destination area setting step for generating destination area information of each gate so that the degree and the target timing critical degree are close,
A gate rearrangement step for performing gate rearrangement in consideration of the movement destination area information of each gate, and
After the gate rearrangement step, the steps after the timing criticality calculation step are performed, and the yield improvement processing accuracy level setting step includes an error between the timing criticality and the target timing criticality index in the timing error determination step. A method for designing a semiconductor integrated circuit, which is performed when it is determined that is smaller than a predetermined threshold value. The method for designing a semiconductor integrated circuit according to claim 1,
Target timing criticality assignment step that is performed after the timing criticality calculation step and sets a target timing criticality index for each region based on the timing criticality of each region calculated in the timing criticality calculation step When,
Timing error determination step for determining whether the error of the timing criticality and the target timing criticality index is larger than a predetermined threshold for each of the regions,
It is performed when it is determined in the timing error determination step that an error between the timing criticality and the target timing criticality index is larger than a predetermined threshold, and the target timing criticality index of each area is determined. A re-physical synthesis step for performing re-physical synthesis for each region as a timing constraint, and
After the re-physical synthesis step, the steps after the timing critical degree calculation step are performed, and the yield improvement processing accuracy level setting step includes an error between the timing critical degree and the target timing critical degree index in the timing error determination step. A method for designing a semiconductor integrated circuit, which is performed when it is determined that is smaller than a predetermined threshold value. The method for designing a semiconductor integrated circuit according to claim 1,
Target timing criticality assignment step that is performed after the timing criticality calculation step and sets a target timing criticality index for each region based on the timing criticality of each region calculated in the timing criticality calculation step When,
Timing error determination step for determining whether the error of the timing criticality and the target timing criticality index is larger than a predetermined threshold for each of the regions,
A destination area setting step for setting the destination area of each gate so that the criticality level of the gate arranged in each area and the target timing criticality level are close to each other;
Gate rearrangement step for performing gate rearrangement in consideration of the movement destination area information of each gate,
Rephysical synthesis step for performing rephysical synthesis for each region using the target timing criticality index of each region as a timing constraint, and
In the destination area setting step, the gate rearrangement step, and the re-physical synthesis step, the error of the timing criticality and the target timing criticality index is larger than a predetermined threshold in the timing error determination step. Alternately when it is determined that
After the gate rearrangement step or the re-physical synthesis step, each step after the timing criticality calculation step is performed, and the yield improvement processing accuracy level setting step includes the timing criticality and the target timing in the timing error determination step. A method for designing a semiconductor integrated circuit, which is performed when it is determined that an error of a criticality index is smaller than a predetermined threshold. The method for designing a semiconductor integrated circuit according to claim 1,
Target timing criticality assignment step that is performed after the timing criticality calculation step and sets a target timing criticality index for each region based on the timing criticality of each region calculated in the timing criticality calculation step When,
Timing error determination step for determining whether the error of the timing criticality and the target timing criticality index is larger than a predetermined threshold for each of the regions,
A destination area setting step for setting the destination area of each gate so that the criticality level of the gate arranged in each area and the target timing criticality level are close to each other;
Gate rearrangement step for performing gate rearrangement in consideration of the movement destination area information of each gate,
Rephysical synthesis step for performing rephysical synthesis for each region using the target timing criticality index of each region as a timing constraint, and
The movement destination region setting step is performed when it is determined in the timing error determination step that an error between the timing criticality and the target timing criticality index is larger than a predetermined first threshold, The re-physical synthesis step is performed when it is determined in the timing error determination step that an error between the timing criticality and the target timing criticality index is larger than a predetermined second threshold;
After the gate rearrangement step or the re-physical synthesis step, each step after the timing criticality calculation step is performed, and the yield improvement processing accuracy level setting step includes the timing criticality and the target timing in the timing error determination step. A method for designing a semiconductor integrated circuit, which is performed when it is determined that an error of a criticality index is smaller than a predetermined first threshold value. A semiconductor integrated circuit design apparatus for designing a semiconductor integrated circuit on a semiconductor chip based on chip information including component information, wiring connection information, and timing constraints between flip-flops in a semiconductor integrated circuit to be designed Because
Initial placement means for performing the initial placement of the semiconductor integrated circuit based on the chip information;
Chip area dividing means for dividing the semiconductor chip into a plurality of areas;
Timing critical degree calculating means for calculating a timing critical degree based on the chip information for each of the areas divided by the chip area dividing means,
Yield improvement processing accuracy level setting means for setting the accuracy level of the yield improvement processing based on the timing criticality calculated by the timing criticality calculation means for each of the divided areas;
A semiconductor integrated circuit design apparatus. The apparatus for designing a semiconductor integrated circuit according to claim 6, wherein
A target timing criticality allocating unit that sets a target timing criticality index for each region based on the timing criticality of each region calculated by the timing criticality calculating unit;
Destination area setting means for generating destination area information for each gate so that the timing critical degree of the gate arranged in each area and the target timing critical degree are close to each other,
Gate relocation in consideration of the destination area information of each gate, and gate relocation means for reflecting the input to the timing criticality calculation means,
For each of the regions, it is determined whether an error between the timing critical degree and the target timing critical degree index is larger than a predetermined threshold, and an error between the timing critical degree and the target timing critical degree index is determined in advance. When it is larger than a predetermined threshold, the timing critical degree and the target timing critical degree index are transferred to the movement destination area setting means, and an error between the timing critical degree and the target timing critical degree index is predetermined. A timing error determination means for transferring the timing criticality to the yield improvement processing accuracy level setting means when the threshold is smaller than a threshold;
A device for designing a semiconductor integrated circuit. The apparatus for designing a semiconductor integrated circuit according to claim 6, wherein
A target timing criticality allocating unit that sets a target timing criticality index for each region based on the timing criticality of each region calculated by the timing criticality calculating unit;
Re-physical synthesis for each region with the target timing criticality index of each region as a timing constraint, and re-physical synthesis means for reflecting the input to the timing critical degree calculation means;
For each of the regions, it is determined whether an error between the timing critical degree and the target timing critical degree index is larger than a predetermined threshold, and an error between the timing critical degree and the target timing critical degree index is determined in advance. When it is larger than a predetermined threshold, the timing critical degree and the target timing critical degree index are transferred to the re-physical synthesis unit, and an error between the timing critical degree and the target timing critical degree index is a predetermined threshold. Timing error determination means for transferring the timing criticality to the yield improvement processing accuracy level setting means if
A device for designing a semiconductor integrated circuit. The apparatus for designing a semiconductor integrated circuit according to claim 6, wherein
A target timing criticality allocating unit that sets a target timing criticality index for each region based on the timing criticality of each region calculated by the timing criticality calculating unit;
Destination area setting means for generating destination area information for each gate so that the timing critical degree of the gate arranged in each area and the target timing critical degree are close to each other,
Gate relocation in consideration of the destination area information of each gate, and gate relocation means for reflecting the input to the timing criticality calculation means,
Re-physical synthesis for each region with the target timing criticality index of each region as a timing constraint, and re-physical synthesis means for reflecting the input to the timing critical degree calculation means;
For each of the regions, it is determined whether an error between the timing critical degree and the target timing critical degree index is larger than a predetermined threshold, and an error between the timing critical degree and the target timing critical degree index is determined in advance. When the timing criticality and the target timing criticality index are larger than a predetermined threshold, the timing criticality index and the target timing criticality index are alternately transferred to the movement destination area setting means, the gate rearrangement means, and the rephysical synthesis means, and the timing A timing error determination means for transferring the timing criticality to the yield improvement processing accuracy level setting means when an error between the criticality degree and the target timing criticality index is smaller than a predetermined threshold;
A device for designing a semiconductor integrated circuit. The apparatus for designing a semiconductor integrated circuit according to claim 6, wherein
A target timing criticality allocating unit that sets a target timing criticality index for each region based on the timing criticality of each region calculated by the timing criticality calculating unit;
Destination area setting means for generating destination area information for each gate so that the timing critical degree of the gate arranged in each area and the target timing critical degree are close to each other,
Gate relocation in consideration of the destination area information of each gate, and gate relocation means for reflecting the input to the timing criticality calculation means,
Re-physical synthesis for each region with the target timing criticality index of each region as a timing constraint, and re-physical synthesis means for reflecting the input to the timing critical degree calculation means;
For each of the regions, it is determined whether an error between the timing critical degree and the target timing critical degree index is larger than a predetermined threshold, and an error between the timing critical degree and the target timing critical degree index is determined in advance. If it is larger than the predetermined first threshold value, the timing critical degree and the target timing critical degree index are transferred to the movement destination area setting means, and the error between the timing critical degree and the target timing critical degree index is previously determined. If it is larger than the predetermined second threshold value, the timing critical degree and the target timing critical degree index are transferred to the re-physical synthesis means, and an error between the timing critical degree and the target timing critical degree index is determined in advance. A timing error determining means to pass the timing criticality in the yield enhancement processing accuracy level setting means when it is smaller than the first threshold value is because,
A device for designing a semiconductor integrated circuit.

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