JP2012227256A - Layout device and layout method of semiconductor integrated circuit, and cell data used for them - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a layout device of a semiconductor integrated circuit which easily eliminates timing violations and can suppress an increase in the number of man-hours, and the like.SOLUTION: In the layout device of the semiconductor integrated circuit which includes a storage device 13 for storing cell data and a layout section 242 for reading out the cell data from the storage device 13 and automatically arranging and wiring the read out cell data, the cell data has information on a filler cell considering a delay which adds a delay according to the situation of the arrangement with respect to a target cell, to the target cell.

Description

  The present invention relates to a semiconductor integrated circuit layout device, a layout method, and cell data used in the layout method.

  Cell-based ICs (Integrated Circuits) are suitable for application-specific semiconductor integrated circuits (ASIC: Application Specific Integrated Circuits), microprocessors that require high integration and high performance, and ASSPs (Application Specific Standards). It's being used. The cell-based IC is designed by combining a unique circuit designed by a user using a cell library provided by a semiconductor manufacturer. In the cell library, cells of various types and sizes are prepared, ranging from primitive cells equipped with basic circuits to macro cells equipped with macros such as CPU and memory. Since such a cell is arranged and wired on a chip by a placement and routing tool to design a circuit, design time and design cost can be reduced. Further, since the layout of the CPU or the like can be incorporated as a macro cell as it is, it is easy to create a system LSI.

  In LSI design, in principle, all timing paths (paths between sequential cells) are operating normally without causing timing violations such as setup violations and hold violations in timing verification at sign-off. Required.

  As one of the causes of timing violations, with the miniaturization of the wiring width in the LSI, there is a problem of variation in gate size (litho variation) due to variation in optical proximity effect and etching amount. When the proportion of the gate in a certain region (gate density) varies depending on the location, the gate pattern for each location has a different shape due to the optical proximity effect. Further, since the permeation degree of the etching solution varies depending on the gate density, the gate size and the gate shape after etching vary in a place where the gate density is different. Variations in transistor characteristics due to variations in gate size degrade product performance, resulting in timing violations in the critical path.

  A solution to such a problem is disclosed in Patent Document 1. An automatic layout device disclosed in Patent Document 1 includes a storage device that stores cell library data (cell data), and a placement and wiring that uses a cell library data to arrange a plurality of cells in a first direction perpendicular to a gate. Tools. The placement and routing tool sets in advance a reference gate designating unit that designates a gate in a predetermined cell as a reference gate among a plurality of arranged cells, and the number of gates existing in an area at a predetermined distance from the reference gate. A layout unit that arranges adjacent cells in a second direction perpendicular to the first direction with respect to a plurality of cells that have already been arranged, so that the number meets the constraints.

  As a result, the gate density around the gate designated as the reference gate becomes a value defined in the constraint condition. In the region where the gate density is the value specified in the constraint conditions, the gate density is uniform, which reduces variations in patterns due to the optical proximity effect and variations in gate size (gate shape) after etching (litho variations). The

JP 2009-65056 A

  As described above, in the prior art, an increase in timing violation is suppressed by reducing litho variation. However, in the prior art, when a timing violation is detected in the timing verification at the time of sign-off, it is necessary to insert a delay cell, relocate and rewire each cell in the same way as before. Become. That is, a design reversion occurs. As a result, the conventional technique has a problem in that it is necessary to insert a delay cell for eliminating the timing violation, resulting in an increase in power consumption. Further, there is a problem that the number of steps increases due to the rearrangement and rewiring of each cell.

  As described above, in the related art, when a timing violation is detected in the timing verification, there is a problem that it is not easy to eliminate the timing violation and the number of man-hours increases.

  A layout apparatus for a semiconductor integrated circuit according to an aspect of the present invention includes a cell data storage unit that stores cell data, and a layout unit that reads cell data from the cell data storage unit and performs automatic placement and routing, The cell data includes information on a delay-considering filler cell that adds a delay corresponding to the arrangement state of the target cell to the target cell.

  According to another aspect of the semiconductor integrated circuit layout device of one aspect of the present invention, a cell data storage unit that stores cell data, and a layout unit that performs automatic placement and routing by reading the cell data from the cell data storage unit The layout unit can further arrange a polysilicon layer shape in an empty area of the layout space, and adds a delay to the target cell in accordance with the arrangement state with respect to the target cell. The polysilicon layer shape is disposed.

  A semiconductor integrated circuit layout method according to one embodiment of the present invention is a semiconductor integrated circuit layout method using cell data, in which cell data is read and automatically placed and routed in accordance with a placement situation with respect to a target cell. A delay-considering filler cell for adding the delay to the target cell is arranged.

  Another aspect of the semiconductor integrated circuit layout method according to one embodiment of the present invention is a semiconductor integrated circuit layout method using cell data, in which cell data is read out, automatically placed and routed, and placed on a target cell. A polysilicon layer shape for adding a delay according to the situation to the target cell is arranged.

  The cell data according to one aspect of the present invention is cell data used for a layout of a semiconductor integrated circuit, and a delay-considering filler cell that adds a delay corresponding to the arrangement state of the target cell to the target cell. Information.

  Another aspect of the cell data according to one aspect of the present invention is cell data used for a layout of a semiconductor integrated circuit, and a different delay is added to the target cell according to the arrangement state with respect to the target cell. Information on a plurality of delay-considering filler cells.

  With the circuit configuration as described above, even when a timing violation is detected in the timing verification, the timing violation can be easily eliminated, so that an increase in man-hours can be suppressed.

  According to the present invention, even when a timing violation is detected in timing verification, a semiconductor integrated circuit layout device, a layout method, and a cell used in the semiconductor integrated circuit capable of easily eliminating the timing violation and suppressing an increase in man-hours Data can be provided.

1 is a block diagram showing an automatic layout apparatus for a semiconductor integrated circuit according to a first embodiment of the present invention; 1 is a diagram lock diagram showing an automatic layout device for a semiconductor integrated circuit according to a first exemplary embodiment of the present invention; 1 is a diagram lock diagram showing an automatic layout device for a semiconductor integrated circuit according to a first exemplary embodiment of the present invention; 1 is a diagram lock diagram showing an automatic layout device for a semiconductor integrated circuit according to a first exemplary embodiment of the present invention; It is a flowchart which shows the production | generation procedure of the delay consideration cell data concerning Embodiment 1 of this invention. It is a figure which shows an example of the delay consideration filler cell concerning Embodiment 1 of this invention. It is a figure which shows an example of the delay consideration filler cell concerning Embodiment 1 of this invention. It is a figure which shows an example of the delay consideration filler cell concerning Embodiment 1 of this invention. It is a figure which shows an example of the delay consideration filler cell concerning Embodiment 1 of this invention. It is a figure which shows an example of the delay consideration filler cell concerning Embodiment 1 of this invention. It is a figure which shows an example of the delay consideration filler cell concerning Embodiment 1 of this invention. It is a figure for demonstrating the production | generation procedure of the delay consideration cell data concerning Embodiment 1 of this invention. It is a figure for demonstrating the production | generation procedure of the delay consideration cell data concerning Embodiment 1 of this invention. It is a figure for demonstrating the production | generation procedure of the delay consideration cell data concerning Embodiment 1 of this invention. It is a figure which shows an example of the delay consideration cell data concerning Embodiment 1 of this invention. It is a flowchart which shows operation | movement of the automatic layout apparatus concerning Embodiment 1 of this invention. It is a flowchart which shows operation | movement of the automatic layout apparatus concerning Embodiment 2 of this invention.

  Hereinafter, an automatic layout apparatus, a layout method, and cell data used in the semiconductor integrated circuit according to the present embodiment will be described with reference to the accompanying drawings. In the present embodiment, a semiconductor circuit design support apparatus that designs a cell-based IC will be described as an example. Since the drawings are simplified, the technical scope of the present invention should not be interpreted narrowly based on the description of the drawings. Moreover, the same code | symbol is attached | subjected to the same element and the overlapping description is abbreviate | omitted.

Embodiment 1
A configuration of an automatic layout apparatus (layout apparatus) 10 according to the first exemplary embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a configuration diagram of an automatic layout apparatus 10 according to the present embodiment. 2 and 3 are configuration diagrams showing a part of the automatic layout apparatus 10 in the delay-considering cell data generation phase. FIG. 4 is a configuration diagram showing a part of the automatic layout apparatus 10 in the chip layout phase.

  The inventor of the present application prepared a plurality of filler cells having different proportions of the polysilicon layer in the whole cell, that is, a proportion of the gate size in the whole cell (hereinafter simply referred to as gate density), and each filler cell Was placed in the vicinity of a certain cell (target cell), and it was found that a delay corresponding to the type and arrangement position of the filler cell was added to the target cell under the influence of lithography. The automatic layout apparatus 10 according to the present embodiment stores data relating to these filler cells (delay-considering filler cells), and an optimum delay-considering filler cell is located near the cell (target cell) on the path where the timing violation has occurred. By arranging, the delay of the target cell is adjusted, and the timing violation is easily eliminated.

  As shown in FIG. 1, the automatic layout device 10 includes a CPU 11, a RAM 12, a storage device 13, an input device 14, and an output device 15 that are connected to each other via a bus 16. The storage device 13 is an external storage device exemplified by a hard disk and a memory. The input device 14 outputs various data to the CPU 11 and the storage device 13 by being operated by a user such as a keyboard and a mouse. The output device 15 is exemplified by a monitor and a printer, and outputs the layout result of the semiconductor device output from the CPU 11 so as to be visible to the user.

  The storage device 13 stores a cell library 21 for automatic layout, constraint information 22, a netlist 23, and an automatic layout program 24. In response to the input from the input device 14, the CPU 11 executes the automatic layout program 24 in the storage device 13 to perform generation or conversion processing of the cell library 21, cell placement and wiring processing. At this time, various data and programs from the storage device 13 are temporarily stored in the RAM 12, and the CPU 11 executes various processes using the data in the RAM 12.

  The cell library 21 is a set of data (hereinafter simply referred to as cell data) related to macro cells whose layout has already been designed. In the cell library 21, macro cells including large-scale circuits such as RAM, ROM, and CPU core are registered from macro cells including basic circuits such as NAND and flip-flop.

  As shown in FIGS. 2 to 4, the cell library 21 stores general cell data 211 that is data related to each cell. The cell library 21 is further added with delay consideration filler cell data 212, which is data related to the delay consideration filler cell, and delay information based on each delay consideration filler cell to each cell through a delay consideration cell data generation phase described later. The delay consideration cell data 213 is stored. In the present embodiment, the cell data includes information on the pin arrangement in the cell and cell frame (cell outline) data, as well as information on the diffusion layer and gate coordinates inside the cell. Explained. In addition, the structure regarding the information regarding the coordinate of the diffusion layer inside a cell and the gate may be provided separately as layout data.

  The constraint information 22 defines design rules such as wiring width and cell interval, timing constraints, and the like used when the layout unit (placement and wiring tool) 242 places and routes cells on the chip. The net list 23 is a logic circuit design result indicating connection information of each cell.

  The automatic layout program 24 of the semiconductor integrated circuit is executed by the CPU 11 to realize the functions of the cell data generation unit 241 and the layout unit 242 in the computer. The cell data generation unit 241 is a unit that generates data of each cell. The layout unit 242 is a unit that outputs layout data after arranging and wiring necessary cells on a chip.

  As shown in FIG. 2, the cell data generation unit 241 generates data regarding a plurality of delay-considering filler cells having different gate densities as delay-considering filler cell data 212 in the delay-considering cell data generation phase. Remember. Based on the general cell data 211, the delay-considering filler cell data 212, and the constraint information 22, the layout unit 242 performs temporary arrangement of cells (target cell and its surrounding cells) and delay-considering filler cells, and delay-considering cell data 213. Outputs layout data for measurement used for generation.

  Thereafter, as shown in FIG. 3, the cell data generation unit 241 performs a plurality of measurements for different types of general cell data 211, the target cell type, the delay consideration filler cell type, and the arrangement conditions in the delay consideration cell data generation phase. Based on a plurality of delay information obtained from the layout data, delay-considering cell data 213 is generated. More specifically, the cell data generation unit 241 adds corresponding delay information to each cell included in the general cell data 211 to generate the delay-considered cell data 213.

  Then, the layout unit 242 is necessary based on the general cell data 211, the delay consideration filler cell data 212, the delay consideration cell data 213, the net list 23, and the constraint information 22 in the chip layout phase as shown in FIG. After placing and wiring a correct cell on the chip, chip layout data is output. At this time, the layout unit 242 refers to the pin arrangement of each cell and the size of each cell included in the general cell data 211, and determines the design rule such as the wiring width and the cell interval included in the constraint information 22 and the wiring delay. In consideration of the arrangement and wiring of each cell. The layout unit 242 may be configured to output chip layout data based on the delay-considering filler cell data 212, the delay-considering cell data 213, the netlist 23, and the constraint information 22 other than the general cell data 211. Good. In this case, the layout unit 242 refers to the pin arrangement of each cell and the size of each cell included in the delay-considering cell data 213 instead of the general cell data 211, and performs the arrangement and wiring of each cell.

  Next, automatic layout processing by the automatic layout apparatus 10 according to the present embodiment will be described in detail. The automatic layout apparatus 10 according to the present embodiment performs automatic layout processing mainly in two phases: a delay-considering cell data generation phase and a chip layout phase. Further, in the chip layout phase, the automatic layout apparatus 10 mainly performs cell arrangement and wiring processing and timing adjustment by arrangement of delay-considering filler cells. The delay-considering cell data generation phase may be executed in advance separately from the chip layout phase. In this case, the automatic layout device 10 functions as a delay-considering cell data generation device.

(Delayed cell data generation phase)
The delay consideration cell data generation phase is that the cell data generation unit 241 adds delay information based on the delay consideration filler cell to each cell registered as the general cell data 211 and generates the delay consideration cell data 213. It is a phase to do. This will be specifically described below.

  FIG. 5 is a flowchart showing a procedure for generating the delay-considered cell data 213 according to the present embodiment. First, the cell data generation unit 241 generates a plurality of delay-considering filler cell data 212 having different gate densities (S100). 6A to 6F show an example of a delay-considering filler cell. In the example of FIGS. 6A to 6F, the polysilicon layers 101 that are gates are arranged in the vertical direction of the paper surface, and the diffusion layers 102 are arranged in two rows so as to sandwich the polysilicon layers from the horizontal direction of the paper surface. FIG. 6A shows a delay-considering filler cell 100A with a medium gate density. FIG. 6B shows a delay-considering filler cell 100B having a high gate density on the right side of the paper inside the cell. FIG. 6C shows a delay-considering filler cell 100C having a low gate density on the right side of the paper inside the cell. FIG. 6D shows a delay-considering filler cell 100D having a medium gate density, similar to FIG. 6A. FIG. 6E shows a delay-considering filler cell 100E having a high gate density on the left side of the paper inside the cell. FIG. 6F shows a delay-considering filler cell 100F having a low gate density on the left side of the paper inside the cell.

  In the present embodiment, a case is described in which a plurality of delay-considering filler cells having different gate densities are used, but the present invention is not limited to this. A plurality of delay-considering filler cells having different gate shapes (polysilicon layer shapes) may be used as long as the influence of the delay on the target cell can be adjusted.

  Next, the layout unit 242 temporarily arranges the target cell and the peripheral cells for generating the delay-considering cell data 213 (S101). In the following description, for convenience, layout data in a state where target cells and peripheral cells are temporarily arranged is referred to as intermediate layout data.

  7 to 9 show an example of the intermediate layout data. In the example of FIG. 7, any cell selected from among a plurality of cells included in the general cell data 211 is arranged as the target cell 103 in the center of the drawing. A plurality of cells (for example, cells with the highest usage rate) are arranged as the peripheral cells 104 so as to surround the target cell 103. In the example of FIG. 7, the area adjacent to the left side surface of the target cell 103 is an empty area. In the example of FIG. 8, the target cell 103 is arranged at the center of the paper surface, and a plurality of peripheral cells 104 are arranged so as to surround the target cell 103. In the example of FIG. 8, the area adjacent to the right side surface of the target cell 103 is an empty area. In the example of FIG. 9, the target cell 103 is arranged at the center of the paper surface, and a plurality of peripheral cells 104 are arranged so as to surround the target cell 103. In the example of FIG. 7, the areas adjacent to the right side surface and the left side surface of the target cell 103 are vacant areas. In the present embodiment, the layout unit 242 first performs temporary arrangement of target cells and peripheral cells as shown in FIG.

  Next, the layout unit 242 arranges any delay-considering filler cell in an empty area of the intermediate layout data (S102), and outputs measurement layout data (S103). For example, the layout unit 242 arranges the delay-considering filler cell 100A shown in FIG. 6A in the empty area of the intermediate layout data shown in FIG. 7, and outputs measurement layout data.

  Thereafter, a lithography simulator (not shown), which is another tool, performs lithography simulation on the measurement layout data to generate a virtual wafer shape (S104). Based on this virtual wafer shape, an effective transistor channel length (L) and channel width (W) are calculated. Thereafter, an analog simulator (not shown), which is another tool, performs simulation based on L / W calculated from the virtual wafer shape, and measures the influence of delay on the target cell 103 by the delay-considering filler cell 100A. (S105). For example, a SPICE simulator is used as the analog simulator. These simulators may be provided as a part of the function of the automatic layout apparatus 10.

  Thereafter, when there is a delay-considering filler cell that has not yet been selected (NO in S106), the layout unit 242 replaces the delay-considering filler cell with the delay-considering filler cell (S107), and outputs new measurement layout data (S103). For example, the layout unit 242 arranges the delay-considering filler cell 100B shown in FIG. 6B in the empty area of the intermediate layout data shown in FIG. 7, and outputs new measurement layout data. Thereafter, the same processing as described above is repeated (S103 to S107). In the present embodiment, the layout unit 242 sequentially arranges the delay-considering filler cells 100A, 100B, and 100C shown in FIGS. 6A to 6C in the empty area of the intermediate layout data shown in FIG. Is output. In these measurement layout data, the influence of the delay that the target cell 103 receives by the delay-considering filler cells having different gate densities is measured.

  The layout unit 242 changes the arrangement positions of the peripheral cells 104 when all the delay-considering filler cells to be targeted are selected and the influence of the delay on the target cell 103 is measured (YES in S106). An empty area is created at the position (NO in S108, S109). For example, the layout unit 242 changes the intermediate layout data shown in FIG. 7 to the intermediate layout data shown in FIG. 8 by changing the arrangement position of the peripheral cell 104. Thereafter, the same processing as described above is repeated (S102 to S109). In the present embodiment, the layout unit 242 sequentially performs temporary arrangements as shown in FIGS. 7 to 9, sequentially arranges each delay-considering filler cell for each, and outputs measurement layout data. In these measurement layout data, the influence of the delay that the target cell 103 receives by each delay-considering filler cell having a different arrangement position is measured.

  As shown in FIGS. 7 and 9, delay consideration filler cells 100 </ b> A, 100 </ b> B, and 100 </ b> C shown in FIGS. 6A to 6C are arranged in an empty area adjacent to the left side surface of the target cell 103. On the other hand, as shown in FIGS. 8 and 9, the delay-considering filler cells 100 </ b> D, 100 </ b> E, and 100 </ b> F shown in FIGS. 6D to 6F are arranged in the empty area adjacent to the right side surface of the target cell 103. This is because the influence of the gate density of each delay-considering filler cell is given only to the target cell 103 and not to other peripheral cells.

  Thereafter, the cell data generation unit 241 adds the delay information obtained from each measurement layout data to the corresponding cell and generates the delay information as a part of the delay-considered cell data 213. The delay-considered cell data 213 is stored in the cell library 21 (S110).

  Such processing is repeated in the same manner by changing the target cell to another cell (S101 to S111). Thus, the layout unit 242 outputs a plurality of measurement layout data having different types of target cells, types of delay-considering filler cells, and arrangement conditions. Then, the cell data generation unit 241 generates delay-considered cell data 213 based on the general cell data 211 and the delay information obtained from these measurement layout data. More specifically, the cell data generation unit 241 adds corresponding delay information to each cell included in the general cell data 211 to generate the delay-considered cell data 213.

  FIG. 10 shows a description example of the delay considering cell data 213. As shown in FIG. 10, for example, for cell A, the delay when the delay consideration filler cell 100A is placed adjacent to the left side surface is 0.0 ps, and the delay when the delay consideration filler cell 100B is placed is 1.0 ps. When the delay-considering filler cell 100C is placed, the delay is -0.5 ps. Further, in the cell A, the delay when the delay consideration filler cell 100D is placed adjacent to the right side is 0.0 ps, the delay when the delay consideration filler cell 100E is placed is 0.3 ps, and the delay consideration filler cell 100F is When placed, the delay is -1.0 ps. In the cell A, the delay when the delay consideration filler cells 100A and 100D are placed adjacent to the right side surface and the left side surface is 0.0 ps, and the delay when the delay consideration filler cells 100B and 100E are placed is 1.5 ps. The delay when the delay consideration filler cells 100B and 100F are placed is 0.1 s, the delay when the delay consideration filler cells 100C and 100E are placed is 1.2 ps, and the delay when the delay consideration filler cells 100C and 100F are placed Is −1.8 ps. Thus, delay information is added to each cell in the delay considering cell data 213.

(Chip layout phase)
FIG. 11 is a flowchart showing the operation of the automatic layout apparatus 10 according to the present embodiment. First, the layout unit 242 arranges necessary cells on the chip based on the general cell data 211, the net list 23, and the constraint information 22, and after wiring, outputs the chip layout data (S200).

  Next, timing adjustment is performed (S201). In this process, first, a sign-off check is performed on the chip layout data (S2011). In other words, timing verification is performed on the chip layout data. This timing verification may be performed by another timing verification tool, or may be performed by a timing verification function provided in the automatic layout apparatus 10.

  When a timing violation is detected, the layout unit 242 detects an empty area near a cell (target cell) on the path where the timing violation has occurred (S2012), and virtually arranges each delay-considering filler cell in the empty area. Each of the timing violations is simulated (S2013, S2014). There may be a plurality of cells on the path where the timing violation has occurred. In addition, a plurality of delay-considering filler cells may be arranged in an empty area near the cell on the path where the timing violation has occurred. Therefore, first, the layout unit 242 virtually arranges and simulates a plurality of appropriate delay-considering filler cells, refers to the result, and replaces the timing violation with the optimal delay-considering filler cell so as to converge again. It is also possible to simulate.

  When the type and arrangement position of the delay-considering filler cell from which the timing violation is eliminated are determined, the layout unit 242 arranges these delay-considering filler cells at the determined position (S2015). Next, the layout unit 242 arranges normal filler cells that do not affect the delay of each already arranged cell in the remaining free space of the layout space (S2016). Thereafter, the layout unit 242 outputs the completed chip layout data (S202). Next, a sign-off check is performed on the chip layout data for confirmation (S203). As described above, the automatic layout apparatus 10 can easily eliminate the timing violation without changing the arrangement and wiring of other cells by arranging the delay-considering filler cells in the empty area of the layout space. As a result, an increase in the number of man-hours for designing is suppressed.

  If the timing violation is not resolved, a correction for the timing violation (S204) and a sign-off check for the corrected chip layout data (S205) are performed. Even in this case, the automatic layout apparatus 10 can easily eliminate the timing violation without changing the arrangement and wiring of other cells by changing the type and arrangement position of the delay-considering filler cells. As a result, an increase in the number of man-hours for designing is suppressed.

  As described above, the automatic layout apparatus 10 according to the present embodiment can easily violate the timing without changing the arrangement or wiring of other cells by arranging the delay-considering filler cells in the empty area of the layout space. Can be resolved. As a result, an increase in the number of man-hours for designing is suppressed. Furthermore, in this embodiment, since the timing violation can be solved by using the delay-considering filler cell, unlike the conventional technique, it is not necessary to insert a delay cell for eliminating the timing violation, and the increase in power consumption is suppressed. .

  In the prior art, dummy cells are inserted in advance in order to reduce litho variation. Therefore, the conventional technique has a problem that the circuit scale and the chip area increase. However, in this embodiment, the timing violation can be solved by using the delay-considering filler cell, so that unlike the conventional technique, it is not necessary to insert a dummy cell to reduce litho variation, and the increase in circuit scale and chip area is suppressed. Is done.

Embodiment 2
In the first embodiment, a case where a plurality of delay-considering filler cells having different gate densities is used has been described as an example. The automatic layout apparatus 10b according to the present embodiment has a function of adding a desired delay to the target cell without using such a delay-considering filler cell. Note that the automatic layout device 10b according to the present embodiment does not use delay-considering filler cells, and therefore, unlike the first embodiment, does not generate delay-considering filler cell data and delay-considering cell data.

  FIG. 12 is a flowchart showing the operation of the automatic layout apparatus 10b according to the present embodiment. Here, only the timing adjustment (S201b) that is different from the operation of the automatic layout apparatus 10 according to the first embodiment will be described.

  In the process of timing adjustment (S201b), first, a sign-off check is performed on the chip layout data (S2011). In other words, timing verification is performed on the chip layout data. This timing verification may be performed by another timing verification tool, or may be performed by a timing verification function provided in the automatic layout apparatus 10.

  When a timing violation is detected, the layout unit 242b detects an empty area near the cell on the path where the timing violation has occurred (S2012), and calculates a delay amount necessary to eliminate the timing violation (S2013b). ). Based on the calculation result, the layout unit 242b virtually arranges an appropriate polysilicon layer shape in an empty area near the cell (target cell) on the path where the timing violation has occurred, and the timing violation is resolved. This is simulated (S2014b). The cell library 21 does not store delay-considering filler cell data and delay-considering cell data. Therefore, the automatic layout apparatus 10b needs to measure the influence of the delay that the target cell receives due to the virtually arranged polysilicon layer shape using the lithography simulation function and the analog simulation function. The layout unit 242b refers to the measurement result and corrects the arrangement of the polysilicon layer shape so as to converge the timing violation as necessary. When the polysilicon layer shape is corrected, it is necessary to consider the Design Rule, so that the Design Rule violation between the inside of the cell and the adjacent cell does not occur when the cell is arranged.

  When the arrangement position of the polysilicon layer shape that eliminates the timing violation is determined, the layout unit 242b arranges the polysilicon layer shape at the determined position (S2015b). Next, the layout unit 242b arranges normal filler cells that do not affect the delay of each already arranged cell in the remaining free space of the layout space (S2016). Thereafter, the layout unit 242b outputs the completed chip layout data (S202).

  As described above, the automatic layout apparatus 10b according to the present embodiment performs more accurate timing adjustment by arranging the polysilicon layer shape directly in the empty area of the layout space instead of the delay-considering filler cell. Is possible. However, a predetermined processing time is required to measure the influence of delay on the target cell due to the virtually arranged polysilicon layer shape.

  As described above, the automatic layout apparatus according to the above-described first and second embodiments arranges one of the delay-considering filler cell and the polysilicon layer shape in the vacant area of the layout space, thereby arranging other cells. The timing violation can be easily resolved without changing the wiring. As a result, an increase in the number of man-hours for designing is suppressed. Further, in the first and second embodiments, since the timing violation can be solved by using either the delay-considering filler cell or the polysilicon layer shape, the delay cell is inserted to eliminate the timing violation unlike the conventional technique. It becomes unnecessary and the increase in power consumption is suppressed.

  In the prior art, dummy cells are inserted in advance in order to reduce litho variation. Therefore, the conventional technique has a problem that the circuit scale and the chip area increase. However, in this embodiment, the timing violation can be solved by using the delay-considering filler cell, so that unlike the conventional technique, it is not necessary to insert a dummy cell to reduce litho variation, and the increase in circuit scale and chip area is suppressed. Is done.

  The present invention is not limited to Embodiments 1 and 2 described above, and can be changed as appropriate without departing from the spirit of the present invention. For example, in the first embodiment, in the intermediate layout data, each delay-considering filler cell is arranged adjacent to the direction perpendicular to the gate of the target cell 103 (the left-right direction of the target cell 103 in the drawing) as an example. Although explained, it is not limited to this. In the intermediate layout data, each delay consideration filler cell is arranged adjacent to the direction parallel to the gate of the target cell 103 (up and down direction of the target cell 103 on the paper surface), or other adjacent arrangement. Also good. However, the channel length of the target cell 103 is likely to change due to the influence of a delay-considering filler cell arranged adjacent to the direction perpendicular to the gate of the target cell 103 (left-right direction) during lithography. Therefore, this embodiment is limited to the case where each delay-considering filler cell is arranged adjacent to the direction (left-right direction) perpendicular to the gate of the target cell 103.

  In the first embodiment, the delay information based on the delay-considering filler cell does not consider conditions such as the input terminal of the cell and the load capacity, but these conditions may be considered. In this case, the delay-considering cell data 213 stores delay information based on differences in cell input terminals, load capacities, etc. in a table.

  In the first embodiment, the case where a delay-considering filler cell that adds a delay only to a target cell adjacent to one side surface is used as an example. However, the present invention is not limited to this. In addition to such delay-considering filler cells, delay-considering filler cells that add delays to target cells adjacent to a plurality of side surfaces may be used.

10, 10b Automatic layout device 11 CPU
12 RAM
DESCRIPTION OF SYMBOLS 13 Memory | storage device 14 Input device 15 Output device 21 Cell library 22 Restriction information 23 Net list 24 Automatic layout program 100A Filler cell 100B Filler cell 100C Filler cell 100D Filler cell 100E Filler cell 100F Filler cell 101 Polysilicon layer 102 Diffusion layer 103 Target cell 104 Peripheral cells 211 General cell data 212 Delay-considering filler cell data 213 Delay-considering cell data 241 Cell data generation unit 242, 242b Layout unit

Claims (13)

A cell data storage unit for storing cell data;
A layout unit that reads cell data from the cell data storage unit and performs automatic placement and routing, and
The cell data is
A layout device for a semiconductor integrated circuit, which has information on a delay-considering filler cell that adds a delay in accordance with an arrangement state with respect to a target cell to the target cell. The layout part is
2. The layout apparatus for a semiconductor integrated circuit according to claim 1, wherein the delay-considering filler cell is arranged adjacent to the target cell in a direction perpendicular to the gate of the target cell. The layout part is
3. The layout apparatus for a semiconductor integrated circuit according to claim 1, wherein the delay-considering filler cell is arranged in an empty area of the layout space. The cell data is
4. The layout of a semiconductor integrated circuit according to claim 1, comprising information on a plurality of delay-considering filler cells that respectively add different delays to the target cell in accordance with the arrangement status with respect to the target cell. 5. apparatus. A cell data storage unit for storing cell data;
A layout unit that reads cell data from the cell data storage unit and performs automatic placement and routing, and
The layout part is
Furthermore, the polysilicon layer shape can be arranged in an empty area of the layout space,
A layout apparatus for a semiconductor integrated circuit, in which the polysilicon layer shape is arranged so as to add a delay corresponding to a situation of arrangement with respect to a target cell to the target cell. A layout method of a semiconductor integrated circuit using cell data,
Read cell data, automatically place and route,
A layout method of a semiconductor integrated circuit, in which a delay-considering filler cell for adding a delay corresponding to a state of arrangement with respect to a target cell to the target cell is arranged.   7. The semiconductor integrated circuit layout method according to claim 6, wherein the delay-considering filler cell is arranged adjacent to the target cell in a direction perpendicular to the gate of the target cell.   8. The method of laying out a semiconductor integrated circuit according to claim 6, wherein the delay-considering filler cells are arranged in an empty area of the layout space.   The delay-considering filler cell is selected and arranged from among a plurality of delay-considering filler cells that respectively add different delays depending on the arrangement state of the target cell to the target cell. Item 9. A layout method for a semiconductor integrated circuit according to any one of Items 6 to 8. A layout method of a semiconductor integrated circuit using cell data,
Read cell data, automatically place and route,
A layout method of a semiconductor integrated circuit, in which a polysilicon layer shape for adding a delay corresponding to a situation of arrangement with respect to a target cell is arranged with respect to the target cell. Cell data used for the layout of a semiconductor integrated circuit,
Cell data having information of a delay-considering filler cell that adds a delay corresponding to the arrangement state of the target cell to the target cell. Cell data used for the layout of a semiconductor integrated circuit,
Cell data having information on a plurality of delay-considering filler cells that add different delays to the target cell according to the arrangement status of the target cell.   A cell data generation device for generating the cell data according to claim 11.

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