JPH04155522A - First-in-random-out circuit - Google Patents

Abstract

PURPOSE:To attain easy and high speed digital signal processing by providing a signal selecting circuit for both writing-in and reading out which can be controlled from the outside, and taking out a sequentially inputted and written signal as a random output signal. CONSTITUTION:A writing controlling signal S7 and an address signal S5 are inputted to a memory 3 in the same timing, and the writing of data S6 is operated. At such a time, a load signal S1 indicating an initial load is inputted to a counter circuit 1, counted-up from an initial value by a clock S2, and outputted as a count signal S3. A signal selecting circuit 2 inputs the count signal S3, and outputs the address signal S5 being an indication signal obtained after operating the clock synchronization of a select signal S9 inputted from the outside. Therefore, the address signal S5 can be prepared by that above mentioned processing. Thus, the address signal S5 is selected by a reading address signal S4 and the select signal S9 arbitrarily set from the outside, and the random output signal can be taken out.

Description

[Detailed description of the invention] [Industrial application field] The present invention is based on first-in random-out (hereinafter referred to as F
The present invention relates to FIR circuits (referred to as IRO circuits) used in digital signal processing such as random number generators, reinterleave generators, and simple encoders/decoders that randomly output sequentially input parallel signals.

[Conventional technology]

Conventionally, this type of FIRO circuit for digital signal processing does not exist due to its circuit configuration that outputs parallel output signals in the same sequence as the input signal from input parallel signals.
Therefore, some of the aforementioned random number generators, simple encryption/decoders, etc. are controlled by a special algorithm circuit configuration provided separately. Furthermore, for the reinterleave generator, a method was used in which data is rearranged in memory using software and then outputted.

[Problem to be solved by the invention]

As mentioned above, since FIRO circuits have not conventionally existed, random number generators and simple encrypters/decryptors have the disadvantage of having complicated circuit configurations in order to generate circuits for special algorithms. Also, the reinterleave generator is
Since memory operations are performed using software, there are drawbacks such as the time required for signal processing.

[Means to solve the problem]

The first-in random-out circuit of the present invention includes:
A memory that temporarily stores a plurality of parallel input signals, a counter circuit that outputs a count signal at the timing of storage in the memory based on a predetermined clock signal and a load signal, and a readout that is input from the outside based on the counter signal. a signal selection circuit that outputs an address signal selected by an address signal and a selection signal, and inputs a read enable signal to the memory at the same timing as the selected read address signal output from the signal selection circuit. Then, an arbitrary output signal corresponding to the read address signal is output.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention. The embodiment shown in FIG. 1 is composed of a counter circuit 1, a signal selection circuit 2, and a memory 3. First, a write control signal S7, which is permitted while data S6, which is a continuous input signal, can be written, and an address signal S5, which will be described next, are input to the memory 3 at the same timing to write data S6. Here, the method for generating the address signal S5 is that a load signal S1 instructing the counter circuit 1 to perform an initial load is input. Next, the counter circuit 1 is counted up (or down) from the initial value by the clock S2, and outputted as a count signal s3. The signal selection circuit 2 inputs the count signal s3 and outputs an address signal S5 which is an instruction signal obtained by tarock synchronizing a select signal S9 inputted from the outside. Memory 3 receives this address signal S.
Enter 5 to complete the first-in procedure.

Next, a random out procedure for reading out this write signal will be explained. In the random out procedure, according to the address signal S5, the read signal s8 input to the memory 3 is output as the output data S6 only while it is permitted, but the address signal S5 is not counted sequentially. will be output randomly. Therefore, an output value different from the procedure of the input signal can be obtained. That is, the address signal s5 of the signal selection circuit 2 is selected by the read address signal S4 and the select signal s9, which are arbitrarily set from the outside.

Through these steps, the FIRO circuit operates,
Random output signals can be extracted.

〔Effect of the invention〕

As described above, the present invention provides an externally controllable writing/reading signal selection circuit, and can output sequentially input and written signals as random output signals.

Therefore, F
We can provide IR○ circuit. Since it is possible to provide a scattering generator, an interleave generator, and a simple encoder/decoder that integrate this FIRO circuit, it is extremely effective.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the present invention. 1...Counter circuit, 2...Signal selection circuit, 3...
・Memory, Sl...load signal, s2...clock, s3...count signal, S4...read address signal, S5...address signal, s6...data,
s7...Write signal, S8...Read signal, S
9...Select signal.

Claims (1)

[Scope of Claims] 1. A memory that temporarily stores a plurality of parallel input signals, and a counter circuit that outputs a count signal at the timing of storage in the memory based on a predetermined clock signal and a load signal;
a signal selection circuit that outputs an address signal selected by a read address signal input from the outside based on the counter signal and a selection signal, the selected read address signal output from the signal selection circuit; A first-in random-out circuit that inputs a read enable signal to the memory at the same timing as and outputs an arbitrary output signal corresponding to the read address signal. 2. When the memory receives a write enable signal and a data signal, it sequentially writes data, and after this write operation, the address signal and read enable signal selected from the signal selection circuit are input. 2. The first-in-random-out circuit according to claim 1, wherein the first-in random-out circuit outputs corresponding arbitrary read data in the case where the first-in random-out circuit outputs corresponding arbitrary read data.