KR100481828B1 - Control method of memory using a variable address control circuit - Google Patents

Abstract

The present invention relates to a memory control method using a variable address control device capable of preventing a collision of data during data writing and reading when data writing and reading timing is not 1: 1. In the memory control method of writing and reading data to and from the memory element of a system in which a memory element is used, data writing and reading of the memory element is controlled by a variable address control device, and the variable address control device is Means for receiving data divided into predetermined units from the outside, specifying an index for each divided unit, and inputting an index for each unit, and receiving an initial address for each unit of data divided into predetermined units. Means generated by designation, and an initial address for each unit, And means for generating a variable data write and read address for each unit in response to the clock signal. By such a memory control method using the variable address control device, it is possible to prevent collision of memory data while using one memory element and to minimize the number of memory elements.

Description

CONTROL METHOD OF MEMORY USING A VARIABLE ADDRESS CONTROL CIRCUIT}

The present invention relates to a method of efficiently using a memory, and more particularly, to a memory control method using a variable address control device that prevents data collision when data is written and read in a system to which a memory is applied.

In an image signal processing system, memory devices are mainly used to store field or frame images. A general field or frame image storage memory device reads data at a specific address, and then uses a method of 1: 1 reading and writing timing for writing image data currently input at the same address. Optimize the number of memory devices applied externally.

However, as shown in FIG. 1, read and write timings of the memory are often not matched 1: 1 in an application field in which the memory device is not used for simple storage.

For example, in the case of storing image data in a memory device and performing electric zoom using the data, field data is written in accordance with the timing output from the CCD, but reading of the image data is performed. It is made in accordance with the timing of the zoom magnification.

In other words, the writing of the data proceeds in accordance with the system clock timing, and the reading and writing of the memory is not 1: 1 because the reading of the data proceeds more slowly than the writing of the data.

Thus, as shown in Fig. 1, if the write address always starts at "1" and the read address is controlled through 2x zoom, the read data "6" and "7" cannot read the previous data. The currently written data will be read. As a result, a problem arises in which the data read out of the memory element collide with the data written in.

In order to prevent such a problem, the proposed method is to use two memory elements in a system requiring a memory for storing one field data.

In this case, when one memory device operates in the read mode, the other memory device operates in the write mode, and data collision is prevented by adjusting the read and write according to the field.

However, the above-described method has a problem in that it requires more memory, that is, twice as much memory as the basic specification of the system in which the memory element is used.

Disclosure of Invention The present invention proposed to solve the above-mentioned problem is an object of the present invention to provide a memory control method using a variable address control device capable of preventing data collisions during data writing and reading of a system to which a memory is applied.

Another object of the present invention is to provide a memory control method using a variable address control apparatus capable of minimizing the number of memory elements in a system in which a memory element is used.

(Configuration)

According to one aspect of the present invention for achieving the above object, in the memory control method for writing and reading data to and from the memory device of the system in which the memory device is used, the data writing and reading of the memory device is Controlled by a variable address control device; The apparatus for controlling a variable address includes: means for receiving data divided into predetermined units from the outside and specifying and generating an index for each divided unit; Means for receiving an index for each unit and generating an initial address for each unit of data divided into predetermined units; Means for receiving an initial address for each unit and generating a variable data write and read address for each unit in response to a clock signal input from the outside.

In a preferred embodiment of this method, the means for generating data write and read addresses for each unit is a programmable counter.

According to another aspect of the present invention, a memory control method using a variable address control apparatus includes: a system in which a memory element in which data writing and reading is performed is used; Write and read times of the data are not equal to each other; The system includes: means for receiving data divided into predetermined units from the outside and specifying the index for each divided unit and generating the index; Means for receiving an index for each unit and generating an initial address for each unit of data divided into predetermined units; Means for receiving an initial address for each unit and generating a variable data write and read address for each unit in response to a clock signal input from the outside.

In a preferred embodiment of this method, the means for generating data write and read addresses for each unit is a programmable counter.

(Action)

By such a memory control method using the variable address control device, it is possible to prevent collision of memory data while using one memory element and to minimize the number of memory elements.

(Example)

Best Mode for Carrying Out the Invention Preferred embodiments of the present invention will now be described in detail with reference to FIGS. 2 and 3.

2 illustrates a variable address control apparatus according to an exemplary embodiment of the present invention, and FIG. 3 is a timing diagram illustrating address control when data is written and read in a system to which a memory using the variable address control apparatus illustrated in FIG. 2 is applied. Is shown.

Referring to FIG. 2, an apparatus for controlling a variable address may include an index generator 10 generated by receiving image data divided into field or frame units, and specifying an index for each field or frame unit of the image data; In response to an input of an index of each field or frame, an initial address generator 20 generated by specifying an initial address for each field or frame, and an initial address of each field or frame, and in response to a clock signal input from outside It has a configuration that includes a programmable ring counter (30) for generating a data write address for each field or frame.

In this case, the index generator 10 creates an index on the basis of when the system is reset or when the power is "on", and the index size may vary depending on the system, but the fixed index size is usually fixed. Need.

An address control method of the memory device using the variable address control device as described above will be described in detail with reference to FIG. 3. Here, the size of the memory is 8x1bit, the field signal consists of 10 clocks, 8 clocks are main data processing intervals, the remaining two clocks are blank intervals, and the application system is 8 It is assumed that the electronic zoom is performed twice by using the clock image data.

Referring to FIG. 3, the memory address control method using the above-described variable address control apparatus according to the present invention may be represented by Equation 1 to Equation 6 below.

[Equation 1]

[Equation 2]

[Equation 3]

[Equation 4]

[Equation 5]

[Equation 6]

Here, "n" is the row size (row or column size), "m" is the memory read size (memory read size), "n" is greater than or equal to "m". In addition, "i" represents a field number, that is, a number of read / write cycle numbers, "α" represents an arbitrary address point, and "α" represents " relatively smaller than n ".

Equations 1 and 2 described above indicate that the write address and the read address are defined for each field (i) with an address point of writing and reading the memory element as the address "0". 4 shows when the address points to be written and read are arbitrary points. The final write address point is determined by Equation 5, and the read address point is also defined by Equation 6 according to the field. "Rem (Wa, n)" represents the remaining value obtained by dividing "Wa" by "n".

By the memory control method using the variable address control as described above, it is possible to prevent data collision of the system in which the memory element is used, and to minimize the number of memory elements.

1 is a timing diagram showing address control in writing and reading data of a system to which a conventional memory is applied;

2 is a block diagram showing a variable address control apparatus according to an embodiment of the present invention;

FIG. 3 is a timing diagram showing address control during data writing and reading of a system to which a memory is applied using the variable address control device shown in FIG. 2; FIG.

Claims (4)

In the memory control method using a variable address control device for controlling the data writing and reading of the memory device used in the system, Receiving data divided into predetermined units from the outside and specifying and generating an index for each divided unit; Receiving an index for each unit and generating an initial address for each unit of data divided into a predetermined unit; Receiving an initial address for each unit and generating a variable data write and read address for each unit in response to a clock signal input from an external device, wherein data write and read are performed in the same memory device. Memory control method, characterized in that. The method of claim 1, And generating a data write and read address for each unit, wherein the programmable counter is used. In the method of controlling the memory when the data write and read times of the memory elements used in the system are not equal to each other, Receiving data divided into predetermined units from the outside and specifying and generating an index for each divided unit; Receiving an index for each unit and generating an initial address for each unit of data divided into a predetermined unit; And receiving a initial address for each unit and generating a data write address for each unit in response to a clock signal input from the outside, thereby preventing a data collision occurring during data writing and reading. The method of claim 3, wherein And generating a data write and read address for each unit, wherein the programmable counter is used.

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