JPS5935256A - Status history device - Google Patents

Abstract

PURPOSE:To realize a status history device which uses the time series an input signal as storage stop condition, by comparing an input signal value with a comparison value at intervals of time specified by an external synchronizing signal, and detecting the time series of the input signal and generating a storage stop trigger. CONSTITUTION:The comparison value for the input signal is stored previously in the 2nd internal storae deivce 7. When the input signal is stored in the 1st storage device 9, comparison value is read out of the storage device 7 at intervals of the time specified by the external synchronizing signal 208 and compared with the input signal. If dissidence occurs, the storage stop trigger 207 is generated to stop the storage into the storage device 6. Then, storaed data is transferred from the storage device 6 to a display device 8 by an external proper means and the status history of the input signal is observed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a state history device (tracer).

[Hikirai technology]

Conventionally, in this type of state history device, a trigger generation circuit has an input signal 1(X)-r <
t=1.2. ......t n) and comparison signal 10
1-r<t=1.2. . . t”) and the comparison valid instruction signal 102-i (1=1e 21-・mark -I n ) are input to the AND gates 1-i, 2
- t, 4 ('=L2,...s n) and or gate 3-t (i=l.

2, . This method has a drawback in that it is not possible to generate triggers in time series, which is a major limitation on the range of use of the state history device.

[Purpose of the invention]

An object of the present invention is to detect the time series of an input signal by sequentially reading out comparison values stored in advance and comparing the input signal value and the comparison value at each time specified by an external synchronization signal. The object of the present invention is to provide a device that eliminates the above drawbacks by generating a storage stop trigger.

[Structure of the Invention] According to the present invention, input signals of a plurality of channels are stored according to a preset internal period or an external synchronization signal, and the addresses are updated in the first internal storage device and the external synchronization signal. A second internal memory that stores in advance a time series of comparison values with input signals for each channel at each time and a time series of comparison valid values indicating whether the comparison is valid or invalid for each channel at each time. a means for reading out the stored comparison value for each channel and the comparison effective value for each channel from the stored start address of the second internal storage device in response to a comparison start instruction signal; means for comparing the input signal value and the read comparison value for each channel for which the read comparison valid value is true in synchronization with the external synchronization signal; 1) if all the comparison results match; For example, means for updating the address of the second internal storage device and reading out the next comparison value and the next comparison effective value for comparison in synchronization with the next external synchronization signal, and means for reading out the next comparison value and the next comparison effective value for comparison in synchronization with the next external synchronization signal, and if the comparison result does not match. means for generating a storage stop trigger to the first internal storage device when the storage stop trigger occurs; A state history device comprising means for stopping storage of input signals in a first internal storage device, and means for outputting data stored in the first internal storage device after the storage is stopped. can get.

[Explanation of Examples]

Next, the present invention will be explained in detail with reference to all the drawings.

In FIG. 2 showing an embodiment of the present invention, the state history device of the present invention includes a storage stop trigger generation circuit 5 and a storage device 6.
．． 7, a display device 8, counters 9 and 11 giving the address of the storage device 6.7, and a signal 251 for actually stopping the storage of the input signal 100 to the storage device 6 after the storage stop trigger occurs.5- A counter 10 that outputs all outputs, a flip-flop 15 that displays that storage is in progress in the storage device 6, a flip-flop 16 that instructs the counter 10 to be updated, and a comparison value and a comparison valid value that are read out from the storage device 7 and used as input signal values. The comparison value is written directly to the storage device 7 from a switch etc., or the input signal once collected in the storage device 6 is written to the storage device 7. a selection circuit 12 that selects the data bus of , a comparison start signal generation circuit 13 that instructs to start a comparison operation between the comparison value read from the storage device 7 and the input signal value, and the AND gates 20, 21 . 22゜23.24,25,
26, 27.28, orgate 30, 31.32,
Delay circuits 40, 41 and 42 are included; 204 is a timing signal for storing input signals; 208 is an input signal 10;
205 is a pulse signal that enables the state history device.

FIG. 3 is a detailed circuit diagram of an example of the comparison start signal generation circuit 13, in which the input signal xoo-1 (t=1°2.
...n) and the condition signal 131 specified from the outside.
− + (;=t, 2.....e ”) *
132-1 (t=1.2...on) and generates a comparison start signal 206 instructing the start of the comparison operation.

FIG. 4 is a detailed circuit diagram of an example of the stop trigger generation circuit 5, in which comparison values 121-i are sequentially read out from the storage device 7.
(i = 1, 2...n), and the comparative effective value 122-
t<1=xe2. . . . e”) and the input signal 100-i (i=11 L . . . , n) to cause all storage stop trigger signals 207 to be activated.

Next, the operation of one embodiment of the state history device of the present invention will be explained using all of FIGS. 2 to 4.

First, a switch or the like is used to set from the outside what value the input signal should take to cause the state history device of the present invention to start the comparison operation, and the signal becomes 131°132.

Next, the comparison value with the input signal at each time at which the comparison is performed and the comparison valid value are written into the storage device 7 in ascending address order. At this time, address 114. Address set signal 212
．． Comparison value 111. Comparison effective value 112. A write instruction signal 211 to the storage device 7 is given, and the selection circuit 12 selects the comparison value 1.
11 is its output 120.

Next, a switch or the like is used to set from the outside how many inputs have to be stored after the trigger is generated to actually stop storing data in the storage device 6, and the output becomes 113.

After that, an instruction to enable the state history device is given by a switch or the like, and when the output is inputted as a pulse on the signal 205, the signal 113 is set in the counter 10, and the flip-flop 15 is activated. The AND gate 23 passes the timing signal 204 for input storage, and its output signal 250 is used as a write instruction signal to the storage device 6, and the input signal 100 is written to the address 115 indicated by the total counter 9. It's crowded. Also signal 2
50 is or gate 30. The counter 9 is updated via the delay circuit 40'. As described above, the input signal is written into the storage device 6 every clock.

Next, when the input signal takes a value that satisfies the above-mentioned fil1 matching condition given to the comparison start signal generation circuit 3, a comparison start signal 206 is generated and passes through the AND gate 20 to the comparison operation in progress display flip-flop 17. Set all. After this, the comparison between the input signal and the comparison value read from the storage device 7 becomes valid, and the address 11 given by the counter 11 becomes valid.
The contents of the storage device 7 are read out using 6 as a read address, and are applied to the storage stop trigger generation circuit 5 as a comparison value 121 and a comparison valid value 122.

As shown in FIG. 4, the storage stop trigger generation circuit 5 generates a comparison value 12t-Bt=t, 2. ...m”), comparative effective value 122-i < i=x, 2.
n), input signal 1oo-i (+=1.2...
+”) is given, the input signal 1oo-J and the comparison value 121 for all j whose comparison valid value 122-j is 1
-j, and if there is even one mismatch among these comparison results, a storage stop trigger signal 207 is generated. On the other hand, if all J's are matched, the storage stop trigger signal 207' is not generated.

If all the above comparisons match, the storage stop trigger 207 is not generated and the flip-flop 17 is set.

The default state is maintained and the comparison timing signal 208 is passed through the AND gate 24. Orgate 31. Address 1 of the storage device 7 is updated by updating the counter 11 via the delay circuit 42.
16 is updated and read out in preparation for the next comparison. In this way, the storage device 7 is read and compared with the input until a discrepancy occurs.

The counter 11 is repeatedly updated, and the time series of the input signal is compared with the time series of comparison values stored in advance.

When a mismatch occurs in the comparison, a storage stop trigger 20 is generated.
7 is issued, the flip-flop and knob 17 are reset through the AND gate 28, and at the same time, the flip-flop 1 is reset.
6 is set. The output of the flip-flop 16 instructs the counter 10 to be updated at every storage timing 204 in the storage device 6, and when an overflow occurs due to repeated updates from the initial value set by the above-mentioned 205 and 113, the signal line 251 all 1
Make it. When the signal @251 becomes t'1'', the flip-flop 15 is reset and storage in the storage device 6 is stopped. After the storage is stopped, Q203't is
When set to l, stored data is transferred from the storage device 6 to the display device 8, and the state history of the stored input signal is observed.

〔Effect of the invention〕

As explained above, in the present invention, the comparison values with the input signal are stored in advance in the second internal storage device, and the first
When an input signal is stored in the internal storage device of the device, the stored comparison value is read at every time determined by an external synchronization signal and compared with the input signal, and when a mismatch is detected, a storage stop trigger is generated. This method has the effect of realizing a complete state history device with a condition for stopping the storage of all time-series input signals, which was impossible in the previous method.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of a trigger generation circuit of a conventional state history device, Fig. 2 is a block circuit diagram of an embodiment of the invention, and Fig. 3 is a detailed circuit diagram of an example of the comparison start signal generation circuit in Fig. 2. 4 is a detailed circuit diagram of an example of the storage stop trigger generation circuit 5 in FIG. 2. 1-1. ......, 1-n, 2-1.・・・・・・
, 2-n. 20.21, 22, 23.24, 25, 26.27...
...antogame), 3-1. ..., 3-[1
, 30° 31. 32... Or Gate, 6. 7
...Internal storage device, 8...Display device,
9, 10.11... Counter, 15, 16.1
7...Flip-flop, 40.41.42...
...Delay circuit, 12...Selection circuit.

Claims (1)

[Claims] A first internal storage device that stores input signals of multiple channels according to a preset internal period or an external period signal and updates the addresses thereof, and an input for each channel at each time specified by an external synchronization signal. a second internal storage device that stores in advance a time series of comparison values with the signal and a time series of comparison valid values that instruct whether the comparison is valid or invalid for each channel at each time; and a comparison start instruction signal. means for reading the stored comparison value for each channel and the comparison valid value for each channel from the stored top address of the second internal storage device, and the read comparison valid value is true. means for comparing the input signal value and the read comparison value for each channel in synchronization with the external synchronization signal, and updating the address of the second internal storage device if all the comparison results match. Then the next outside■
a means for generating a next comparison value and a next valid comparison value for comparison in synchronization with a synchronization signal; and a storage stop trigger in the first N storage device when a discrepancy occurs in the comparison results. and stopping the storage of the input signal in the first internal storage device when the internal period or the external synchronization signal has passed a preset number of times after generating the storage stop trigger. and means for outputting the data stored in the first internal storage device after the storage is stopped.