JPH04151861A - Manufacture of hybrid integrated circuit - Google Patents
Manufacture of hybrid integrated circuitInfo
- Publication number
- JPH04151861A JPH04151861A JP2275852A JP27585290A JPH04151861A JP H04151861 A JPH04151861 A JP H04151861A JP 2275852 A JP2275852 A JP 2275852A JP 27585290 A JP27585290 A JP 27585290A JP H04151861 A JPH04151861 A JP H04151861A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- wiring board
- solder bumps
- wire bonding
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000004065 semiconductor Substances 0.000 claims abstract description 61
- 229910000679 solder Inorganic materials 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims abstract description 23
- 238000010438 heat treatment Methods 0.000 claims abstract description 14
- 239000002184 metal Substances 0.000 claims abstract description 12
- 229910052751 metal Inorganic materials 0.000 claims abstract description 12
- 238000002844 melting Methods 0.000 claims abstract description 6
- 230000008018 melting Effects 0.000 claims abstract description 6
- 229920005989 resin Polymers 0.000 claims abstract description 6
- 239000011347 resin Substances 0.000 claims abstract description 6
- 238000007789 sealing Methods 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 description 23
- 239000003990 capacitor Substances 0.000 description 5
- 239000004020 conductor Substances 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000006023 eutectic alloy Substances 0.000 description 2
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 2
- 239000005011 phenolic resin Substances 0.000 description 2
- 229920001568 phenolic resin Polymers 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 239000012808 vapor phase Substances 0.000 description 2
- 238000010923 batch production Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000010309 melting process Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は混成集積回路の製造方法に関し、特に複数の半
導体素子を配線基板に搭載する混成集積回路の製造方法
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a hybrid integrated circuit, and particularly to a method for manufacturing a hybrid integrated circuit in which a plurality of semiconductor elements are mounted on a wiring board.
従来の混成集積回路の製造方法において、半導体素子を
配線基板に搭載する技術として、ワイヤボンティング技
術およびフリップチップ技術か用いられている。In conventional methods for manufacturing hybrid integrated circuits, wire bonding technology and flip chip technology are used as technologies for mounting semiconductor elements on wiring boards.
ワイヤボンディング技術による混成集積回路の従来の製
造方法は、第３図（ａ）〜（ｃ）に示すように、まず配
線基板１に半導体素子２を固着しく第３図（ａ））、次
に半導体素子２に設けられた電極３と配線基板１に設け
られた電極４とを金属細線５により接続しく第３図（ｂ
））、半導体素子２と金属細線５を樹脂６により封止す
る（第３図（Ｃ））ようになっている。The conventional manufacturing method of a hybrid integrated circuit using wire bonding technology is as shown in FIGS. 3(a) to 3(c). First, a semiconductor element 2 is fixed to a wiring board 1 (FIG. 3(a)), and then a The electrode 3 provided on the semiconductor element 2 and the electrode 4 provided on the wiring board 1 are connected by a thin metal wire 5 as shown in FIG.
)), the semiconductor element 2 and the thin metal wire 5 are sealed with a resin 6 (FIG. 3(C)).
フリップチップ技術は、半導体素子の搭載密度をさらに
向上する技術てあり、このフリップチップ技術による半
導体素子の搭載方法は、第４図（ａ＞、（ｂ）に示され
る。まず半田ハンプ７か形成されている半導体素子２ａ
を配線基板１に載置しく第４図（ａ））、次に半田バン
プ７を加熱溶融して配線基板］に半導体素子２ａを接続
する（第４図（ｂ））。Flip-chip technology is a technology that further improves the mounting density of semiconductor devices, and the method of mounting semiconductor devices using this flip-chip technology is shown in FIGS. The semiconductor element 2a that is
is placed on the wiring board 1 (FIG. 4(a)), and then the semiconductor element 2a is connected to the wiring board by heating and melting the solder bumps 7 (FIG. 4(b)).
このフリップチップ技術とワイヤボンディング技術を比
較すると、フリップチップ技術では半導体素子２ａに半
田バンプ７を形成するという通常の半導体装置の製造工
程に含まれていない工程を必要とするなめに、半導体素
子２ａの入手が困難であること、トランジスタ素子のよ
うに半導体素子の裏面から接続をとる必要のある半導体
素子には適用か困難であることから、従来の混成集積回
路の製造方法においては、ワイヤホンディング技術が広
く採用されている。Comparing this flip-chip technology and wire bonding technology, it is found that the flip-chip technology requires a process of forming solder bumps 7 on the semiconductor element 2a, which is not included in the normal semiconductor device manufacturing process. Because wire bonding is difficult to obtain and is difficult to apply to semiconductor devices such as transistor devices that require connections from the back side of the semiconductor device, wire bonding is The technology is widely adopted.
従来のワイヤボンディング技術による混成集積回路の製
造方法では、金属細線５による接続は一般に熱圧着方式
を用いるために、半導体素子２が固着された配線基板１
を少なくとも１５０℃以上、望ましくは３００〜３５０
°Ｃに昇温する必要があり、通常ヒータブロック等によ
る下地加熱方式が採られている。従って、ワイヤボンデ
ィング技術による半導体素子の配線基板の表裏両面の実
装は実用上困難であった。In the conventional manufacturing method of a hybrid integrated circuit using wire bonding technology, since the connection using thin metal wires 5 is generally made by thermocompression bonding, the wiring board 1 to which the semiconductor element 2 is fixed is
at least 150°C or higher, preferably 300-350°C
It is necessary to raise the temperature to °C, and a base heating method using a heater block or the like is usually used. Therefore, it has been practically difficult to mount a semiconductor element on both the front and back sides of a wiring board using wire bonding technology.
また、フリップチップ技術によれば、雰囲気加熱を行う
ことにより半導体素子の両面実装を行うことは可能であ
るが、片側の面に搭載される半導体素子と、他方の面に
搭載される半導体素子の半田バンプは互いに異なる半田
材料で形成する必要があるため、半田バンプ形成コスト
の上昇を招くこと、半導体素子に管理コストの上昇を招
くこと、半田バンプの加熱溶融工程を配線基板の両面で
別々に設ける必要があることのような問題点があった。In addition, according to flip-chip technology, it is possible to perform double-sided mounting of semiconductor elements by heating the atmosphere, but the semiconductor element mounted on one side and the semiconductor element mounted on the other side are Since solder bumps must be formed using different solder materials, there are problems such as an increase in the cost of forming solder bumps, an increase in management costs for semiconductor devices, and the need to perform the heating and melting process of solder bumps separately on both sides of the wiring board. There were problems such as the need to set up
本発明の目的は、これらの問題を解決し、半導体素子の
両面実装を可能にし、混成集積回路の製造方法を提供す
ることにある。An object of the present invention is to solve these problems, enable double-sided mounting of semiconductor elements, and provide a method for manufacturing a hybrid integrated circuit.
本発明の混成集積回路の製造方法の構成は、配線基板の
片方の面に第１の半導体素子を固着する工程と、前記第
１の半導体素子の電極と前記配線基板の電極とを金属細
線により接続する工程と、前記第１の半導体素子と前記
金属細線を樹脂により封止する工程と、前記配線基板の
他方の面に、半田バンプが形成された第２半導体素子を
載置する工程と、前記半田バンプを加熱溶融して前記配
線基板に前記第２の半導体素子を接続する工程とを含む
ことを特徴とする。The method for manufacturing a hybrid integrated circuit according to the present invention includes a step of fixing a first semiconductor element to one surface of a wiring board, and connecting an electrode of the first semiconductor element and an electrode of the wiring board with a thin metal wire. a step of connecting, a step of sealing the first semiconductor element and the thin metal wire with a resin, a step of placing a second semiconductor element with solder bumps formed on the other surface of the wiring board, The method is characterized by including a step of heating and melting the solder bumps to connect the second semiconductor element to the wiring board.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）〜（ｅ）は本発明の一実施例を工程順に説
明する断面図である。FIGS. 1(a) to 1(e) are cross-sectional views illustrating an embodiment of the present invention in the order of steps.
まず、厚膜印刷基板］−〇に片方の面に設けられた導体
配線１１の所定の位置にスクリーン印刷技術を用いて銀
／エポキシペーストを塗布した上に半導体素子２を載置
した後、３００℃３０分の条件でその銀／エポキシペー
ストを硬化して半導体素子２を厚膜印刷基板１０に固着
する（第１図（ａ））。First, silver/epoxy paste was applied to a predetermined position of the conductor wiring 11 provided on one side of the thick film printed board]-- by screen printing technology, and then the semiconductor element 2 was placed on it. The silver/epoxy paste is cured for 30 minutes at a temperature of 0.degree. C., thereby fixing the semiconductor element 2 to the thick film printed substrate 10 (FIG. 1(a)).
次に、厚膜印刷基板１０を下地加熱方式により３００℃
に昇温して、半導体素子２上に設けられた電極３と厚膜
印刷基板１０に設けられた電極４とをワイヤボンディン
グ技術を用いて、３０μｍ径金線１５により接続する（
第１図（ｂ））。Next, the thick film printed circuit board 10 is heated to 300°C using a base heating method.
The electrode 3 provided on the semiconductor element 2 and the electrode 4 provided on the thick film printed substrate 10 are connected by a 30 μm diameter gold wire 15 using wire bonding technology.
Figure 1(b)).
次に、半導体素子２と金線］５をフェノール系樹脂６で
被覆した後、１８０℃２時間の条件でフェノール系樹脂
６を硬化する（第１図（Ｃ））。Next, the semiconductor element 2 and the gold wire] 5 are coated with a phenolic resin 6, and then the phenolic resin 6 is cured at 180° C. for 2 hours (FIG. 1(C)).
一方、厚膜印刷基板１０の反対側の面には導体配線つと
保護ガラス層８が設けられており、この面上に鉛−スズ
共晶合金からなる半田バンプ７が形成された半導体素子
２ａを保護ガラス層８の開口部と半田バンプ７とが対向
するように位置合わせして厚膜印刷基板１０に載置する
（第１図（ｄ））。On the other hand, a conductor wiring layer and a protective glass layer 8 are provided on the opposite surface of the thick film printed circuit board 10, and a semiconductor element 2a on which solder bumps 7 made of a lead-tin eutectic alloy are formed is mounted. It is placed on the thick film printed circuit board 10 with alignment so that the opening of the protective glass layer 8 and the solder bump 7 face each other (FIG. 1(d)).
続いて、半導体素子２ａが載置された厚膜印刷基板１０
を蒸気相加熱方式により２１５℃に昇温して半田バンプ
７を加熱溶融して厚膜印刷基板１０と半導体素子２ａの
接続を行う（第１図（ｅ））。Subsequently, a thick film printed substrate 10 on which the semiconductor element 2a is mounted
The temperature is raised to 215° C. by a vapor phase heating method, and the solder bumps 7 are heated and melted to connect the thick film printed circuit board 10 and the semiconductor element 2a (FIG. 1(e)).
本実施例において、半導体素子２の厚膜印刷基板１０へ
の実装は、従来のワイヤボンディング技術と実質上同一
であり、従来の製造装置をそのまま流用することができ
る。また反対面の半導体素子２ａの実装は半田バンプ７
の加熱溶融を蒸気相加熱方式で行っているので半導体素
子２が裏面に実装されていても半田バンプ７の加熱は均
一に行うことができる。In this embodiment, the mounting of the semiconductor element 2 on the thick film printed circuit board 10 is substantially the same as the conventional wire bonding technique, and the conventional manufacturing equipment can be used as is. Also, the semiconductor element 2a on the opposite side is mounted using solder bumps 7.
Since heating and melting is performed using a vapor phase heating method, even if the semiconductor element 2 is mounted on the back surface, the solder bumps 7 can be heated uniformly.
第２図（ａ）〜（ｃ）は本発明の第２の実施例を工程順
に説明する断面図である。第１実施例と同様の方法によ
り半導体素子２を厚膜印刷基板１０の片方の面に実装し
た後、厚膜印刷基板１０の反対側の面に設けられた導体
配線９の所定の位置にスクリーン技術を用いて半田ペー
スト１７を塗布した上にチップコンデンサ１８を載置す
る（第２図（ａ））。FIGS. 2(a) to 2(c) are cross-sectional views illustrating a second embodiment of the present invention in the order of steps. After the semiconductor element 2 is mounted on one side of the thick film printed circuit board 10 by the same method as in the first embodiment, a screen is placed at a predetermined position of the conductor wiring 9 provided on the opposite surface of the thick film printed circuit board 10. A chip capacitor 18 is placed on the solder paste 17 applied using a technique (FIG. 2(a)).
次に、鉛−スズ共晶合金からなる半田バンプ７が形成さ
れた半導体素子２ａを保護ガラス層８の開口部と半田バ
ンプ７が対向するように位置合わせして厚膜印刷基板１
．０に載置する（第２図（ｂ））。Next, the semiconductor element 2a on which the solder bumps 7 made of a lead-tin eutectic alloy are formed is aligned so that the opening of the protective glass layer 8 and the solder bumps 7 face each other, and the thick film printed circuit board 2 is placed.
．． 0 (Fig. 2(b)).
続いて、チップコンデンサ１８と半導体素子２ａが載置
された厚膜印刷基板１０を赤外線加熱方式により２３０
’Ｃに昇温して半田ペースト１７と半田バンプ７とを
加熱溶融してチップコンデンサ１８と半導体素子２ａの
厚膜印刷基板１０への接続を行う（第２図（Ｃ）〉。Subsequently, the thick film printed circuit board 10 on which the chip capacitor 18 and the semiconductor element 2a are placed is heated at 230 by an infrared heating method.
The solder paste 17 and the solder bumps 7 are heated and melted by increasing the temperature to 'C, thereby connecting the chip capacitor 18 and the semiconductor element 2a to the thick film printed circuit board 10 (FIG. 2(C)).
本実施例においては半田ペースト１７と半田バンプ７の
加熱溶融を赤外線加熱方式により一括して行うことによ
りチップコンデンサ１８と半導体素子２ａを厚膜印刷基
板］０上に一括処理で接続できる。In this embodiment, the solder paste 17 and the solder bumps 7 are heated and melted all at once using an infrared heating method, so that the chip capacitor 18 and the semiconductor element 2a can be connected to the thick film printed circuit board 0 in a batch process.
なお、半導体素子２としてトランジスタ素子、半導体素
子２ａとしてゲートアレイ素子を用いることができる。Note that a transistor element can be used as the semiconductor element 2, and a gate array element can be used as the semiconductor element 2a.
このトランジスタ素子はコレクタ接続を素子の裏面から
とる必要があるためワイヤボンディング技術による実装
を行い、ゲートアレイ素子は接続端子数が多いことから
フリップチップ技術採用することにより、ワイヤボンデ
ィング技術の場合に比較して搭載占有領域を著しく縮小
できる。Since the collector connection of this transistor element needs to be made from the back side of the element, it is mounted using wire bonding technology.Since gate array elements have a large number of connection terminals, flip-chip technology is used, compared to the case of wire bonding technology. The mounting area can be significantly reduced.
以上説明したように本発明は、配線基板の片面に第１の
半導体素子を固着し、第１の半導体素子の電極と配線基
板の電極とを金属細線により接続し、第１の半導体素子
と金属細線とを樹脂により被覆封止し、半田バンプが形
成された第２の半導体素子を配線基板の裏面に載置し、
その半田バンプを加熱溶融して配線基板に第２の半導体
素子を接続することにより、従来の製造方法では困難で
あった半導体素子の両面実装を容易に実現することがで
きると共に、ワイヤボンディング技術とフリップチップ
技術を併用しているので、個々の半導体素子の有する特
性に応じて最適な実装技術を選択でき、混成集積回路の
高機能化、高密度化を図ることができるという効果を有
する。As explained above, the present invention fixes a first semiconductor element to one side of a wiring board, connects the electrode of the first semiconductor element and the electrode of the wiring board with a thin metal wire, and connects the first semiconductor element to the metal wire. The thin wires are coated and sealed with resin, and a second semiconductor element on which solder bumps are formed is placed on the back surface of the wiring board,
By heating and melting the solder bumps and connecting the second semiconductor element to the wiring board, it is possible to easily realize double-sided mounting of the semiconductor element, which was difficult with conventional manufacturing methods, and also with wire bonding technology. Since flip-chip technology is also used, the optimum mounting technology can be selected according to the characteristics of each semiconductor element, and this has the effect of increasing the functionality and density of the hybrid integrated circuit.
【図面の簡単な説明】
第１図（ａ）〜（ｅ）は本発明の一実施例を工程順に説
明する断面図、第２図（ａ）〜（Ｃ）は本発明の第２の
実施例を工程順に説明する断面図、第３図（ａ）〜（ｃ
）は従来のワイヤボンディング技術を工程順に示す断面
図、第４図（ａ）、（ｂ）は従来のフリップチップ技術
を工程順に示す断面図である。
１・・・配線基板、２，２ａ・・・半導体素子、３，４
・・・電極、５・・・金属細線、６・・・樹脂、７・・
・半田バンプ、８・・・保護ガラス層、９．１１・・・
導体配線、１０・・・厚膜印刷基板、１５・・・金線、
１７・・・半田ペースト、１８・・・チップコンデンサ
。[BRIEF DESCRIPTION OF THE DRAWINGS] FIGS. 1(a) to (e) are sectional views explaining one embodiment of the present invention in the order of steps, and FIGS. 2(a) to (C) are sectional views of a second embodiment of the present invention. Cross-sectional views explaining examples in the order of steps, FIGS. 3(a) to (c)
) is a cross-sectional view showing the conventional wire bonding technique in the order of steps, and FIGS. 4(a) and 4(b) are cross-sectional views showing the conventional flip-chip technique in the order of steps. 1... Wiring board, 2, 2a... Semiconductor element, 3, 4
...electrode, 5...metal thin wire, 6...resin, 7...
・Solder bump, 8...protective glass layer, 9.11...
Conductor wiring, 10... Thick film printed board, 15... Gold wire,
17...Solder paste, 18...Chip capacitor.
Claims (1)
程と、前記第１の半導体素子の電極と前記配線基板の電
極とを金属細線により接続する工程と、前記第１の半導
体素子と前記金属細線を樹脂により封止する工程と、前
記配線基板の他方の面に、半田バンプが形成された第２
半導体素子を載置する工程と、前記半田バンプを加熱溶
融して前記配線基板に前記第２の半導体素子を接続する
工程とを含むことを特徴とする混成集積回路の製造方法
。a step of fixing a first semiconductor element to one surface of a wiring board; a step of connecting an electrode of the first semiconductor element and an electrode of the wiring board with a thin metal wire; and a step of connecting the first semiconductor element and the a step of sealing the thin metal wire with resin; and a second step of forming solder bumps on the other surface of the wiring board.
A method for manufacturing a hybrid integrated circuit, comprising the steps of: mounting a semiconductor element; and heating and melting the solder bumps to connect the second semiconductor element to the wiring board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2275852A JP2841822B2 (en) | 1990-10-15 | 1990-10-15 | Manufacturing method of hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2275852A JP2841822B2 (en) | 1990-10-15 | 1990-10-15 | Manufacturing method of hybrid integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04151861A true JPH04151861A (en) | 1992-05-25 |
| JP2841822B2 JP2841822B2 (en) | 1998-12-24 |
Family
ID=17561336
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2275852A Expired - Fee Related JP2841822B2 (en) | 1990-10-15 | 1990-10-15 | Manufacturing method of hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2841822B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6154372A (en) * | 1993-09-02 | 2000-11-28 | Siemens Aktiengesellschaft | Multichip module for surface mounting on printed circuit boards |
-
1990
- 1990-10-15 JP JP2275852A patent/JP2841822B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6154372A (en) * | 1993-09-02 | 2000-11-28 | Siemens Aktiengesellschaft | Multichip module for surface mounting on printed circuit boards |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2841822B2 (en) | 1998-12-24 |
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