JPH04150218A - Oscillation circuit - Google Patents
Oscillation circuitInfo
- Publication number
- JPH04150218A JPH04150218A JP2271830A JP27183090A JPH04150218A JP H04150218 A JPH04150218 A JP H04150218A JP 2271830 A JP2271830 A JP 2271830A JP 27183090 A JP27183090 A JP 27183090A JP H04150218 A JPH04150218 A JP H04150218A
- Authority
- JP
- Japan
- Prior art keywords
- comparator
- output
- oscillation
- terminal
- input terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010355 oscillation Effects 0.000 title claims abstract description 34
- 239000003990 capacitor Substances 0.000 claims abstract description 15
- 238000010586 diagram Methods 0.000 description 10
- 238000007599 discharging Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、発振回路に関し、 に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to an oscillation circuit, Regarding.
特にＣＲ発振回路 用いて説明する。 Especially CR oscillation circuit I will explain using
この回路は、２個のインバータ２１．２２と、抵抗Ｒ３
゜、コンデンサＣ１゜とからなる。インバータ２１の出
力がＨレベル、インバータ２２の出力がＬレベルの時、
抵抗Ｒ０゜とコンデンサＣ１゜との充放電によりｄ点の
電位がＬからＨレベルへ変化し、インバータ２１の論理
スレショールド電圧ｖＴヨ以上になると、インバータ２
１の出力がＬレベル、インバータ２２の出力がＨレベル
に反転シ、今度は抵抗Ｒ１゜とコンデンサＣ１゜との充
放電によりｄ点電位がＨからＬレベルへ変化してインバ
ータ２１の論理スレショールド電圧Ｖ□以下になると、
再びインバータ２１の出力がＨレベル、インバータ２２
の出力がＬレベルに反転する。This circuit consists of two inverters 21, 22 and a resistor R3.
゜, capacitor C1゜. When the output of inverter 21 is H level and the output of inverter 22 is L level,
When the potential at point d changes from L to H level due to charging and discharging of resistor R0° and capacitor C1°, and becomes higher than the logic threshold voltage vTyo of inverter 21, inverter 2
The output of the inverter 22 is inverted to the L level, and the output of the inverter 22 is inverted to the H level.Now, due to the charging and discharging of the resistor R1° and the capacitor C1°, the potential at point d changes from H to L level, and the logic threshold of the inverter 21 is reached. When the voltage drops below V□,
The output of the inverter 21 is at H level again, and the inverter 22
The output of is inverted to L level.
このような動作を繰り返し行なう事により発振が行われ
る。Oscillation is performed by repeating such operations.
上述した従来の発振回路では、ｄ点の電位が電源電圧以
上に振幅するため、安定した発振出力を得るのは難かし
く、また、集積回路上に構成する事も困難である。さら
に、この種の発振回路では、発振出力のデユーティ比を
設定する事が出来ないという欠点があった。In the conventional oscillation circuit described above, since the potential at point d swings higher than the power supply voltage, it is difficult to obtain a stable oscillation output, and it is also difficult to configure it on an integrated circuit. Furthermore, this type of oscillation circuit has the disadvantage that the duty ratio of the oscillation output cannot be set.
本発明の目的は、これらの欠点を除き、安定した発振出
力で任意のデユーティ比を容易に設定できる発振回路を
提供することにある。An object of the present invention is to provide an oscillation circuit that eliminates these drawbacks and allows easy setting of any duty ratio with stable oscillation output.
本発明の発振回路の構成は、制御電圧を比較器の第１の
入力端子に入力し、この比較器の第２の入力端子と出力
端子との間に第１の抵抗を接続し、この第２の入力端子
と電源端子との間にコンデンサを接続して構成される発
振部と、前記制御電圧が前記比較器の出力により切替え
られるアナログスイッチにより抵抗分割された所定電圧
が供給される制御電圧供給部と、を備えることを特徴と
する。The configuration of the oscillation circuit of the present invention is such that a control voltage is input to a first input terminal of a comparator, a first resistor is connected between a second input terminal and an output terminal of this comparator, and a first resistor is connected between a second input terminal and an output terminal of this comparator. an oscillation unit configured by connecting a capacitor between the input terminal of the second input terminal and the power supply terminal, and a control voltage to which a predetermined voltage is supplied by resistance-dividing the control voltage by an analog switch that is switched by the output of the comparator. A supply unit.
次に本発明について図面を用いて説明する。 Next, the present invention will be explained using the drawings.
第１図は本発明の一実施例の回路図である。この回路は
、電源ｖＤＤと接地との間に直列接続した抵抗Ｒ１〜Ｒ
３の角接点す、ｃを切換えるインバータ８およびアナロ
グスイッチ４，５からなる電圧供給部と、抵抗Ｒ１゜、
コンデンサＣＩＯと比較器１０とからなる発振部とから
構成される。FIG. 1 is a circuit diagram of an embodiment of the present invention. This circuit consists of resistors R1 to R connected in series between the power supply vDD and ground.
A voltage supply unit consisting of an inverter 8 and analog switches 4 and 5 that switch the corner contacts S and C of 3, and a resistor R1°,
It consists of an oscillation section consisting of a capacitor CIO and a comparator 10.
第１の電源端子（ＶＤＤ）１と、第２の電源端子（ＧＮ
Ｄ）３との間に抵抗Ｒ１〜Ｒ３を直列接続し、抵抗Ｒ１
と抵抗Ｒ２との接続端子すとアナログスイッチ４の第１
の端子（入力端子）とを接続し、抵抗Ｒ２と抵抗Ｒ１と
の接続端子Ｃとアナログスイッチ５の入力端子との接続
する。また、コンデンサＣ１゜の第１の端子と第２の電
源端子３とを接続し、アナログスイッチ４の出力端子と
アナログスイッチ５の出力端子と比較器１０の第１の入
力端子（＋）とを接続し、比較器１０の第２の入力端子
（−）とコンデンサＣ１゜の第２の端子と抵抗Ｒ１゜の
第１の端子とを接続し、比較器１０の出力端子と発振出
力端子２と抵抗Ｒ１゜の第２の端子とを接続している。The first power terminal (VDD) 1 and the second power terminal (GN
D) Connect resistors R1 to R3 in series between R1 and R3.
and the connection terminal between resistor R2 and the first terminal of analog switch 4.
(input terminal), and the connection terminal C between the resistor R2 and the resistor R1 is connected to the input terminal of the analog switch 5. Also, the first terminal of the capacitor C1° and the second power supply terminal 3 are connected, and the output terminal of the analog switch 4, the output terminal of the analog switch 5, and the first input terminal (+) of the comparator 10 are connected. The second input terminal (-) of the comparator 10, the second terminal of the capacitor C1°, and the first terminal of the resistor R1° are connected, and the output terminal of the comparator 10 and the oscillation output terminal 2 are connected. It is connected to the second terminal of the resistor R1°.
この比較器１０の出力によりアナログスイッチ４，５０
オン、オフが制御される回路で構成される。The output of this comparator 10 causes the analog switches 4 and 50 to
It consists of a circuit that is controlled to turn on and off.
この発振回路の場合、比較器１０の出力がＨレベルとす
ると、アナログスイッチ４がオン、アナログスイッチ５
がオフとなり、比較器１０の＋側入力端子には電源電圧
を抵抗Ｒ１〜Ｒ３で分圧されたｂ点の電位が入力される
。In the case of this oscillation circuit, when the output of the comparator 10 is at H level, the analog switch 4 is turned on and the analog switch 5 is turned on.
is turned off, and the potential at point b, which is obtained by dividing the power supply voltage by the resistors R1 to R3, is input to the + side input terminal of the comparator 10.
ここで第１の電源端子ｌの入力電圧をＶ工、第２の電源
端子３０入力電圧をＧＮＤ＝ＯＶとすると、ｂ点の電位
は次式で表わされる。Here, if the input voltage of the first power supply terminal l is V and the input voltage of the second power supply terminal 30 is GND=OV, then the potential at point b is expressed by the following equation.
Ｒｌ””’ Ｒｓの抵抗値、Ｖつ。は電源電圧とする。Rl””’ Resistance value of Rs, V. is the power supply voltage.
第２図は第１図の各部の動作波形図である。FIG. 2 is an operational waveform diagram of each part of FIG. 1.
一方、比較器１０の一側入力端子には、抵抗Ｒ１゜とコ
ンデンサＣ１゜による充放電電圧（ａ点の電位）が入力
されている。このａ点の電位は、比較器１０の出力がＨ
レベルとするとコンデンサＣ１゜は除々に充電されるが
、やがてｂ点の電位（Ｖ、）以上となった瞬間に（この
時を第２図のｔ、とする）、比較器１０の出力はＬレベ
ルになりアナログスイッチ４がオフ、アナログスイッチ
５がオンとなり、比較器１０の＋側入力端子には抵抗Ｒ
１〜Ｒ３で分圧された０点の電位が入力される。この０
点の電位Ｖ。は（２）式で表わされる。On the other hand, a charging/discharging voltage (potential at point a) generated by a resistor R1° and a capacitor C1° is input to one side input terminal of the comparator 10. The potential at point a is such that the output of the comparator 10 is H.
The capacitor C1° is gradually charged, but at the moment when it reaches the potential (V, ) at point b (this time is designated as t in Figure 2), the output of the comparator 10 becomes L. level, the analog switch 4 is turned off, the analog switch 5 is turned on, and the + side input terminal of the comparator 10 is connected to the resistor R.
The potential at the 0 point divided by 1 to R3 is input. This 0
Potential of point V. is expressed by equation (2).
また、比較器１０の出力がＬレベルになったことで、ａ
点の電位は抵抗Ｒ１゜とコンデンサＣ１゜の時定数で除
々に放電され、やがて０点の電位（Ｖｃ）以下となった
瞬間に（第２図のｔ２とする）、再び比較器１０の出力
はＨレベルになりアナログスイッチ４がオン、アナログ
スイッチ５がオフとなる。Also, since the output of the comparator 10 has become L level, a
The potential at the point is gradually discharged with the time constant of the resistor R1° and the capacitor C1°, and at the moment when it becomes below the zero point potential (Vc) (denoted as t2 in Fig. 2), the output of the comparator 10 is again discharged. becomes H level, analog switch 4 is turned on, and analog switch 5 is turned off.
再び、比較器１０の出力がＨレベルになったことでコン
デンサＣ１゜は充電され始め、ａ点の電位がｂ点の電位
７１以上となった瞬間に（第２図ｔｌとする）、また比
較器１０の出力がＬレベルになる。As the output of the comparator 10 becomes H level again, the capacitor C1° starts to be charged, and at the moment when the potential at point a becomes equal to or higher than the potential 71 at point b (denoted as tl in Fig. 2), the comparison starts again. The output of the device 10 becomes L level.
これらの動作を繰り返す事により発振する。Oscillation occurs by repeating these operations.
次に、この発振回路の発振周波数ｆを求める。Next, the oscillation frequency f of this oscillation circuit is determined.
まず、第２図のｔｌからｔ２までの時間Ｔｌを求める。First, the time Tl from tl to t2 in FIG. 2 is determined.
コンデンサＣ１゜の容量Ｃ，，，抵抗Ｒ１゜の抵抗値ｒ
＋ｏとすると、
次式が得られる。Capacitance C of capacitor C1゜, resistance value r of resistor R1゜
+o, the following formula is obtained.
ｙ ｂｙ ｃ＝ｖ ｂｌ−６ＣＩ＋ ’ ｒ ｌａ・・
・（３）
（３）式に（１）（２）式を代入し、
簡単化すると、
次式と
なる。y by c=v bl-6CI+' r la...
・(3) By substituting equations (1) and (2) into equation (3) and simplifying it, we get the following equation.
ｒ２＋ｒｌ ｒ、＋ｒｚ＋ｒ＋ ＋ｒ２＋ｒ３ 同様に第２図のｔ２からｔ、までの時間Ｔ２を求める。r2+rl r, +rz+r+ +r2+r3 Similarly, time T2 from t2 to t in FIG. 2 is determined.
したがって、 第１図の発振回路の発振周波数ｆ は次式のようになる。therefore, Oscillation frequency f of the oscillation circuit in Figure 1 is as follows.
また、発振出力のデユーティ比ＴＩ／Ｔ２は、（５）、
（６）式より次式のようになる。Moreover, the duty ratio TI/T2 of the oscillation output is (5),
From equation (6), the following equation is obtained.
こりように本実施例の回路によれば、抵抗値を設定する
ことにより、発振周波数およびデユーティ比を可変でき
る発振回路が得られる。According to the circuit of this embodiment, an oscillation circuit can be obtained in which the oscillation frequency and duty ratio can be varied by setting the resistance value.
第３図は本発明の第２の実施例の回路図で、複数の直列
接続抵抗Ｒ１〜Ｒ５の接続点をアナログスイッチ４〜７
で選択する回路が示されている。これらアナログスイッ
チ４〜７は、比較器１０の出力に従ってデータセレクタ
９が切換えている。この場合も同様に、（７）、 （８
）式により周波数、デーティ比が可変できることは明ら
かである。FIG. 3 is a circuit diagram of a second embodiment of the present invention, in which connection points of a plurality of series-connected resistors R1 to R5 are connected to analog switches 4 to 7.
The circuit to be selected is shown. These analog switches 4 to 7 are switched by a data selector 9 according to the output of a comparator 10. In this case as well, (7), (8
) It is clear that the frequency and duty ratio can be varied using the equation.
第４図は本発明の第３の実施例の回路図で、抵抗Ｒ１〜
Ｒ３の接続点を比較器１０の出力によりオ訃
ン・オフされるＮチャンネル型電譚効果トランジスタＱ
１により切換えたものである。FIG. 4 is a circuit diagram of a third embodiment of the present invention, in which resistors R1 to
The connection point of R3 is connected to an N-channel electric current effect transistor Q which is turned on and off by the output of the comparator 10.
1.
以上説明したように本発明によれば、発振回路内の電位
が電源電圧範囲内で動作しており、安定した発振出力が
得られ、かつ抵抗値を設定することにより任意のデユー
ティ比を容易に設定することができる。また、この回路
は集積回路に内蔵するのも容易であり、それが廉価に実
現できるという効果がある。As explained above, according to the present invention, the potential in the oscillation circuit operates within the power supply voltage range, stable oscillation output can be obtained, and any duty ratio can be easily set by setting the resistance value. Can be set. Further, this circuit can be easily incorporated into an integrated circuit, and has the advantage that it can be realized at a low cost.
第１図は本発明の一実施例の回路図、第２図は第１図の
回路の主要信号の波形図、第３図、第４図は本発明の第
２．第３の実施例の回路図、第５図は従来例の回路図、
第６図は第５図の主要信号の波形図である。
ｌ・・・・・・第１の電源端子、２・・・・・・発振出
力端子、３・・・・・・第２の電源端子、４〜７・・・
・・・アナログスイッチ、８，１１，２１．２２・・・
・・・インバータ、９・・・・・・データセレクタ、１
０・・・・・・比較器、Ｒ１−Ｒ６゜Ｒ１゜、Ｒ１１・
・・・・・抵抗％ ｅｌｌ Ｃ２・・・・・・コンデン
サ、Ｑｌ・・・・・・Ｎチャンネル型電界効果トランジ
スタ。
代理人 弁理士 内 原 音
光１
図
Ｆ１２
図
第３図FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a waveform diagram of main signals of the circuit of FIG. 1, and FIGS. 3 and 4 are diagrams of a second embodiment of the present invention. The circuit diagram of the third embodiment, FIG. 5 is the circuit diagram of the conventional example,
FIG. 6 is a waveform diagram of the main signals in FIG. l...First power supply terminal, 2...Oscillation output terminal, 3...Second power supply terminal, 4-7...
...Analog switch, 8, 11, 21.22...
...Inverter, 9...Data selector, 1
0...Comparator, R1-R6゜R1゜, R11.
...Resistance% ell C2...Capacitor, Ql...N-channel field effect transistor. Agent Patent Attorney Otoko Uchihara 1 Figure F12 Figure 3
Claims (1)
器の第２の入力端子と出力端子との間に第１の抵抗を接
続し、この第２の入力端子と電源端子との間にコンデン
サを接続して構成される発振部と、前記制御電圧が前記
比較器の出力により切替えられるアナログスイッチによ
り抵抗分割された所定電圧が供給される制御電圧供給部
と、を備えることを特徴とする発振回路。A control voltage is input to a first input terminal of the comparator, a first resistor is connected between the second input terminal and the output terminal of the comparator, and a voltage between the second input terminal and the power supply terminal is connected. An oscillation unit configured by connecting a capacitor between them, and a control voltage supply unit to which a predetermined voltage obtained by resistance-dividing the control voltage by an analog switch switched by the output of the comparator is supplied. oscillation circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2271830A JPH04150218A (en) | 1990-10-09 | 1990-10-09 | Oscillation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2271830A JPH04150218A (en) | 1990-10-09 | 1990-10-09 | Oscillation circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04150218A true JPH04150218A (en) | 1992-05-22 |
Family
ID=17505457
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2271830A Pending JPH04150218A (en) | 1990-10-09 | 1990-10-09 | Oscillation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04150218A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108809071A (en) * | 2018-08-28 | 2018-11-13 | 上海艾为电子技术股份有限公司 | A kind of SS (soft start) control circuit and Switching Power Supply of Switching Power Supply |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60128708A (en) * | 1983-12-15 | 1985-07-09 | Toshiba Corp | Oscillating circuit |
| JPS6032834B2 (en) * | 1978-03-22 | 1985-07-30 | ダイキン工業株式会社 | Air conditioner timer |
-
1990
- 1990-10-09 JP JP2271830A patent/JPH04150218A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6032834B2 (en) * | 1978-03-22 | 1985-07-30 | ダイキン工業株式会社 | Air conditioner timer |
| JPS60128708A (en) * | 1983-12-15 | 1985-07-09 | Toshiba Corp | Oscillating circuit |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108809071A (en) * | 2018-08-28 | 2018-11-13 | 上海艾为电子技术股份有限公司 | A kind of SS (soft start) control circuit and Switching Power Supply of Switching Power Supply |
| CN108809071B (en) * | 2018-08-28 | 2024-05-03 | 上海艾为电子技术股份有限公司 | Soft start control circuit of switching power supply and switching power supply |
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