JPH0414969A - Picture display device - Google Patents

Abstract

PURPOSE:To allow the display device to cope with a video signal whose scanning line number (vertical scanning frequency) is different by providing a presettable counter to count line number and a deflection data memory to the display device. CONSTITUTION:A deflection memory 57 uses a pulse (e) generated by a pulse generating circuit 53 to read a vertical and horizontal deflection waveform data and a cathode counter 60 uses a 1H pulse (a) generated by the pulse generating circuit 53 as a clock to count a line number thereby counting number of lines shared by one line cathode. The number of lines shared by one cathode is optionally set by using a data setting circuit 61 and a preset pulse (b) to revise a preset value of the cathode counter 60. Thus, the display device copes with a video signal of various line number by having only to revise the vertical deflection data and the preset value of the counter.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention provides a method for deflecting electron beams for each section in the vertical and horizontal directions when a screen is divided into a plurality of sections in the vertical and horizontal directions. The present invention relates to a device that displays a plurality of lines and displays an image as a whole.

2. Description of the Related Art The basic structure of a conventional image display device will be explained with reference to FIG.

This display element consists of a back electrode 1, a line cathode 2 as a beam source, a beam extraction electrode 3, a beam flow control electrode 4, a focusing electrode 5, a horizontal deflection electrode 6, a vertical deflection electrode 7, and a screen in order from the back to the anode side. A plate 8, etc. are arranged, and these are housed inside the vacuum container.

A line cathode 2 serving as a beam source is stretched horizontally so as to generate an electron beam distributed linearly in the horizontal direction.
A plurality of line cathodes 2 are further provided at intervals in the vertical direction (in this description, only seven line cathodes 2A to 2G are shown). In this configuration, the spacing between the line cathodes is 3B and the number of line cathodes is 30, and the number of line cathodes is 2-27. The distance between the linear cathodes 2 cannot be freely increased, but is regulated by the distance between the vertical deflection electrode 7 and the screen 8, which will be described later. As the configuration of these line cathodes 2, 10
It is made by coating the surface of a tungsten rod with a diameter of ~30 μm with an oxide cathode material. As will be described later, the linear cathodes are controlled to sequentially emit electron beams from the upper linear cathode 2a to the lower linear cathode 27 for a predetermined period of time. The beam extraction electrode 3 has a large number of through holes 10 arranged at regular intervals in the horizontal direction facing each of the line cathodes 2a to 27, and allows the electron beam emitted from the line cathode 2 to pass through the through holes 10.
Take it out through.

The beam flow control pole 4 is composed of a plurality of conductive plates 15 each having a through hole 14 corresponding to the through hole 10, and controls the amount of electron beam generated from the line cathode 2 in accordance with the picture element of the video signal. Control is performed in synchronization with the timing of horizontal deflection, which will be described later.

The focusing electrode 5 is composed of a conductor 'Xi +1i J 7 having a through hole 16 corresponding to the through hole 14.

The horizontal deflection electrode 6 is composed of a plurality of conductive plates 18 and 180 arranged vertically along both horizontal sides of the through hole 16, and each conductive plate is provided with a voltage for horizontal deflection. is stamped. The electron beams for each picture element are each deflected in the horizontal direction, and sequentially irradiate each of the R, G, and B phosphors on the screen B to emit light.

In this configuration, each electron beam is deflected by two trios. The vertical deflection electrode 7 is composed of a plurality of LLT plates 19a and 190 arranged horizontally at vertically intermediate positions of the through-holes 16, and a voltage for vertical deflection is applied to the plate 190, which deflects the electron beam. deflected vertically. In this configuration, the electron beam generated from the line cathode is deflected by eight lines in the vertical direction by a pair of electrodes 19a and 90. The 31 vertical deflection electrodes 7 constitute 30 pairs of vertical deflection conductors corresponding to each of the 30 line cathodes, and two vertical deflection conductor pairs are formed on the screen 8 in the vertical direction.
40 horizontal scanning lines are drawn.

As explained above, in this configuration, a plurality of horizontal deflection electrodes 6 and a plurality of vertical deflection electrodes 7 are each arranged in a comb shape. Further, by setting the distance to the screen 8 longer than the distance between the horizontal and vertical deflection electrodes, it becomes possible to irradiate the screen 8 with the electron beam with a small deflection amount.

This allows horizontal and vertical deflection electrodes I can do that.

The screen 8 is constructed by coating the back surface of a glass plate 21 with phosphor 20 in stripes. Although not shown, a metal back and carbon are also coated. Phosphor 20
is provided to irradiate two trios of R, G, and B phosphor pairs by deflecting the main electron beam in the electrode of the electron beam flow control electrode 4 in the vertical direction. It is applied in stripes.

In FIG. 3, the dashed lines drawn on the screen 10 indicate the vertical divisions displayed corresponding to the plurality of line cathodes 2, and the two-dot chain lines indicate the plurality of beam flow control electrodes 4.
Shows the horizontal divisions displayed corresponding to each. FIG. 4 shows an enlarged view of one section partitioned by broken lines and two-dot chain lines. As shown in FIG. 4, it has a width of two trios of R, GB phosphors 20 in the horizontal direction, and a width of eight lines in the vertical direction. In this example, the size of one section is 1 cm in the horizontal direction.
, 3++a in the vertical direction.

Although the phosphors of each of the three colors R, G, and B are shown in stripes in FIG. 4, they may be arranged in a delta.

However, when arranged in a delta shape, it is necessary to apply horizontal and vertical deflection waveforms that are compatible with the arrangement.

In FIG. 3, for convenience of explanation, the aspect ratio is different from the image displayed on the actual screen.

Furthermore, in this configuration, two trios of R, G, and B phosphors are provided for each electrode of the beam flow control electrode 4, but it may be configured with one trio or more than three trios. . However, on the beam flow side? ! One trio or three or more trios of R, G, and B video signals are sequentially separated into the I+ electrode 4, and it is necessary to horizontally deflect them in synchronization with them.

Next, the operation of the drive circuit for driving this display element is as follows.
This will be explained with reference to FIGS. 5 and 6. First, a driving portion that irradiates the screen 8 with an electron beam to display an image will be explained.

The power supply circuit 22 is a circuit for applying a predetermined bias voltage to each electrode of the display element.
3. Apply the DC voltage of ①8 to the screen 8, respectively. The line cathode drive circuit 26 creates line cathode drive pulses (I-MA) using the vertical synchronization signal (2) and the horizontal synchronization signal H. In FIG. 6, various pulses are sent to the horizontal counter 51 using the clock generated by the reference oscillator 50 and the horizontal synchronization signal H.
, is generated by the pulse generation circuit 53, and the vertical counter 52 is operated using the output of one pulse (IH pulse) a during one horizontal scanning period and the vertical synchronization signal V, and the output of the vertical counter 52 is generated by the pulse generation circuit. 53 and a line cathode drive pulse generation circuit 54. A pulse C for determining the start timing of the line cathode and a pulse 8 for line cathode selection are sent from the line cathode drive pulse generation circuit 54 to the line cathode selection circuit 55.
A pulse d is generated for each H period and sent to the line cathode selection circuit 55.

FIG. 7 shows the timing diagram. Each line cathode 2-27
As shown in Figure 7 (I to M), a current flows and heats up while the drive pulse is at a high potential.
The heated state is maintained such that the material (ma) emits electrons during periods of low potential. As a result, electrons are emitted from the 30 line cathodes 2a to 27 only during eight horizontal scanning periods to which low-potential drive pulses (i to ma) are applied, respectively. During the period in which a high potential is applied, the potential applied to the line cathodes 2a-27 is lower than the potential around the line cathode 2 determined by the bias voltage applied to the beam flow control electrode 4 and the beam extraction electrode 3. Since the potential at the line cathode 2 is higher, no electrons are emitted from the line cathode 2.

To construct one screen, the potentials may be sequentially switched from the upper line cathode 2a to the lower line cathode 27 every 8 scanning periods.

Next, the deflection part will be explained. The deflection voltage generation circuit 40 is
Direct memory access controller below C DM
A controller) 41, a memory for storing deflection voltage waveforms (hereinafter referred to as deflection memory) 42, digital-to-analog converters (hereinafter referred to as D/A converters) 43h, 43v, etc., and vertical deflection signals v, v' and a horizontal deflection signal, h'.

In this configuration, 240 horizontal scanning periods are displayed in one field in consideration of overscanning regarding the vertical deflection signal. Further, the memory address area storing vertical deflection position information corresponding to each line is divided into a first field and a second field, each having one set of memory capacity. When displaying, select the corresponding deflection memory 4
Data is read out from 2, converted into an analog signal by a D/A converter 43v, and applied to the vertical deflection electrode 7. The vertical deflection position information stored in the deflection memory 42 is composed of almost regular data for every 8 horizontal scanning periods, and the D/A converted waveform also becomes a vertical deflection signal with approximately 8 levels. However, as mentioned above, it has a memory capacity for two fields, so that the position can be finely adjusted for each horizontal scanning line.

Regarding the horizontal deflection signal, it is necessary to horizontally deflect the electron beam in six stages during one horizontal scanning period, and a memory is provided so that the deflection position can be finely adjusted for each horizontal scanning. Therefore, assuming that 480 horizontal scanning periods are displayed between one frame,
480× 6 =2880 bytes of memory are required, but since the data of the first field and the second field are shared, 1440 bytes of memory are actually used. During display, deflection information corresponding to each horizontal scanning line is read out from the deflection memory 42, converted into an analog signal by a D/A converter 43h, and applied to the horizontal deflection electrode 6. To summarize, during the display period excluding the vertical retrace period of the vertical period, the electron beam emitted from the line cathode to which a low-potential drive pulse is applied among the line cathodes 2A to 27 is beam extracted. 1 horizontally by electrode 3
It is divided into 20 sections and constitutes 120 electron beam rows. The beam amount of this electron beam is controlled by a beam control electrode 4 for each section as described later, and a pair of horizontal deflection signals h that change in approximately six steps as shown in FIG.
, h' are added to R1, G1, B1 of the screen 8 during each horizontal display period.
Then, the phosphors such as R2, G2, and B2 are sequentially irradiated for each horizontal display period/6. Thus, each horizontal line raster divides the electron beam into R1, G1,
A color image can be displayed on the screen 8 by modulating the video signals corresponding to B1, R2, G2, and B2.

Next, the modulation control portion of the electron beam will be explained. First, in FIG. 5, signal input terminals 23R, 23G, 23B
The R, G, and B video signals added to the
sample and hold circuit sets 31a to 31n. Each sample hold group 31a to 31n is R1
6 for Gl, bl, R2, G2, B2
It consists of several sample and hold circuits. The sampling pulse generation circuit 34 has a horizontal period = x (63, 5)
During the horizontal display period (approx.
720 (120×6) sampling pulses Ra1 to Rn2 corresponding to the sample hold circuits for I, bl, R2, G2, and B2 are sequentially generated. Said 7
Six sampling pulses are applied to each of the 120 sample-and-hold circuit sets 31a to 31n, so that each sample-and-hold circuit set has two picture elements for each of the 120 segments of one line. Minute R
1, G1, B1, R2, G2, and B2 are individually sampled and held. Sample and hold 120u R1, G1, B1, R2, C2, B2
The video signal is 1 after the sample hold for 1 line
The data is transferred all at once to 20 sets of memories 32a to 32n by a transfer pulse t, where it is held for the next one horizontal scanning period. The held signal is sent to 120 switching circuits 35a.
~35n added. Switching circuits 35a to 35
n is constituted by a circuit each having individual input terminals for R1, G1, B1, R2, G2, and B2 and a common output terminal for first switching and outputting them. Switching is controlled simultaneously by switching pulses r1, gl, bl, r2, B2, and B2.

The switching pulses r1, gl, bl, r2, B2
, B2 divides each horizontal display period into 6 and switches the switching circuits 353 to 35n for each horizontal display period/6.
1, G1, B1, R2, G2, and B2 are time-divided and sequentially outputted, and supplied to pulse width modulation circuits 37a to 37n. The output of each switching circuit 35a to 35n is applied to 120 sets of pulse width modulation (hereinafter referred to as PWM) circuits 37a to 37n, R1, G1, B1, R2
, G2, and B2, which are pulse width modulated according to the magnitude of each video signal and output. This pulse width modulation circuit 378-37
The output of 120 conductive plates 15 of the beam flow control electrode 4 of the display element is used as a control signal for modulating the electron beam.
are added to each separately.

Next, horizontal deflection and display timing will be explained. R1, G1, B in switching circuits 35a to 35n
1, R2, G2, and B2, and electron beams R1, G1, B1, and R by the horizontal deflection drive circuit 41.
The switching timing and order of the horizontal deflection to the phosphors No. 2, G2, and B2 are synchronously controlled so that they completely match. As a result, when the electron beam is irradiating the R1 phosphor, the irradiation amount of the electron beam is controlled by the R1 control signal, and thereafter G1, B1, R2, G2, and B2 are similarly controlled, so that each picture element R1, Gl, B1,
R2, G2, B2 each phosphor emits light from the R1, G of that picture element.
1, B1, R2, G2, and B2, and each picture element is displayed by emitting light according to the input video signal. Such control is executed for 120 sets (2 pixels each) for one line, and
An image of 240 picture elements per line is displayed, and images are further displayed on the screen 8 by sequentially processing the 240 lines of one field starting from the upper line. Furthermore, the above operations are repeated for each field of the input video signal, and a television signal or the like is displayed on the screen 8. The basic taro and ri necessary for this configuration are supplied from the pulse generation circuit 39 shown in FIG. 5, and the horizontal synchronization signal H1
The timing is controlled by a vertical synchronization signal V.

Problems to be Solved by the Invention However, the control circuit for the image display device as described above cannot cope with video signals having different numbers of scanning lines (vertical scanning frequencies).

In view of the above problems, the present invention provides a control circuit for an image display device that can accommodate various numbers of lines by simply changing the vertical deflection data in the deflection memory and the preset value of the counter.

Means for Solving the Problems In order to solve the above problems, the image display device of the present invention includes:
It has a precentable counter for counting the number of lines and a memory for deflection data.

Effect of the Invention By having the above configuration, the present invention can provide an image display device that can handle video signals having different numbers of scanning lines (vertical scanning frequencies).

EXAMPLE An example of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a line cathode drive circuit and deflection signal generation circuit of an image display device according to an embodiment of the present invention, and FIG. 2 is a timing diagram of various waveforms of the image display device according to an embodiment of the present invention. It is. In Figure 1, 5
0 is a reference oscillator, 51 is a horizontal counter, 52 is a vertical counter, 53 is a pulse generation circuit, 54 is a line cathode drive pulse generation circuit, 55 is a line cathode selection circuit, 56 is a line cathode drive circuit, 57 is a deflection memory, 58 is a D/A converter, 60 is a cathode counter, and 61 is a data setting circuit.

The operation of the line cathode drive circuit and deflection signal generation circuit configured as described above will be explained with reference to FIGS. 1 and 2.

First, FIG. 1 shows a basic circuit diagram of a line cathode drive circuit and a deflection signal generation circuit in one embodiment of the present invention. The pulse generation circuit 5 counts the IH clock and uses the count output.
3 generates various pulses, operates the vertical counter 52 using the output of one pulse (IH pulse) a and the vertical synchronization signal V during one horizontal scanning period, and outputs the output of the vertical counter 52 to the pulse generation circuit 53. and sent to the line cathode drive pulse generation circuit 54. The cathode counter 60 counts the number of lines using the IH pulse a generated by the pulse generating circuit 53 as a counter, and counts the number of lines that one line cathode has. The number of lines that one line cathode has can be arbitrarily set by changing the preset value of the cathode counter 60 using the data setting circuit 61 and the recent pulse b.

In the following description, it is assumed that the present embodiment is preset to count 9 lines. , the line cathode drive pulse generation circuit 54 generates a pulse C for determining the start timing of the line cathode and a pulse d for line cathode selection, and sends them to the line cathode selection circuit 55. The line cathode selection circuit 55 is composed of a simple shift register, which applies two pulses c and d to the input terminal and counter terminal of the shift register, respectively, and outputs the output of the shift register as shown in FIG. Line cathode driving pulses 1, 1, 2, . . . are generated. These outputs [I~
A line cathode drive circuit 56 amplifies the signals [2a to 27] and supplies them to the line cathode 2 as drive signals [2a to 27]. The deflection memory 57 reads waveform data for vertical and horizontal deflection using the pulse e generated by the pulse generating circuit 53, and passes the data through the D/A converter 58 to generate a vertical deflection signal as shown in FIG. ■, V' and horizontal deflection signal, h'
can be obtained.

In this example, the vertical deflection data for one line cathode is deflected in nine stages, resulting in a total of 270 lines per field and 540 lines per frame (taking into account overscan), and the TV system is similar to PALSECAM etc. This makes it possible to display images with different numbers of lines. The vertical deflection data differs depending on the deflection stage, and by storing the vertical deflection data in different areas of the deflection memory 57, it is possible to easily switch the data by simply selecting the area.

Note that since the number of lines per line cathode can be freely changed, the line cathode drive circuit of the present invention can be used even in the case of image display devices having different numbers of line cathodes.

Effects of the Invention As described above, the present invention can handle video signals with various numbers of lines by simply changing the vertical deflection data and the preset value of the counter, and can also display the world's television system % type %.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram of a line cathode drive circuit and a deflection signal generation circuit of an image display device according to an embodiment of the present invention, and FIG.
3 is an exploded perspective view showing the basic structure of the image display element, FIG. 4 is an enlarged view of the screen, and FIG.
The figure is a basic drive circuit diagram of an image display element, FIG. 6 is a pronk diagram of a conventional line cathode drive circuit and deflection signal generation circuit, and FIG.
The figure is a timing diagram of various waveforms. 2... Line cathode, 3... Beam extraction electrode, 4... Beam flow control electrode, 5...
・Focusing electrode, 6...Horizontal deflection electrode, 7...
... Vertical deflection electrode, 8 ... Screen plate, 20
...phosphor, 22 ... power supply circuit, 23
...Input terminal, 26... Line cathode drive circuit, 31a-31n... Sample hold circuit, 32a-32n... Memory, 35a-35n
...Switching circuit, 36...Switching pulse generation circuit, 37...PWM circuit, 39...Pulse generation circuit, 40...
Deflection signal generation circuit, 41...DMA controller, 42...Deflection memory, 43...D
/A converter, 50... Reference oscillator, 51...
...Horizontal counter, 52...Vertical counter,
53... Pulse generation circuit, 54... Line cathode drive pulse generation circuit, 55... Line cathode selection circuit, 56... Line cathode drive circuit, 57・・・・・・
... Deflection memory, 58 ... D/A converter, 60
...Cathode counter, 61...Data setting circuit. Agent's name Patent attorney Shigetaka Awano Haka 1 name 浬 Tobe beam drawer 11 Rin beam 1 vice TIp Denga 1 bundle 1 Yusui fp Kamo Doden! Nao S Usuka Kei Suri Ri Ri Rin Satoru v113 Figure Mi Figure Hyoman's i1 Figure 1a 2a 35゜a Mi! Verbally! L'll omitted --- Ward also l)! ! (al!!h, 5 car W-return L'fimeku

Claims (1)

[Claims] The screen surface is divided into a plurality of sections in the vertical and horizontal directions, an electron beam is generated for each section, and each electron beam is deflected in the vertical and horizontal directions for each section. A device for displaying images on a computer, including a deflection memory that stores vertical and horizontal deflection data,
The counter includes a counter that counts the number of horizontal scanning lines using a one-pulse output signal as a clock during a horizontal scanning period, and a line cathode drive pulse generation circuit that generates a pulse for driving the line cathode based on the output of the counter, An image display device characterized in that it is configured to be able to change preset values.