JPH04148255A - Address generating device - Google Patents

Abstract

PURPOSE:To improve the speed of a whole process by adding prescribed fixed bit data to a logic address signal by an adder, and outputting a physical address signal for a data access when the logic address signal of a data storing memory is outputted from an address discriminator. CONSTITUTION:An adder 7 is provided. And when it is discriminated that address data are the address of the data storing memory by the discrimination of an address discriminator 5, a deficit bit is compensated by a fixed value by the adder 7, and the physical address signal for the data access is generated and outputted. This applying process is just to add the deficit bit signal parallel, and to the physical address, no process of an arithmetic and the like is not executed. Thus, the whole process time is shortened.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention (table) Accesses memory based on a segment value given from an address generation device, especially an arithmetic device, and a logical address within the segment. The present invention relates to an address generation device that generates physical addresses for.

[Conventional technology] In recent years, automobiles have been equipped with electronic control units (hereinafter also referred to as ECUs).

) has been introduced to provide a comfortable driving environment by controlling the internal combustion engine, suspension, etc. according to driving conditions and environment.

This type of ECU uses, for example, a 16-bit one-chip microcomputer. In this microcomputer, in order to secure a memory space of 64 bytes or more, the concept of segment E is introduced, and the memory space of a 20-bit physical address can be secured with a 16-bit logical address. Therefore, at the time of execution, the segment value of the stored logical address is read from the base table and added to the logical address to calculate the physical address. In this way, the target physical address can be accessed.

"Problem to be solved by the invention M" However, since it is necessary to change the segment value every time the program module is switched and to add the logical address and the segment value, the overhead increases by the processing time. As a solution to this problem, there is a technique for minimizing the segment value changing process for each module (Japanese Unexamined Patent Publication No. 280943/1983).

However, the addition process between the logical address and the segment value is unavoidable, and the effect is not that great. It is also possible to memorize the 20-bit physical address from the beginning and access it without performing the addition. Memory capacity for storing addresses becomes a problem, and 2.
Reading a 0-bit address requires two read operations in an arithmetic unit that processes in units of 16 bits, and the processing speed is not significantly improved.

The inventor of the present invention (above) Due to the nature of single-company control in microcomputers installed in various types of equipment to control the equipment, it is necessary to secure a relatively large ROM area for storing program code data. The present invention has been completed with the aim of solving the above problems by paying attention to the fact that the RAM area of the computer may be relatively small.

[Means for solving the problem] The address generation device of the present invention, which was made to solve the above problem (as shown in Fig. 1, the logical address has fewer bits than the physical address) A device that generates a physical address signal for accessing the program code storage memory or data storage memory from a logical address signal output by an arithmetic unit according to the contents of the program code storage memory stored in the computer. A base table that outputs a segment signal according to a segment instruction signal output from the arithmetic unit and a logical address signal output from the arithmetic unit determine whether the address of the program code storage memory is the address of the data storage memory. When the logical address signal of the program code storage memory is output by the determination of the address determiner, (i
An adder adds the value of this logical address signal and the value of the segment signal to generate a physical address signal for program code access, and a logical address signal of the data storage memory is determined by the address determiner. is output, an adder adds a predetermined fixed bit signal to the logical address signal and outputs it as a physical address signal for data access.

[Operation] Since the memory area for data storage is set to a size that allows reading with a logical address having a smaller number of bits than a physical address, there is no need to differentiate by segment value when accessing. In this case, the bit signal added to the logical address to generate the physical address may have any value.

Therefore, when the address determiner determines that the address data is the address of the data storage memory, the adder supplements the missing bits with a fixed value, generates and outputs a physical address signal for data access. do. This addition process simply adds the missing bit signals in parallel, and no calculations or other processing are performed on the logic attribution. This shortens the overall processing time.

[Example] Next, a preferred example of the present invention will be described in detail based on the drawings.

FIG. 2 shows a block diagram of the hardware configuration of a chip microprocessor employed in an ECU for controlling devices such as automobiles.

The arithmetic unit outputs a 16-bit logical address signal to the determination circuit 5 in order to access the necessary address in the memory 3 and perform writing or reading according to the processing result.

Determination circuit 5 determines whether the logical address signal from the execution unit is an address of RAM 3a for data storage or an address of ROM 3b for program storage, and determines whether the logical address signal is an address of RAM 3a for data storage. ROM3b for outputting to the adder 7 and storing the program
IL logical address signal is output to the adder 9 regardless of the address.

Address determination 1 by the determination circuit 5 is performed by determining whether the table reference signal from the arithmetic unit 1 and the state of the upper bits of the logical address signal match. Example 1. f, the RAM area for storing data is [0000(H)~7F
F It is determined that it is the address of the RAM 3a for data storage, and the logical address signal is switched to the adder 7 side.In cases other than the above, the R
It is determined that it is the address of OM3b, and the logical address signal is switched to the adder 9 side. Processing of a circuit having such simple determination and switching functions is quick. Furthermore, since such a circuit is well known, a detailed explanation will be omitted.

Adder 711 is a circuit that adds a 1:4 bit signal to the upper part of the logical address signal in order to convert the 16-bit logical address signal into a 20-bit physical address signal.

The circuit configuration is extremely simple, and it is sufficient to add a 4-bit line fixed to ro(H)J to the 16-bit line. Therefore, 20 bits of I'0OOOO(H) to 07 F
A physical address signal in the range of F (H) J is generated and output.

Adder 9 adds the 16-bit logical address signal from determination circuit 5 and the 16-bit segment address signal output from base table 1 by execution unit 1, and outputs a 20-bit physical address signal. . 1
The 6-bit segment address signal is processed by the adder 9 as
The 16-bit logical address signal (
(offset signal) to output a 20-bit physical address signal.

This 20-bit physical address range is set by adjusting the segment values in the base table 1 in advance using the linker function described later, and the physical address range (roooooo ( H)～
Range other than 07FFF(H)J) (+08000(H)
~FFFFF(H)J).

The physical address signal from the adder 7 or the physical address signal from the adder 9 via the memory address register 13 is sent to the address decoder 17 via the address bus 15. The address decoder 17 selects a predetermined input/output port (
(not shown) to enable the arithmetic unit 1 to perform write or read processing to a predetermined address via the memory buffer register 19 and the data bus 2].

Although not shown in FIG. 2, the arithmetic unit 1 also executes various device controls based on the compared contents.

Here, the setting of the program area and data area within the memory 3 will be explained.

As mentioned above, RAM3a corresponding to the data area is
The physical address is ro OOO0(H) ~O7FFF(
H) J) Tags set in the range 6 corresponding to the program area
ROM3blL r08000(H) ~FFFFF
(H) It is set to J. This setting (Table 1: When creating an executable program by integrating multiple modules using software that performs linking processing, a so-called linker, after developing a program for each module.1), the size of each module, and This is done by calculating the data area of each module.The size of the data area of each module is extremely small compared to the program size, and the design conditions are such that the total is sufficiently within 32 bytes. It is set.

The linker checks whether each module of the program created by dividing the program is designed in accordance with the above design conditions regarding memory size, and whether the execution program generated by linking the modules conforms to the above design conditions. Execute link processing while making the determination. The relevant part of the processing in the linker is shown in the flowchart of FIG.

This process is executed on the computer of the program development system. First, the developed module group is stored on a predetermined storage medium. Then, the linker program is run.

After link processing starts, when processing addresses within it, all address data (represented by labels, for example) in all modules are first found (
Step 110). Next, it is determined whether the address is a data address (step 120). Even if the address represents a relative logical address by a label for program code rather than an address for data, the address is converted into a logical address of the segment corresponding to each module (step 130).

Next, it is determined whether the address data is complete (step 140).

If address data still exists, the process of step 120 is repeated. (Step 1)
50). That is, it belongs to segment roooo(H)J in area 1 of RAM3a, but this segment roo
In the oO(H)J area, as shown in FIG. 4, the data areas D1 to Dn of the modules M1 to Mn are secured in order in a last-filling manner every time the process of this step is executed.

Next, as a result of securing this data area, it is determined whether the area exceeds 32 bytes (step 60). If it exceeds (Yo), error 8 will be generated as it is an overflow.
The force is displayed on the computer display or the like (step 170), and the process ends. If there is no overflow, the process moves to step 140.

After processing of all address data is completed in this way, the process shifts to other processing at step 1''.As one of the other processing, the ROM writer writes the programs of each module M1 to Mn into the ROM 3b.This writing In processing, when writing each instruction code, the logical address for data set as described above is written in RAM.
The logical address for one segment r0000(H)J that fits in 3a is written to ROM3b, and the logical address for the program is written to each module Ml-
While determining the Mn segment, it is written into the ROM 3b as a logical address for that segment. Also RO
A table of segments corresponding to each module M1-Mn is written to the base table 11 provided in M3bfi or a separate ROM.

Through the above linker processing, as shown in Figure 4,
For RAM3a of memory 3 (each module M1
One fixed segment value roo0 common from ~Mn
Data areas D1~ that can be accessed based on 0(H)J
Dn is secured. Regarding the instruction codes in the ROM 3b (Table) Since the entire program is huge in size, it can be accessed based on segment values obtained by referring to the base table 11.

Since the structure of the first embodiment is as described above, when accessing an instruction code, after obtaining a segment from the base table 11, the adder 9 adds the logical address and the segment value. If you have obtained the physical address but want to access RAM3a, which is the data area, 1
The physical address is obtained by simply adding four fixed bits as parallel lines in the adder 7.

In this way, access to the data area does not involve address arithmetic processing. Furthermore, since the number of bits of the stored address data remains at 16 bits and does not increase, there is no burden on readout. Therefore, it can be accessed extremely quickly. Therefore, the speed of the entire process is improved, and even if the same process is performed as before, it becomes faster, or even more complex processing is possible with the same processing time. Furthermore, the overall size of the program can be as large as in the past.

In the above embodiment, the data area was set to 32 bytes, but of course the range where the segment is not changed, that is, 6
It may be less than 4 bytes. In this case, the address can be determined using only the 1 table reference signal in the determination circuit 5.

■Kawabe Effect Present Invention 1 Table When the address determiner outputs a logical address signal of the data storage memory, the adder adds predetermined fixed bit data to this logical address signal and generates a physical address signal for data access. Begour power. Therefore, no arithmetic processing is performed during physical address generation. Further 1: Since the number of bits of stored address data does not increase, there is no burden on reading. Therefore, it can be accessed extremely quickly.

As a result, the speed of the entire process is improved, and the overall processing time is shortened even if the process is the same as the conventional process. Further, even more complex processing is possible with the same processing time.

[Brief explanation of the drawing]

FIG. 1 is a basic configuration diagram conceptually illustrating the content of the present invention. FIG. 2 is a block diagram of the hardware configuration of a one-chip microprocessor according to an embodiment. FIG. 3 is a flowchart of a linker for the developed program module. represents. Figure 4 is an explanatory diagram of the contents of memory]... Execution unit 3... Memo 1 large 3a...
RAM, 3b... ROM, 5... Judgment circuit, 7...
・Adder, 9...Adder, 11...Base table, 13...Memory address register, ]5...Address bus, 17...Address decoder, ]9...Memory buffer register, 21...Data bus

Claims (1)

[Claims] From the logical address signal output by the arithmetic unit according to the contents of the program code storage memory in which the logical address is stored with a smaller number of bits than the physical address, the program code storage memory or data storage A device that generates a physical address signal for accessing a memory for use in a computer, and includes a base table that outputs a segment signal according to a segment instruction signal output from the arithmetic device, and a logical address signal output from the arithmetic device that is programmed. an address determiner that determines whether the address is a code storage memory address or a data storage memory address; and when the address determiner outputs a logical address signal for the program code storage memory,
An adder adds the value of this logical address signal and the value of the segment signal and outputs the result as a physical address signal for program code access, and a logical address signal for the data storage memory is output based on the judgment of the address determiner. An address generating device comprising: an adder that adds a predetermined fixed bit signal to the logical address signal and outputs it as a physical address signal for data access.