JPH04131949A - Memory access controller - Google Patents

Abstract

PURPOSE:To reduce the hardware quantity by providing a wait control unit and a bus cycle control unit which controls the transmission of the address signal between the internal and external address buses and also the transmission of data between the internal and external data buses respectively. CONSTITUTION:A memory access controller consists of a wait control unit 2 and a bus cycle control unit 3. A bus cycle generating circuit 31 performs the wait state insertion control based on the inputted wait control signals WC1 and WC2. At the same time, the circuit 31 activates successively the driver control signals DDC and ADC within a prescribed number of clocks and also controls an address bus driver 36 and the data bus drivers 37 and 38 to perform the control of transmission of data between an address bus 34, an external address bus 4 and between a data bus 35 and an external data bus 5 respectively. Thus it is possible to minimize the hardware dependent on the number of blocks of the unit 2 and a small scale of hardware suffices.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory access control device, and more particularly to a memory access control device for dividing a memory space into blocks and controlling access to these blocks.

[Conventional technology]

In recent years, the speed of microcomputers and the integration of memory devices have increased dramatically. With the trend toward higher integration in memory devices, the access time, which represents the time required to read and write data, is increasing in SRAM, DRAM,
There is a noticeable difference between ROM, FROM, etc., and the access time is longer for ROMs that are available at lower prices.

On the other hand, in microcomputers, the method of increasing the operating frequency of the internal clock using semiconductor speed-up technology is an effective method for increasing the speed, and the time of one clock cycle is being shortened. Along with this, the minimum time required for a bus cycle (memory access control device) when a microcomputer performs input/output with an external memory is also becoming shorter. Furthermore, the memory space capacity of microcomputers for data processing is increasing significantly.

Under these circumstances, in systems that use microcomputers with large memory spaces and large amounts of memory, high-speed ROM or PORM is used for program memory that requires high-speed program execution, and high-speed SRAM or high-speed RAM is used for program control data. DRAMs for large-capacity data that do not require relatively high speeds, ROMs for storing character fonts, and the like are used for purposes such as speeding up systems and reducing costs.

The microcomputer used in this manner is equipped with a function called wait control as one of memory access controls in order to connect and access multiple types of memory elements with different speeds. Wait control is for extending the access time by inserting a user-specified number of clocks called a wait state into the predetermined minimum bus cycle clock number when performing memory access.

In such microcomputer systems, there are two block division methods that control memory access by dividing the memory space into blocks: a fixed size method in which the block size is predetermined, and a block size method in which the block size is set to an integral multiple of the fixed size. There is a configurable variable size method.

FIG. 6 is a block diagram of an example of a conventional memory access control device that adopts a fixed size method for block division, mainly consisting of a weight control unit.

Wait control unit 2 of this memory access control device
In No. 11, the memory space is divided into eight fixed-sized blocks, starting from the lower address: block "0", block "1", block "2", etc., block "
It's called 7".

The wait control unit 2B includes an address decoder 25.
．． A weight control register 23B and a weight selector 24m are included. The path line 1 is used to input and output address signals, input/output data, various register setting data, etc. to and from a central processing unit (hereinafter referred to as CPU) (not shown).

The address decoder 25 inputs the address signal AD from the address bus, and activates the block designation signal BDO when the value of the address signal AD indicates block "0", and activates the block designation signal BDO when the value indicates block "1". Activate BDI, and similarly block designation signal B
Activate D2 to EDγ exclusively.

The wait control register 23B stores the wait control data output to the pass line and is always connected to the wait selector 2.
4. Output to.

Wait control data is a set of wait state insertion information for each block to be memory accessed,
When a user uses a memory manipulation command or the like in a program, data is stored from the CPU via a pass line.

A predetermined number of bits is assigned to each block of the wait control data, and the wait control data includes, for example, no wait state insertion, one wait state insertion,
It has the meaning of inserting a wait state twice.

The wait selector 24B inserts wait state insertion information for block "0" when the block designation signal BDO is active, wait state insertion information for block "1" when the block designation signal BD1 is active, and similarly, the wait state insertion information for blocks "2" to "2". Any of the wait state insertion information of block "7" is output to a bus cycle control section (not shown).

The bus cycle control section inserts a predetermined number of wait states according to the contents of the wait control data to perform desired memory access control.

FIG. 7 is a block diagram mainly consisting of a weight control unit of an example of a conventional memory access control device that employs a variable size method for block division.

In this weight control unit I'2c, the memory space is divided into a maximum of four blocks each consisting of an integral multiple of a fixed size, block "O", block "1", block "
2”, weight control unit (referred to as block “3”) 2
In order to detect that the value of address signal AD of the address bus is for block "0", block start address register register 'c' stores the upper 8 bits of the start address of block "0". A block size register (hereinafter referred to as BSZ) 27A that stores the upper 8 bits of the difference (offset value) obtained by subtracting the start address from the end address of block "O". An adder 28A that adds the values of BST26A and BSZ27, and a comparator 29
It has A. Then, the added value and the upper 8 bits of the address signal AD are compared by the comparator 29A, and when the value of the address signal AD is smaller than or equal to the added value, the block designation signal BDO is activated.

Similarly, in order to detect that the value of the address signal AD is for block "1", BST2
6 B, BSZ27m, and adder 28. And comparator 29! I
BST26c, BSz27c and adder 28 to detect that it is for block "2".
c and a comparator 29c, which detects that it is for block "3", a BSZ 27n, and an adder 28. and a comparator 29D,
When the value of the address signal AD is smaller than or equal to the added value, each block designation signal is activated. In addition, in accordance with this order, the block designation signals BDO-BD3 have a priority order between blocks set by a priority determination unit (not shown), and are controlled so that multiple blocks are not designated at the same time. ing.

The weight control unit 2° also includes a weight control register 23° and a weight selector 24. Contains.

The weight control register 23c stores weight control data set by a user's program, and each block has a field to which a predetermined number of bits are assigned, and has four fields for four blocks.

The wait selector 24c inserts wait state insertion information for block "0" when block designation signal BDO is active, wait state insertion information for block "l" when block designation signal BDI is active, and similarly for block "2". weight state insertion information, pro,
Wait state insertion information of "3" is output to a bus cycle control unit (not shown). The bus cycle control unit performs memory access control according to the contents of wait control data.

[Problem to be solved by the invention]

In the conventional memory access control device described above, in the fixed size method, the number of blocks and block size are fixed, so it is necessary to reduce the unit size of the block in order to adapt to small capacity and high speed memory. Since the number of blocks increases when dealing with a large memory space, (&) the wait control register that stores wait control information corresponding to each block becomes large.

(b) In the user's program, the number of command operations for setting data in the wait control register increases and becomes complicated.

(c) The number of block designation signals increases, and the circuit scale of the wait selector increases.

However, in the variable size method, the number of blocks can be suppressed to some extent, so the complexity of the program for setting data in the wait control register is not a problem, but compared to the registers required to identify the block, The disadvantage is that the hardware increases.

In addition, in these methods, in order to connect multiple types of memory elements with different access speeds, it is necessary to have a certain range in the number of wait states that can be inserted, and the difference in access speed of memory elements becomes noticeable. This increases the number of bits of wait state insertion information per block, which has the disadvantage that the wait control register for storing wait control data and its peripheral hardware increase.

An object of the present invention is to provide a memory access control device that facilitates the operation of storing settings such as wait control information and reduces the amount of hardware.

Means for Solving the Problem] A memory access control device of the present invention divides a memory space into a plurality of blocks, and stores and outputs block definition data including information on the number of divisions of these blocks and the size of each block. a block definition register; a block determination decoder that determines which block among the plurality of blocks the address specified by the address signal belongs to and sets the corresponding block designation signal to an active level; and a wait state of each of the blocks. a wait control register that stores and outputs wait control data including insertion information; a wait selector that selects and outputs the wait control data corresponding to a block for which the block designation signal is at an active level; and a wait selected by the wait selector. a bus cycle control unit that controls the transmission of address signals between the internal address bus and the external address bus and the transmission of data between the internal data bus and the external data bus according to the contents of the control data; It also has address signal transmission control between the internal address bus and the external address bus of the bus cycle control unit;
The data transmission control device 100 also controls data transmission between the internal data bus and the external data bus in accordance with the contents of the wait control data and the block designation signal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

This embodiment is roughly divided into two units: a weight control unit 2 and a bus cycle control unit 3.

The weight control unit 2 has a block definition register 21.
．． Block discrimination decoder 22. Wait control register 2
3. and a weight selector 24.

The pass line 1 is for inputting and outputting address values, input/output data, setting data of various registers, etc. with a CPU (not shown).

The block definition register 21 stores the block definition data output on the pass line 1 and always outputs it to the block discrimination decoder 22. Block definition data is a set of information indicating the number of block divisions of memory space and the size of each block.The block definition data is a set of information indicating the number of block divisions of the memory space and the size of each block.
Can be stored through. In this example, a 1 megabyte space is divided into a maximum of 5 blocks of various sizes, and the block "0" is divided from the lower address.
, block “1” block “2”, block “3”,
It is called block “4”.

The block definition register 21 has four 2-bit fields, MBO is a field that stores end address information of block "0", and MBO is a field that stores end address information of block "1". It consists of a certain MBI, MB2 which is a field F storing end address information of block "2", and KB3 which is a field storing end address information of block "3".

The block discrimination decoder 22 inputs this block definition data and the address signal AD output to the address bus 34, and when the address signal AD specifies block "0", activates the block designation signal BDO, When specifying “1”, block designation signal BDI
Activate the block designation signal BD2 to designate block "2", activate the block designation signal BD3 to designate block "3", and activate the block designation signal BD4 to designate block "4".
Activate.

The wait control register 23 stores the wait control data output to the pass line 1, and always outputs the wait control data to the wait selector 2.
Output to 4. The wait control data is a set of wait state insertion information for each block to be memory accessed, and is output to the pass line 1 by the CPU when the user uses a memory manipulation command or the like in a program. In this example, to simplify the explanation,
It is assumed that the weight control data consists of 10 bits for a total of 5 blocks, with 2 bits corresponding to 1 block. For example, when the value of each 2 bit is “00” (binary number, the same applies hereafter), the number of wait states to be inserted is '0'', '0''.
1”, the number of wait states inserted is “1”, ’10”
When the number of wait state insertions is "2", and when the number is 011, the wait state is inserted twice, and the bus cycle control unit 3 monitors the external wait control signal WCX and inserts an additional wait state while it is active.
(・Having a meaning.

The wait control register 23 has five 2-bit fields, including MWO, which is a field that stores wait state insertion information for block "0";
MWl is a field for storing wait state insertion information for block 1, and similarly consists of MW2 for block "2", MW3 for block "3", and MW4 for block "4".

The weight selector 24 receives block designation signals BDO-B.
Wait state insertion information is selected according to D4.

The bus cycle control unit 3 includes a bus cycle generation circuit 31. Address bus driver 36. Data bus driver 37.38. Address latch circuit 32, data latch circuit 33. Address bus 34. and a data bus 35.

The address latch circuit 32 takes in the address signal output to the pass line 1 and always outputs it to the address bus 34. The data latch circuit 33 takes in output data outputted to the pass line and outputs it to the data bus 35, and also takes in input data inputted to the data bus 35 from the external data bus 5 and outputs it to the pass line 1.

Next, the block definition register 21 and block discrimination decoder 22 will be explained in detail.

FIG. 2 is a circuit diagram describing the block discrimination decoder 21 at the logic element level.

A16 to A19 are 4 bits of the upper address signal (AD) of address bus l.

When this block discrimination decoder 22 is applied to a 1 megabyte memory space, block division as shown in FIG. 3 is realized.

As described above, the field MEO of the block definition register 21 has 2 bits and stores the end address information of block "0". The value of this field MBO is “0”
When it is 0n, the end address of block "0" is 64 kilobytes (hereinafter, kilobytes will be referred to as KB) from the start address (the OK position in Figure 3), and when it is "01", it is the same <128KB. When it is ``10'', it is the same <192KB position, and when it is ``11'', it is the same <256KB position.

Field MB1 stores end address information of block "1", and when the value of MBI is "00", the end address of block 1 is located 128 KB from the start address, and when "O1", the same < The position is 256KB, the same <384KF position when it is "1O", and the same <512KB position when it is "11".

Furthermore, field MB2 stores end address information of block "2", and when the value of MB2 is "00", the end address of block "2" is 256K from the start address.
It is the position of B, and when it is “01”, it is the same < 512KB
When it is "10", it is the same <768KB position, and when it is "11", it is the same position of 1 megabyte (hereinafter, megabyte is referred to as MB).

Field MB3 stores the end address information of block "3", and when the value of MB3 is "00", the end address of block "3" is 640K from the start address.
When it is '01' it is the same <768KB position, when it is '10' it is the same <896KB position, and when '11' it is the same <IMB position.

Block "4" is the remaining area, and the end address is fixed at the IMB position. The block diagram in FIG. 3 shows fields MBO, MBI, MB2. MB3 respectively, 01,0
The cases where the values are set to 1, 01, and 10 are shown.

Note that if the block definition register 21 is set so that the end address of a certain block is smaller than the end address of a block located at a lower address,
According to the logic of the block discrimination decoder 22 in FIG. 2, the lower block definition becomes valid, and the size of the higher block becomes "0".

Next, the weight selector 24 will be explained with reference to FIG.

The weight selector 24 selects transfer gates T1 to T
+6, and block designation signals BDO to BD4
Select the weight state insertion information accordingly.

When block designation signal BDO becomes active, transfer gates T'+ and Tz become conductive, and the upper bit of field MWO for wait state insertion information of block "0" in wait control register 23 becomes wait control signal WC1. , and the lower bits are transmitted as a wait control signal WC2,a to the bus cycle generation circuit 31.
can be conveyed to.

Similarly, when block designation signal BDI becomes active, the stored value of field MWI is stored, and when block designation signal BD2 becomes active, field M
When the block designation signal BD3 becomes active, the stored value of field MW3 becomes the stored value of W2, and when the block designation signal BD4 becomes active, the stored value of field MW4 becomes the wait control signal WCI, W, respectively.
It is output as C2 and transmitted to the bus cycle generation circuit 31.

The bus cycle generation circuit 31 performs wait state insertion control according to the input wait control signals WCI and WC2, and simultaneously activates the driver control signals ODC and ADC sequentially for a predetermined number of clocks. and the data bus drivers 37 and 38 to control the address bus 34 and the external address bus 4,
It also controls transmission of addresses and data between the external data bus 35 and the external data bus 5, and performs targeted memory access control.

In this embodiment, the weight control data is explained as having 2 bits per block, but the number of bits of the weight control data is not limited to this.

FIG. 5 is a block diagram showing a second embodiment of the invention.

In this embodiment, block designation signals BDO to BD
4 as wait selector 24 and bus cycle generation circuit 3
It is input to 1A.

As in the first embodiment, the wait selector 24 outputs one block of the wait state insertion information stored in the wait control register 23 to the block designation signal B.
Selected by DO-BD4, wait control signal WCI,
WC2 is output to the bus cycle generation circuit 31A. In the bus cycle generation circuit 31A, the block designation signal BDO
Based on ~BD4 and wait control signals WCI and WC2, the actual number of wait states to be inserted is generated for each block, and bus cycle control is performed.

For example, when the wait control signal WCI is at a low level and the wait control signal WC2 is at a high level, the block “0”
” is selected, the number of wait states to be inserted “
It is possible to perform wait state insertion control as shown in Table 1, such as generating the wait state insertion number "3" when the block "4" is selected.

Table 1 As described above, in this embodiment, the meaning of the wait state insertion information, that is, the number of wait state insertions can be changed for each divided block.

Therefore, even if the access time differs significantly depending on the type of memory element of the memory used in each block, there will be a significant increase in hardware, such as increasing the number of bits that specify the number of wait states to be inserted. This has the advantage that the number of wait states to be inserted can be changed flexibly without any problems.

〔Effect of the invention〕

As explained above, the present invention stores block definition data including information on the number of blocks and block size that can be set by a program, etc., and wait control data including wait state insertion information, and stores block definition data including information on the number of blocks and block size that can be set by a program etc. 7-1 according to the wait control data corresponding to the designated block, and according to the wait control data and the block designation signal, the transmission of data and address signals to the external data bus and external address bus is controlled. Assuming the type of memory element to be used, the block size can be specified in small steps to accommodate high-speed, small-capacity SRAM, etc., and the block size can be specified in small steps to accommodate the type of memory element used.
You can set multiple blocks whose size can be roughly specified to accommodate OM, etc., and use the set blocks to perform weight control according to the type of memory element used. By setting the number of divided blocks to the number of types of memory elements expected to be used, fine-grained weight control is possible, and the hardware that depends on the number of blocks in the weight control unit can be minimized. There is. Moreover, since the number of divided blocks can be set to the minimum, there is an effect that the number of command operations for setting required for each memory access control can be significantly reduced.

In addition, since the meaning of wait state insertion information can be defined for each block, even if the access time differs significantly depending on the type of memory element, each memory block can be inserted without increasing the number of bits that specify the number of wait state insertions. You can insert the optimal weight state for
Furthermore, since the block discrimination decoder is a decoder that can be realized with logic gate elements although the size of the number of blocks is variable, it has the advantage that it can be constructed with small-scale hardware.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the present invention;
1 is a circuit diagram showing a specific example of the block discrimination circuit of the embodiment shown in FIG. 1, FIG. 3 is a block division diagram for explaining the operation of the embodiment shown in FIG. 1, and FIG. is a circuit diagram showing a specific example of the weight selector of the embodiment shown in FIG. 1, FIG. 5 is a block diagram showing a second embodiment of the present invention,
FIGS. 6 and 7 are block diagrams showing first and second examples of conventional memory access control devices, respectively. 1...Pass line, 2,2A~2°...
・Wait control unit), 3.3A...Bus cycle control unit, 4...External address bus, 5...External data bus, 21...Block Definition register, 22...Block discrimination decoder, 23.23B, 23C...Wait control register, 24.24B, 24G...Wait selector, 25...Address decoder , 26A~
26. ...Block start address register, 2
7A to 27D...Block size register, 2
8A-28D...Adder, 29A-29.・・・
... Comparator, 31.31A ... Bus cycle generation circuit, 32 ... Address latch circuit, 33
...Data latch circuit, 34...Address bus, 35...Data bus, 36...
...Address bus driver, 37°38...Data bus driver, 100...Memory L'r+
~T1゜・・・・・・Transfer gate. Agent Patent Attorney Shinto Uchihara／HeT／θ L υ SFA γ゛−← Figure 4

Claims (1)

[Claims] 1. A block definition register that divides a memory space into a plurality of blocks and stores and outputs block definition data including information on the number of blocks to be divided and the size of each block, and a block definition register that specifies an address signal. a block discrimination decoder which discriminates which block of the plurality of blocks the address belongs to and sets a corresponding block designation signal to an active level; and wait control data including wait state insertion information for each block. A wait control register to output, a wait selector to select and output the wait control data corresponding to the block for which the block designation signal is at the active level, and an internal address according to the content of the wait control data selected by the wait selector. A memory access control device comprising a bus cycle control unit that controls transmission of address signals between a bus and an external address bus, and controls transmission of data between an internal data bus and an external data bus. . 2. The transmission control of address signals between the internal address bus and external address bus of the bus cycle control unit and the data transmission control between the internal data bus and external data bus are controlled based on the contents of wait control data. 2. The memory access control device according to claim 1, wherein the memory access control device performs the access control in accordance with the contents of the block designation signal.