JPH04147652A - Package for semiconductor device - Google Patents
Package for semiconductor deviceInfo
- Publication number
- JPH04147652A JPH04147652A JP27183990A JP27183990A JPH04147652A JP H04147652 A JPH04147652 A JP H04147652A JP 27183990 A JP27183990 A JP 27183990A JP 27183990 A JP27183990 A JP 27183990A JP H04147652 A JPH04147652 A JP H04147652A
- Authority
- JP
- Japan
- Prior art keywords
- resin layer
- conductive resin
- semiconductor device
- package
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 229920005989 resin Polymers 0.000 claims abstract description 31
- 239000011347 resin Substances 0.000 claims abstract description 31
- 239000010410 layer Substances 0.000 claims abstract description 21
- 239000011241 protective layer Substances 0.000 claims abstract description 8
- 239000004020 conductor Substances 0.000 claims abstract description 7
- 238000000465 moulding Methods 0.000 abstract description 4
- 239000004593 Epoxy Substances 0.000 abstract description 3
- 229920001296 polysiloxane Polymers 0.000 abstract description 2
- 238000007650 screen-printing Methods 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 5
- 229920000647 polyepoxide Polymers 0.000 description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 3
- 229910052799 carbon Inorganic materials 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置用パッケージのモールド樹脂層の
構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of a mold resin layer of a package for a semiconductor device.
従来、この種の半導体装置用パッケージは、第２図に示
すように半導体素子３とその外部引出し導体２の一部を
モールド樹脂１（エポキシ系樹脂＋カーボン）で包囲し
てパッケージングされる。Conventionally, this type of semiconductor device package is packaged by surrounding a semiconductor element 3 and a part of its external lead conductor 2 with a molding resin 1 (epoxy resin + carbon) as shown in FIG.
通常の半導体装置は取り扱いやすく、また機械的保護の
ために絶縁物であるモールド樹脂１のみで半導体素子３
を覆っているものであった。Ordinary semiconductor devices are easy to handle, and for mechanical protection, the semiconductor elements 3 are only made of mold resin 1, which is an insulator.
It was something that covered.
ＩＣ，ＬＳＩ等の半導体装１は各種の家庭電化製品、産
業用機器の分野へ導入されている。しかし近年電子機器
の電磁妨害規制が強まる傾向にあることから半導体装置
においても外部からの電磁雑音に強い製品が要求されて
きている。しかし、上述した従来の半導体装置は、モー
ルド樹脂（エポキシ系樹脂＋カーボン）のみで包囲して
いるため、外部からの電磁雑音により誤動作するという
欠点があった。Semiconductor devices 1 such as ICs and LSIs have been introduced into the fields of various home appliances and industrial equipment. However, in recent years, as electromagnetic interference regulations for electronic devices have become stricter, there has been a demand for semiconductor devices that are resistant to external electromagnetic noise. However, since the conventional semiconductor device described above is surrounded only by molding resin (epoxy resin + carbon), it has the disadvantage that it malfunctions due to external electromagnetic noise.
本発明は、半導体素子とその外部引出し導体の一部をモ
ールド樹脂で包囲する半導体装置用パッケージにおいて
、半導体装置パッケージの表面を導電性樹脂層と保護層
（エポキシ系及びシリコーン系樹脂）で覆ったことを特
徴とする。これにより機器の外部からの電磁雑音に対し
て強くなり１頼性を向上させることができる。The present invention provides a semiconductor device package in which a semiconductor element and a part of its external conductor are surrounded by a molded resin, in which the surface of the semiconductor device package is covered with a conductive resin layer and a protective layer (epoxy-based and silicone-based resin). It is characterized by As a result, the device becomes strong against electromagnetic noise from outside, and reliability can be improved.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の断面図である。モールド樹
脂１（エポキシ系樹脂子カーボン）で包すした半導体装
置パッケージにおいて、まずモーノド樹脂１の表面に導
電性樹脂層４としてＣｕペーストを塗付する。第１図を
例としてみると、上口だけの片面あるいは上面、下面の
両面にスクリーン印刷して塗付するものとする。また導
電性樹脂層４は外部引出し導体２に接触しないように！
（＝する。導電性樹脂層４の厚さは、５０〜５０Ｃμｍ
程度で形成するものとする０次に導電性樹１層４を保護
する目的で導電性樹脂層４の表面を介護面５で覆う。保
護層５はエポキシ系あるいはシリコーン系樹脂により厚
さ５０〜７０μｍ程度て形成するものとする。FIG. 1 is a sectional view of an embodiment of the present invention. In a semiconductor device package wrapped in mold resin 1 (epoxy resin child carbon), Cu paste is first applied to the surface of mold resin 1 as conductive resin layer 4 . Taking FIG. 1 as an example, it is assumed that the coating is applied by screen printing on one side of the upper opening only or on both the upper and lower surfaces. Also, make sure that the conductive resin layer 4 does not come into contact with the external lead conductor 2!
(= Yes. The thickness of the conductive resin layer 4 is 50 to 50 Cμm.
The surface of the conductive resin layer 4 is covered with a care surface 5 for the purpose of protecting the zero-order conductive resin layer 4, which is formed at a certain level. The protective layer 5 is made of epoxy or silicone resin and has a thickness of about 50 to 70 μm.
このように半導体装置用パッケージを導電性樹脂層４
（Ｃｕペースト）で覆ったことにより電磁遮蔽層となり
外部からの電磁雑音は遮蔽される。またより効果を増す
ために導電性樹脂層４をＧＮＤとなる外部引出し導体に
接触させてもよい。In this way, a package for a semiconductor device is formed using a conductive resin layer 4.
By covering with (Cu paste), it becomes an electromagnetic shielding layer and shields electromagnetic noise from the outside. Furthermore, in order to further enhance the effect, the conductive resin layer 4 may be brought into contact with an external lead conductor serving as GND.
以上説明したように本発明は、半導体装置用パッケージ
の表面を導電性樹脂層、保護層で覆うことにより次のよ
うな効果がある。（ａ）半導体装置パッケージ自身が電
磁遮蔽効果を持つので、遮蔽効果を有する配線基板に搭
載して筐体（ケース）に収納する際、遮蔽板を別に用い
る必要がなく、筺体（ケース）自身を小さくできる。（
ｂ）配線基板が遮蔽板の役目をはなすので、部品数を減
らせ軽量、低コストが期待できる。（Ｃ）電磁雑音の多
い場所での使用に対して従来品より信頼性が高くなる。As explained above, the present invention provides the following effects by covering the surface of a semiconductor device package with a conductive resin layer and a protective layer. (a) Since the semiconductor device package itself has an electromagnetic shielding effect, when it is mounted on a wiring board that has a shielding effect and is housed in a case, there is no need to use a separate shielding plate, and the case itself does not need to be used. Can be made smaller. (
b) Since the wiring board plays the role of a shielding plate, the number of parts can be reduced and light weight and low cost can be expected. (C) Higher reliability than conventional products when used in places with a lot of electromagnetic noise.
第１図は本発明の一実施例の断面図、第２図は従来の半
導体装置用パッケージの断面図、第３図は従来の半導体
装置用パッケージの斜視図である。
１・・・モールド樹脂層、２・・・外部引出し導体、３
・・・半導体素子、４・・・導電性樹脂層、５・・・保
護層。FIG. 1 is a sectional view of an embodiment of the present invention, FIG. 2 is a sectional view of a conventional package for a semiconductor device, and FIG. 3 is a perspective view of a conventional package for a semiconductor device. DESCRIPTION OF SYMBOLS 1...Mold resin layer, 2...External drawer conductor, 3
... Semiconductor element, 4 ... Conductive resin layer, 5 ... Protective layer.
Claims (1)
脂で包囲する半導体装置用パッケージにおいて、前記モ
ールド樹脂の表面を導電性樹脂層及び保護層の２層で覆
ったことを特徴とする半導体装置用パッケージ。A package for a semiconductor device in which a semiconductor element and a part of its external lead-out conductor are surrounded by a molded resin, characterized in that the surface of the molded resin is covered with two layers: a conductive resin layer and a protective layer. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27183990A JPH04147652A (en) | 1990-10-09 | 1990-10-09 | Package for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27183990A JPH04147652A (en) | 1990-10-09 | 1990-10-09 | Package for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04147652A true JPH04147652A (en) | 1992-05-21 |
Family
ID=17505587
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27183990A Pending JPH04147652A (en) | 1990-10-09 | 1990-10-09 | Package for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04147652A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5355016A (en) * | 1993-05-03 | 1994-10-11 | Motorola, Inc. | Shielded EPROM package |
| FR2774810A1 (en) * | 1998-02-10 | 1999-08-13 | St Microelectronics Sa | Screened integrated circuit packaging and method for the fabrication |
| US6365960B1 (en) * | 2000-06-19 | 2002-04-02 | Intel Corporation | Integrated circuit package with EMI shield |
| US6479886B1 (en) * | 2000-06-19 | 2002-11-12 | Intel Corporation | Integrated circuit package with EMI shield |
| US8884424B2 (en) | 2010-01-13 | 2014-11-11 | Advanced Semiconductor Engineering, Inc. | Semiconductor package with single sided substrate design and manufacturing methods thereof |
| US9349611B2 (en) | 2010-03-22 | 2016-05-24 | Advanced Semiconductor Engineering, Inc. | Stackable semiconductor package and manufacturing method thereof |
| US9406658B2 (en) | 2010-12-17 | 2016-08-02 | Advanced Semiconductor Engineering, Inc. | Embedded component device and manufacturing methods thereof |
-
1990
- 1990-10-09 JP JP27183990A patent/JPH04147652A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5355016A (en) * | 1993-05-03 | 1994-10-11 | Motorola, Inc. | Shielded EPROM package |
| FR2774810A1 (en) * | 1998-02-10 | 1999-08-13 | St Microelectronics Sa | Screened integrated circuit packaging and method for the fabrication |
| US6312975B1 (en) | 1998-02-10 | 2001-11-06 | Stmicroelectronics S.A. | Semiconductor package and method of manufacturing the same |
| US6365960B1 (en) * | 2000-06-19 | 2002-04-02 | Intel Corporation | Integrated circuit package with EMI shield |
| US6479886B1 (en) * | 2000-06-19 | 2002-11-12 | Intel Corporation | Integrated circuit package with EMI shield |
| US8884424B2 (en) | 2010-01-13 | 2014-11-11 | Advanced Semiconductor Engineering, Inc. | Semiconductor package with single sided substrate design and manufacturing methods thereof |
| US9196597B2 (en) | 2010-01-13 | 2015-11-24 | Advanced Semiconductor Engineering, Inc. | Semiconductor package with single sided substrate design and manufacturing methods thereof |
| US9349611B2 (en) | 2010-03-22 | 2016-05-24 | Advanced Semiconductor Engineering, Inc. | Stackable semiconductor package and manufacturing method thereof |
| US9406658B2 (en) | 2010-12-17 | 2016-08-02 | Advanced Semiconductor Engineering, Inc. | Embedded component device and manufacturing methods thereof |
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