JPH04147497A - Electrically erasable programmable memory - Google Patents

Abstract

PURPOSE:To minimize the power consumed in the write and erasure operation by adopting the configuration such that a frequency of a clock signal fed to a boosting circuit is made lower when a high power supply voltage rises and is settled. CONSTITUTION:The above memory is provided with a boosting circuit 15 boosting the output signal of a changeover circuit to generate a high voltage while a high voltage control section is at an active level, and after the high voltage Vpp is settled, the frequency of the clock signal driving the boosting circuit 15 is made lower. In this case, since a current flowing to the boosting circuit 15 is proportional to the frequency of the clock signal, a large current flows thereto only at the rising of the high voltage Vpp and after the rising of the current is finished and settled, the current consumption is decreased. Furthermore, in comparison with the entire time required for write, the time required for the rising of the high voltage Vpp is very small. Thus, the power consumption is reduced to an irreducible minimum.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an electrically erasable programmable memory, and more particularly to an electrically erasable programmable memory used in devices requiring low power consumption.

[Conventional technology]

Conventionally, this type of electrically erasable programmable memory has had a configuration as shown in FIG. 3, for example.

EEPROM cell array 1 is electrically written,
A plurality of erasable memory cells are arranged, and these memory cells are selected by an address latch circuit 21, a row selection circuit 3, and a column selection circuit 4.

The write/erase circuit 6 sends write data D input via the write data latch circuit 5 to a memory cell selected by receiving a high voltage vPP during write operation and erase.
Write and erase Tw.

The read circuit 7 and the output circuit 8 output read data DTR from the selected memory cell during a read operation.

The oscillator 9 generates a clock signal CI1 with a predetermined frequency and supplies it to the counter 11 and the booster circuit 15.

The counter 11 initializes the count value by the reset signal R3T, starts counting the clock signal CK, and outputs the end signal END when the count value reaches a preset count value.

The control circuit 14 outputs a reset signal R3T when the write signal WE and the erase signal ER are input, and sets the high voltage control signal HVC to an active level, and when the end signal END is input, the high voltage control signal HVC is deactivated. level.

The booster circuit 15 boosts the clock signal CK to generate a high voltage Vpp of about 20V while the high voltage control signal HVC is at an active level.

Note that the connection of each terminal during writing and erasing to a selected memory cell of the EEPROM cell array 1 is as follows.
As shown in Figures (a) and (b).

Further, as shown in FIG. 5, the booster circuit 15 is composed of a capacitor C, an l-transistor Q, an inverter IV, and the like.

Next, the operation of this circuit will be explained using writing as an example.

FIG. 6 is a waveform diagram of various signals for explaining the write operation of this circuit.

First, a predetermined memory cell of the EEPROM cell array 1 is selected using the address signal AD. When the write signal WE is input, the control circuit 14 outputs the reset signal R3T and sets the high voltage control signal HVC to the active level. The booster circuit 15 is activated by this high voltage control signal HVC, and the high voltage VP is activated.
begins to generate P. At the same time, the reset signal R3T clears the counter 11 values from 1 to 1, and the high voltage Vpp
Start counting the amount of time that the voltage is applied.

The high voltage VPP generated by the booster circuit 15 is applied to the drain of the selected memory cell through the write/erase circuit 6 when writing is required depending on the contents of the write data latch circuit 5. The time during which the high voltage Vpp is applied is usually several milliseconds.

Note that the erase operation is performed by applying a high voltage VpP to the gate of the memory cell.
is applied and the source is grounded, but the operation is similar to the write operation.

[Problem to be solved by the invention]

The conventional electrically erasable programmable memory described above has a configuration in which the clock signal CK is boosted by a booster circuit 15 to generate a high voltage VPP.
Since the boosting ability of 5 is proportional to the frequency of the clock signal CKI that drives it, even when high boosting ability is required during the period when high voltage VPP rises, the boosting ability after high voltage VPP rises and stabilizes is low. Boost circuit 15 at the same frequency even when
The disadvantage is that it consumes more power than necessary.

An object of the present invention is to provide an electrically erasable programmable memory that can minimize power consumption.

[Means to solve the problem]

The present invention provides an electrically erasable programmable memory comprising:
a memory cell array in which a plurality of electrically programmable and erasable memory cells are arranged; a selection circuit that selects a predetermined memory cell of the memory cell array according to an address signal; an oscillator that generates a first clock signal of a predetermined frequency; and an oscillator that divides the first clock signal and generates a second clock signal. a frequency divider that generates a clock signal; and a first counter that initializes a count value with a reset signal, starts counting the first clock signal, and outputs a termination signal when a preset first count value is reached. a second counter that initializes a count value by the reset signal, starts counting the first clock signal, and outputs a set signal when a second count value smaller than the first count value is reached; a switching circuit that outputs the first clock signal when a reset signal is input and outputs the second clock signal when the set signal is input; and a switching circuit that outputs the reset signal during a write operation and an erase operation. a control circuit that sets the high voltage control signal to an active level and sets the high voltage control signal to an inactive level when the termination signal is input; and an output signal of the switching circuit during a period when the high voltage control signal is at the active level; and a booster circuit that boosts the voltage to generate the high voltage.

[Effect]

The present invention lowers the frequency of the clock signal that drives the booster circuit (15) after the potential of the high voltage (Vpp) has stabilized,
The power consumed by the booster circuit (15) is minimized.

In other words, in principle, EEPROM cells do not require current even if they require a high voltage for writing and erasing, so the load on the booster circuit (15) is large when the high voltage (Vpp) rises.
Only during lily season. Therefore, only at the rise of the high voltage (Vpp) that requires a high boosting ability in the booster circuit (15), the frequency of the clock signal is increased to increase the boosting ability. The frequency may be reduced to just enough to maintain the high voltage (vpp) already available.

On the other hand, since the current flowing through the booster circuit (15) is proportional to the frequency of the clock signal, according to the present invention, a large current flows only when the high voltage (Vpp) rises, and after it has finished rising and stabilized. The current consumption will be smaller. Since the time required for the high voltage (Vpp) to rise is very small compared to the entire time required for writing, the power consumed in the writing operation can be reduced.

Embodiment] Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

This embodiment differs from the conventional electrically erasable programmable full memory shown in FIG.
The frequency divider 10 outputs the clock signal CK2 and the count value is initialized by the reset signal R3T to start counting the clock signal CK1, and the counter 11 outputs the end signal E.
A high voltage smaller than the count value that generates ND ■ A count 12 that outputs a set signal ST when the count value indicating the period during which PP rises and settles, a logic circuit 2] and a flip-flop 22 are provided, and a reset signal R3T or input is provided. A switching circuit 1 outputs a clock signal CK when the set signal ST is input, and outputs a clock signal CK2 when the set signal ST is input.
3 is provided, and a high frequency clock signal CKs is supplied to the booster circuit 15 when the high voltage PP rises, and a low frequency clock signal CK2 is supplied to the booster circuit 15 after the high voltage Vpp has stabilized.

Next, the operation of this embodiment will be explained using a write operation as an example.

FIG. 2 is a waveform diagram of signals of various parts for explaining the operation of this embodiment.

First, the time. When the WE to write is input manually, the control circuit 14 outputs the reset signal RST and the high voltage control signal HVC becomes active level (high level), the booster circuit 15 starts boosting operation, and the counter 11,
12 is reset and starts counting the clock signal CK. The switching circuit 13 also receives a reset signal R3.
Since T is input, the output signal SW of the flip-flop 22 becomes low level, and the high frequency clock signal CI
1 passes through the logic circuit 21 and is supplied to the booster circuit 15.

At time t1, the high voltage VPP rises to almost a static level, and then at time t2, the counter 12 outputs the set signal ST, and the output signal S of the flip-flop 22
W becomes high level, and the divided low frequency clock signal CK2 passes through the logic circuit 21 and is supplied to the booster circuit 15.

At this time, the clock signal CK supplied to the booster circuit 15
Since the frequency of is lowered, the current flowing through the booster circuit 15 becomes smaller.

When the time required for writing has elapsed in this state, time t9
Then, the count value of the counter 11 becomes the set value, the end signal END is outputted, the high voltage control signal HVC becomes low level, and the boosting operation and writing operation are completed.

In this way, the current consumption during write operation (same as during erase) can be suppressed to the necessary minimum.

〔Effect of the invention〕

As explained above, the present invention reduces the power consumed in write and erase operations to the minimum necessary level by reducing the frequency of the clock signal supplied to the booster circuit after the high voltage rises and stabilizes. It has the effect of reducing

[BRIEF DESCRIPTION OF THE DRAWINGS] FIGS. 1 and 2 are block diagrams showing one embodiment of the present invention, waveform diagrams of signals of various parts to explain the operation of this embodiment, and FIGS. 3 and 4, respectively. . FIG. 5 is a block diagram showing an example of a conventional electrically erasable programmable memory;
FROM cell area memory cell, circuit diagram of booster circuit,
FIG. 6 is a waveform diagram of various signals for explaining the operation of the electrically erasable programmable memory shown in FIG. 3. 1...EEPROM, 2...Address latch circuit,
3...4 row selection circuit, 4...column selection circuit, 5 write data latch circuit, 6...write/erase circuit, 7...
Readout circuit, 8... Output circuit, 9... Oscillator, 10
... Frequency divider 11.12... Counter, 13... Switching circuit, 14 Control circuit, 15... Boosting circuit, 21...
...Logic circuit, 22...Flip 70 tubes. , ,” Figure 6

Claims (1)

[Claims] a memory cell array in which a plurality of electrically programmable and erasable memory cells are arranged; a selection circuit that selects a predetermined memory cell of the memory cell array according to an address signal; a write/erase circuit that writes and erases data to and from memory cells; an oscillator that generates a first clock signal of a predetermined frequency; and a second clock signal that divides the first clock signal. a first counter that initializes a count value by a reset signal, starts counting the first clock signal, and outputs a termination signal when a preset first count value is reached; a second counter that initializes a count value by the reset signal, starts counting the first clock signal, and outputs a set signal when a second count value smaller than the first count value is reached, and the reset signal; a switching circuit that outputs the first clock signal when the set signal is input, and outputs the second clock signal when the set signal is input;
a control circuit that outputs the reset signal and sets the high voltage control signal to an active level during a write operation and during erasing, and sets the high voltage control signal to an inactive level when the end signal is input; and the high voltage control circuit. an electrically erasable programmable memory, comprising a booster circuit that boosts the output signal of the switching circuit to generate the high voltage while the signal is at an active level.