JPH023192A - Non-volatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To speed up a reading access by boosting the output voltage of a raw decoder to be power source voltage at the time of reading operation. CONSTITUTION:A capacitor C0 is inserted between a high voltage pulse VPP and a word line WL. In the reading operation at the time of selection, lines N1 and N2 go to 'H' by the outputs of predecoders G1 and G2 and a raw decoder Z and the potential of the line N2 goes to a value, whose threshold is lower than a transistor T. Next, when the high voltage pulse VPP goes to 'H' while delaying to the predecoders G1 and G2 and and decoder Z, the potential of the line N is boosted by the capacitor C0 with the impression of the high voltage pulse VPP. Accordingly, in the reading operation, the signal of a word line WL can be raised and the reading access can be executed at high speed. Since charge ability is improved, the gate width of a transistor T can be reduced and high integration can be executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a nonvolatile semiconductor memory device that boosts a signal voltage to a memory cell array.

[Conventional technology]

The row decoder in the electrically reprogrammable and erasable read-only memory device (hereinafter referred to as EEPROM) K raises only the word line (hereinafter referred to as WL line) corresponding to the address input from the outside to rHJ (when selected ), it has the function of making other WL lines rLJ (when not selected). Normally, a row decoder is placed adjacent to a memory cell array, so for example, two decoders are used to decode part of the address input, and their output lines are placed in parallel to the memory cell array to reduce the number of elements and occupy space. We are trying to reduce this. Furthermore, since a plurality of memory cell arrays are connected to the WL line, its stray capacitance increases. Therefore, in order to achieve high integration and high-speed access, it is necessary to reduce the number of elements and the size of the elements to speed up the rise of the WL line.

FIG. 3 is a circuit diagram of a conventional EEFROM WL line selection circuit (row decoder). In the figure, M is a 1-byte memory cell array when 1 byte is 2 bits.
WL is a WL line that propagates word signals, Gl and G2 are pre-row decoders, TI and T2 are WL line drivers that charge and discharge signals on the WL line, T3 is a high voltage cut transistor,
T4. T5 is a transistor, and C1 is a capacitor.

Here, transistor T4. T5 and capacitor C1 constitute a high voltage changeover switch. In addition, φ is a clock source, vpp is a high voltage pulse, Vce is a power supply voltage, CGL
.

BL, , BL are signal lines.

Next 1c, the operation of the WL line selection circuit is explained at 7 in Figures 4 and 5.
0-Explain according to the chart. FIG. 4 shows the read operation at the time of selection, and (&) to (f) in the same figure show the lines Nl, N2 (WL) N3°N4 . N5
．． The waveform of high voltage pulse VPp/clock source φ is shown. In addition, FIG. 5 shows the write operation at the time of selection, and (a) to (g) of the same figure show the line N in FIG.
The waveforms of 1, N2 (WL), N3, N4, N5, high voltage pulse vpp, and clock source φ are shown.

Now, as described above, the WL line selection circuit performs two operations: when selected and when not selected. When selected, the Brillou decoder Gl is used for the WL line in both read and write operations.
, G2, line N3 = rHJ, N4 = rLJ (Fig. 4(e), (d), Fig. 5(e), (d)
)) , the output of the z decoder becomes rHJ. Therefore, since the transistor T1 is turned on and the transistor T2 is turned off, both the lines Nl and N2 are charged with rHJK (
Figure 4 (aJ, (bLFigure 5 (a), (b))
o In case of non-selection, line N3= rLJ,
Since N4=rHJ or the output of the two decoders becomes rLJ, even if the lines Nl and N2 become rHJ at the time of selection, the transistor T1 is discharged through T2 and becomes rLJ.

By the way, since EEPROM requires a high voltage pulse for writing, the WL line must be set at a high voltage of about 15 to 20V. Therefore, the output r on line N2
A high voltage changeover switch (transistors T4, T5, capacitor CI) is provided to boost the voltage of HJ.

Its operation is based on boosting voltage through capacitive coupling as follows. First, a high voltage pulse Vpp (1
5 to 20 V) and oscillate one clock source φ at a frequency of 5 MHz (Fig. 5 (f), (g)).
. At this time, if the line N2 is "H" (when selected), the transistor T4 is turned off and the voltage of the line N5 is Vec-V
4 (where v4 is the threshold value of transistor T4). Furthermore, since the line N2 is at "H" (power supply voltage Wee), the transistor T5 is off. Now, if we focus on the charging of the line N5 during the period when the clock source φ is rLJ, if the stray capacitance of the line N5 is CF, then (CI + CF
) (Mcc-V4) is accumulated.

After that, when the clock source φ becomes rHJ, due to charge conservation,
) ”/(C1+CF)Mcc voltage is boosted.

At this time, the potential of the line N5 is Vec+V5 (however, v5
When the voltage exceeds the threshold value of the transistor T5), the transistor T5 is turned on, and the line N2 becomes higher than the power supply voltage Vee. In this way, during the period when the next clock source φ is rLJ, the potential of the line N5 becomes Vce V4 or higher and is further boosted. Normally, the voltage on the line N2 for a period of 100 μs or less is boosted to about the high voltage pulse VpP (15 to 20 V). On the other hand, when it is not selected, the line N2 is grounded as described above, so the transistor T4 is turned off, so no boosting is performed and the line N2 remains at rLJ.

Further, as described above, the EEPROM includes transistors T4. Since T5 must be turned off by the gate voltage Ov when a drain voltage of 15 to 20 V is applied, the width of the gate length is increased to ensure breakdown voltage.

However, in order to speed up read access,
The charging capacity must be improved by narrowing the gate widths of the transistors TI and T2.

Therefore, the gate widths of the transistors TI and T2 are made narrower, and in order to ensure the withstand voltage, the transistor T3 is used to which the power supply voltage Vce is applied to the gate to improve the withstand voltage.

[Problem to be solved by the invention]

However, the conventional EEFROM has the disadvantage that it is not possible to boost the voltage on the WL line during a read operation, and therefore, the speed of read access cannot be increased. Furthermore, in order to improve the withstand voltage, it is necessary to increase the gate width of the transistor 3, which has the disadvantage that it is not suitable for high integration.

The present invention has been made to solve the above-mentioned drawbacks.
An object of the present invention is to obtain a nonvolatile semiconductor memory device that can speed up read access.

[Means to solve the problem]

The nonvolatile semiconductor memory device according to the present invention includes boosting means for boosting the output voltage of the row decoder to a level higher than the power supply voltage when the output of the row decoder is selected.

[Effect]

The booster boosts the output voltage of the row decoder during a read operation.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows an EEPROM K showing an embodiment of the present invention.
FIG. 2 is a circuit diagram of an LW line selection circuit (row decoder) in FIG. In the figure, the same parts as in FIG. 1 are given the same reference numerals. Co is a capacitor serving as boosting means provided between the high voltage pulse VPP and the WL line. In addition, FIG. 2 is a flowchart of the read operation at the time of selection, and the lines (a) to (a) in FIG.
L), N3. N4. N5. The waveforms of the high voltage pulse Vpp and the clock source φ are shown.

Now, the read operation at the time of selection is similar to that shown in FIG. (threshold value) (Fig. 2 (a), (b)). Next, high voltage pulse vpp
When becomes rHJ later than the timing (time 1+) when becomes rHJ of pre-decoder Gl, G2 and 2 decoder, (
At time t2), by applying a voltage of 15 to 20 V of the high voltage pulse VPP, the potential of the line N2 becomes more than Vee-V3 by Co/(Co +CE)Vpp (however, CE is the potential of the line N2).
2 stray capacitance) is boosted (Figure 2 (b))
. Note that the clock source φ at this time is always rLJ.

In addition, the 1-read operation when selected is performed by the clock source φ
oscillates, resulting in an operation similar to that shown in FIG.

In this way, in this embodiment, by providing the capacitor Co, the signal on the WL line can be boosted even in a read operation, so that read access can be speeded up. Further, since the charging capacity is improved by using the capacitor Co, the gate width of the transistor T3 can be reduced, and high integration can be achieved.

Note that although the capacitor Co is usually formed alongside the gate capacitance of the transistor T4, it may be formed separately from the transistor T4.

〔Effect of the invention〕

As described above, the present invention includes boosting means for boosting the output voltage to a level higher than the power supply voltage when the output of the row decoder is selected, so that read access can be speeded up. Further, this boosting means allows the gate width of the transistor to be reduced, and higher integration can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an LW line selection circuit in an EgPROM showing an embodiment of the present invention, FIG. 2 is a time chart of each part of FIG. 1 in a read operation, FIG. 3 is a conventional circuit diagram, and FIG. The figure is a time chart of each part of FIG. 3 in a read operation, and FIG. 5 is a time chart of each part of FIG. 3 in a write operation. Co... Capacitor, vppIllllll/high voltage pulse, φ...20 power source, T3. T4. T5・
...Transistor, C1...Capacitor.

Claims (1)

[Claims] Writing information arranged in an array in the row and column directions,
A semiconductor memory device comprising an erasable memory cell array, column decoder means for decoding an externally input address signal and making a selection in the column direction, and row decoder means for decoding the address signal and making a selection in the row direction. . A nonvolatile semiconductor memory device, comprising boosting means for boosting the output voltage to a power supply voltage or higher when the output of the row decoder is selected.