JP3101296B2 - Semiconductor storage device - Google Patents

Description

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device using a ferroelectric capacitor.

(Prior Art) In recent years, technology relating to electrically writable and erasable nonvolatile memories has been advanced, and various memory elements have been developed. One of them is a ferroelectric memory.

A ferroelectric memory stores information according to the direction of polarization of a ferroelectric capacitor using a ferroelectric as a dielectric. For example, Japanese Patent Laid-Open No. 63-201998 discloses details. The basic operation will be briefly described. The ferroelectric has a polarization-voltage characteristic having hysteresis as shown in FIG. Therefore, once polarized, the polarization remains even when the applied voltage is removed (remanent polarization). When a voltage is applied such that an electric field (coercive electric field) of a fixed value or more is applied to the ferroelectric in a direction opposite to the polarization direction, the polarization direction of the ferroelectric is reversed. When a voltage in the same direction as the polarization direction is applied to this ferroelectric, only a charge corresponding to the capacitance flows in, as in a normal dielectric. Inversion occurs, and much more charge flows in than in the same direction. Therefore, the direction of polarization of the ferroelectric can be determined by detecting the magnitude of the charge inflow by, for example, the amount of voltage drop. That is, information can be stored and read by associating one of the polarization directions with “1” and the other with “0”. As described above, this information remains as remanent polarization even when the applied voltage to the ferroelectric substance is lost, and thus it is understood that the memory is a nonvolatile memory. Such a ferroelectric memory has several tens of nanoseconds for both writing and reading.
It is a high speed memory device as shown below and is expected to be developed in the future.

(Problem to be Solved by the Invention) When information is stored in the polarization direction of the ferroelectric substance, for example, if the polarization direction in the “1” state is the direction of the voltage applied at the time of reading, the “1” information is stored. In this case, polarization inversion does not occur, but when "0" information is stored, polarization inversion is accompanied. Therefore, regardless of the stored information after the read operation, the polarization direction of the ferroelectric is oriented in the same direction. Therefore, when the “0” information is stored, it is necessary to return to the original polarization direction. . The same applies to the opposite state. As described above, since the above-described memory is basically a destructive readout, the frequency of polarization reversal is large.

It is known that the polarization characteristics of a ferroelectric material deteriorate as the number of polarization inversions increases (wear-out phenomenon). It is generally said that the degradation becomes significant after 10 ¹² or more polarization reversals. Therefore, this is one of the major factors that determine the lifetime when used as an element, and it is necessary to reduce the number of polarization inversions as much as possible.

Japanese Patent Application Laid-Open No. 64-66899 discloses a technique of storing information in a ferroelectric memory when a non-volatile memory is required by separately attaching a ferroelectric memory as described above to a conventional semiconductor memory. Have been. According to this technique, a minimum frequency of polarization inversion is sufficient, so that the service life can be extended without concern for the wear-out phenomenon of the ferroelectric. However, this is no different from the case where a conventional backup memory is provided, and if incorporated in the same device, the memory cell becomes extremely large and the circuit becomes complicated, which is not suitable for high integration. .

As described above, the ferroelectric memory is a promising memory element, but has a problem that its life is limited due to a wear-out phenomenon. Accordingly, it is an object of the present invention to provide a semiconductor memory device having a simple configuration and a long life while making the most of the feature of the nonvolatile memory of the ferroelectric memory.

[Constitution of the Invention] (Means and Action for Solving the Problems) The present invention provides a volatile operation of judging a storage state based on a stored charge amount without accompanying a polarization inversion of a dielectric capacitor, and a polarization operation of the ferroelectric capacitor. This is a semiconductor memory device that can select two operation states, namely, a nonvolatile operation in which a storage state is determined according to a direction. That is, in the normal operation, the ferroelectric capacitor is used as a simple capacitor, and the operation mode is switched so that the ferroelectric capacitor is used in a state accompanied by polarization reversal. This switching may be performed by an external signal that is appropriately input, or a signal may be obtained by turning on / off the power and the switching may be automatically performed based on the signal.

According to the present invention as described above, the ferroelectric capacitor causes polarization inversion only when the operation mode is the nonvolatile memory operation involving polarization inversion, and does not accompany polarization inversion in a normal volatile operation state. Can be extremely reduced. Therefore, the period until the wear-out of the ferroelectric material is reduced can be made much longer than that of the conventional ferroelectric memory, and the effect of improving the device life can be obtained. Also, as disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 64-66899, separate ferroelectric capacitors are not provided for the non-volatile operation and the volatile operation, but the ferroelectric capacitor is common and the element structure becomes complicated. There is no
The memory cell does not become large. Therefore, it is suitable for high integration.

 The basic operation principle of the present invention will be described with reference to FIG.

FIG. 1 is a characteristic curve diagram showing the applied voltage of a ferroelectric capacitor and the hysteresis of polarization. Drive voltage is Vd,
The corresponding maximum polarization is Pm, and the residual polarization is Pr. Note that Vd is a voltage at which an electric field larger than an electric field (coercive electric field) required for polarization inversion can be applied. Therefore, four points in the figure, P1, P2,
P3 and P4 can be represented by (voltage, polarization) coordinates, respectively: P1 = (Vd, Pm), P2 = (0, Pr), P3 = (-Vd, -Pm), P4 = (0, -Pr) Become.

According to the present invention, a storage method (a) in which the states of P1 and P2 correspond to "1" and "0" respectively, and a storage method (b) in which the states of P2 and P4 correspond to "1" and "0" respectively are selected. Will do.

(A) Storage method (volatile mode) P1 indicates that the ferroelectric capacitor is polarized in the positive direction and
This is a state in which charges (Pm-Pr) that can flow when both ends are short-circuited are accumulated. Although P2 is polarized in the positive direction, there is no charge that can flow when both ends are short-circuited. Therefore, if the state of the ferroelectric capacitor is set to two values of P1 and P2 and a voltage Vd is applied to the ferroelectric capacitor in that state, no new charge flows into the ferroelectric capacitor in the P1 state, but in the P2 state. The charge of (Pm-Pr) flows in. Therefore, the state of the ferroelectric capacitor can be detected by detecting the charge amount.

In this storage method, when the power is cut off, the charge of the ferroelectric capacitor in the P1 state cannot be stored due to a leak current or the like, so that the volatile operation is performed.

(B) Storage method (non-volatile mode) P2 indicates that the ferroelectric capacitor is polarized in the positive direction and
There is no charge that can flow when both ends are short-circuited. P4 is a state where the ferroelectric capacitor is polarized in the negative direction and there is no charge that can flow when both ends are short-circuited. Here, the state of the ferroelectric capacitor is set to two values of P2 and P4, and if the voltage Vd is applied to the ferroelectric capacitor in that state, the charge of (Pm−Pr) flows into the ferroelectric capacitor in the P2 state. Will do. Pm-(-Pr) for a ferroelectric capacitor in the P4 state
= (Pm + Pr). Therefore, the state of the ferroelectric capacitor can be detected by detecting the difference (2 · Pr) in the charge amount.

In this storage method, the storage state of the ferroelectric capacitor is stored as remanent polarization even when the power is turned off.
It becomes a nonvolatile operation.

The two operation modes are selectively used as described above. In order to enhance the detection accuracy, it is desirable that the difference between the charge amounts (Pm-Pr) and 2 · Pr be large. For this purpose, the squareness ratio (Pr / Pm) representing the hysteresis characteristic is 0.2
It is preferable to select a ferroelectric material in a range of about 0.7 to about 0.7. If it is larger than 0.7, (Pm-Pr) does not become too large, and if it is smaller than 0.2, 2.Pr cannot be made sufficiently large.
The composition system of the ferroelectric material constituting the ferroelectric capacitor is not particularly limited. For example, a ferroelectric material based on Pb (Zr, Ti) O ₃ or a ferroelectric material based on (Pb, La) (Zr, Ti) O ₃ The squareness ratio (Pr / Pm) can be adjusted by appropriately setting the composition, the film forming method, the applied voltage Vd, and the like using a dielectric material.

 Next, the basic operation of the present invention will be described with reference to FIG.

The basic configuration is a ferroelectric capacitor (1-1), a switching element (1-2) connected to one electrode thereof, a reference capacitor (2-1) and a switching element (2-2).
It is. The switching element (1-2) connects the ferroelectric capacitor (1-1) to the bit line (BL). The other electrode of the ferroelectric capacitor (1-1) is connected to the voltage supply means (3). One electrode of the reference capacitor (2-1) is connected to the bit line (BL '), and the other electrode is connected to the reference capacitor voltage supply means (4). The bit line pair is connected to the sense amplifier (5).

Basically, in the present invention, during the volatile operation, the ferroelectric capacitor (1-1) does not change the polarization state and is simply used as a capacitor for accumulating electric charge, and during the non-volatile operation, the ferroelectric capacitor (1-1) is used. The memory is performed by changing the polarization state of ()). Therefore, any method may be used as long as the state can be determined. However, a method of determining the voltage drop of the bit line pair by a sense amplifier, which is used in a normal DRAM, is simple.

First, during the volatile operation, the amount of charge flowing into the ferroelectric capacitor (1-1) when the bit line pair is connected to the Vcc level and is connected is Q1. At this time, the amount of charge flowing into the reference capacitor (2-1) is defined as Q2. Assuming that a state in which electric charges are accumulated in the ferroelectric capacitor (1-1) is “1” and a state in which no electric charge is accumulated is “0”, in the “0” state, the capacitance of the ferroelectric capacitor (1-2) ( A large amount of Q1 flows in according to Cm). On the other hand, in the "1" state, there is almost no newly flowing charge because the charge has already been stored. The amount of charge flowing into the reference capacitor (2-1) is determined by the precharge state. The sense amplifier compares the potential drops associated with Q1 and Q2 to determine each of the bit line pairs at a high level (for example, Vcc) and a low level (for example, Vss). If Q2 flowing into the reference capacitor (2-1) is set between Q1 (> 0) in the "0" state and 0, the bit line (BL) is in the "1" state.
At a high level and the bit line (BL ') at a high level in the "0" state. In this case, since it is certain that Q2 is out of both the states of 0 and Q1, Q2
Is desirably controlled to be an intermediate value between Q1 and 0.

Actually, at the time of connection with the bit line, electric charge determined by the balance with the bit line capacitance is introduced.

Q2 can be set by the capacitance of the reference capacitor (2-1) and the applied voltage. For example, the reference capacitor (2-
The capacitance (Cm ') of (1) is set to Cm' = 1 / 2.Cm, and in the precharge state, the potential of the reference capacitor voltage supply means (4) is set to the Vss level. And supply the Vss level to the reference capacitor (2
The charge amount stored in -1) is set to 0. When the determination is made by the sense amplifier, the potential of the reference capacitor voltage supply means (4) may be kept at the Vss level and the other end may be set to the bit line level, that is, the Vcc level. On the other hand, a potential of Vss level is supplied to the ferroelectric capacitor (1-1) by the voltage supply means (3). Now, when a bit line pair of Vcc level is connected, in the "1" state, the voltage of Vcc is applied to the ferroelectric capacitor (1-1). Capacitor (1-1)
The charge Q1 flowing into the reference capacitor (2-1) is almost zero, whereas the charge Q2 flowing into the reference capacitor (2-1) is a capacitance Cm '(= 1 / 2.Cm).
And an electric charge corresponding to the applied voltage (Vcc). Therefore, Q
2> Q1, and the sense amplifier (5) is activated to determine the bit line (BL) at a high level and the bit line (BL ') at a low level. In the “0” state, Q1 is a charge corresponding to the capacitance Cm and the applied voltage Vcc, but Q2 is a charge amount corresponding to the capacitance Cm ′ (= 1/2 · Cm) and the applied voltage Vcc as in the case of “1”. Becomes Therefore, Q1> Q2, and the bit line (BL ') is determined to be high and the bit line (BL) is determined to be low.

Also, let Q3 be the amount of charge flowing into the ferroelectric capacitor (1-1) when the bit line pair is connected to the Vcc level during the nonvolatile operation and connected. At this time, the reference capacitor (2-
Let Q4 be the amount of charge flowing into 1). If the direction of polarization of the ferroelectric capacitor (1-1) is the direction of the bit line (BL) and "1" is the reverse direction, a large amount of polarization inversion occurs in the "0" state. Charge (Q3) of the ferroelectric capacitor (1-
Flow into 1). On the other hand, in the "1" state, since there is no polarization inversion, only the charge (Q1) corresponding to the capacitance (Cm) flows. Therefore, the amount of charge flowing into the reference capacitor (2-1)
If Q4 is set between Q1 and Q3, Q1 <
Since it is Q4, the bit line (BL) can be determined to be at a high level, and in the "0" state, since Q4 <Q3, the bit line (BL ') can be determined to be at a high level. In this case, since it is certain that Q4 is out of the state of both Q3 and Q1, Q4
It is desirable to control so as to be an intermediate value between Q3 and Q3.

For example, the capacitance (Cm ') of the reference capacitor (2-1) is
In the precharge state, the potential of the reference capacitor voltage supply means (4) is set to the Vss level, and the other end is also supplied with the Vss level via a switching element (not shown) to supply the reference capacitor (2-1). ) Is 0. On the other hand, a potential of Vss level is supplied to the ferroelectric capacitor (1-1) by the voltage supply means (3). Now, if you connect a pair of Vcc-level bit lines,
In the “1” state, a voltage having the same polarity as the polarization direction is applied to the ferroelectric capacitor (1-1), so that no polarization inversion occurs, and only a charge amount Q1 equivalent to the capacitance Cm flows in. The reference capacitor (2-1) has a capacitance Cm '(= 2 · C
m) and the charge Q4 corresponding to the applied voltage (Vcc) flows.
Therefore, Q4> Q1, and the bit line (BL) is determined to be high and the bit line (BL ') is determined to be low. In the “0” state, a voltage that causes polarization inversion is applied to the ferroelectric capacitor (1-1). Therefore, Q3 has a large amount of electric charge (for example, 3 · Cm equivalent)
However, since Q4 is the same as "1" and Q4> Q2, the bit line (BL ') is determined to be high and the bit line (BL) is determined to be low.

The writing can be performed by forcibly setting the bit line pair to "0" or "1" and turning on the switching elements (1-2) and (2-1).

Thus, the reference capacitor may be selected according to the operation mode. Although only one reference capacitor is shown in FIG. 2, a plurality of reference capacitors may be prepared, switched, and the applied potential may be controlled by the reference capacitor voltage supply means. More specifically, a ferroelectric capacitor; a switching element connected to one electrode of the ferroelectric capacitor; and a switching element connected to the other electrode of the ferroelectric capacitor.
A first voltage application unit for controlling a voltage applied to the ferroelectric capacitor to apply a voltage that does not change the polarization direction of the ferroelectric capacitor regardless of stored information; and a change in the polarization direction of the ferroelectric capacitor. Voltage supply means for selecting one of the second voltage application means for applying a voltage that can be applied; and when the first voltage application means is selected, a charge smaller than the charge quantity flowing into the ferroelectric capacitor flows. A first reference capacitor having a capacitance set to perform the above operation; and when the second voltage applying means is selected, the amount of charge flowing when the polarization inversion occurs in the ferroelectric capacitor is smaller, and the polarization inversion occurs. The second is a capacitor whose capacity is set so that a current larger than the amount of charge flowing when there is no
A reference capacitor; a sense amplifier connected to the first and second reference capacitors and the ferroelectric capacitor; and a first amplifier when the voltage supply unit selects the first voltage application unit. Select a reference capacitor and
And a reference capacitor selecting means for selecting the second reference capacitor and connecting to the sense amplifier when the voltage applying means is selected, wherein the ferroelectric capacitor and the reference capacitor are connected via a bit line pair to the sense amplifier. Connected to the ferroelectric capacitor and the reference capacitor, the sense amplifier amplifies the degree of voltage drop caused by the charge flowing when a voltage is applied from the bit line to the ferroelectric capacitor and the reference capacitor, and changes the storage state of the ferroelectric capacitor to the potential of the bit line pair. It may be configured so that reading is performed at a high or low level.

The charge amount flowing into the reference capacitor may be based on the state where the accumulated charge amount is 0, or may be based on the charge amount that is charged to some extent and stacked and then flows.

In the above description, a plurality of reference capacitors are used and the voltage applied to the reference capacitor is fixed. However, the voltage applied to the reference capacitor may be changed by fixing one reference capacitor, that is, Cm '. For example, a ferroelectric capacitor (1-
Assuming the same Vcc applied voltage as in 1), Q3 (when the polarization is inverted)>Q4> Q3 (when the polarization is not inverted), Q1 ("0")>Q2> Q1
The voltage applied to the reference capacitor (2-1) may be controlled so as to satisfy (“1”). For example, the capacitance corresponding to the amount of charge flowing into the ferroelectric capacitor at the time of polarization inversion is Cm ″ = 3.
・ If it is about Cm ', the reference capacitor capacity (Cm') becomes
Cm ′ = 2 · Cm, the reference accumulated charge amount is set to 0 in the nonvolatile operation, and the charge amount at 3/4 · Vcc is set to the reference in the volatile operation, and the inflowing charge amount may be compared. Reading is the same as in the previous example. As a specific configuration, for example, a ferroelectric capacitor; a switching element connected to one electrode of the ferroelectric capacitor; and a switching element connected to the other electrode of the ferroelectric capacitor,
A first voltage application unit for controlling a voltage applied to the ferroelectric capacitor to apply a voltage that does not change the polarization direction of the ferroelectric capacitor regardless of stored information; and a change in the polarization direction of the ferroelectric capacitor. Voltage supply means for selecting one of second voltage application means for applying a voltage that can be applied; a reference capacitor; a sense amplifier connected to the ferroelectric capacitor and the reference capacitor; and the first voltage application. When the means is selected, an electric charge smaller than the electric charge flowing into the ferroelectric capacitor flows into the reference capacitor, and when the second voltage applying means is selected, the polarization inversion occurs in the ferroelectric capacitor. Less than the amount of charge flowing into the reference capacitor, and more than the amount of charge flowing when no polarization reversal occurs. Reference capacitor selecting means for controlling an amount of charge to be charged in the reference capacitor, wherein the ferroelectric capacitor and the reference capacitor are connected to a sense amplifier via a bit line pair, and a drive voltage is applied to the ferroelectric capacitor and the reference capacitor. It is sufficient to amplify the degree of the voltage drop caused by the electric charge flowing when the voltage is applied by the sense amplifier, and to read out the storage state of the ferroelectric capacitor depending on the level of the potential of the bit line pair.

The case where two types of reference capacitors are used for volatile operation and non-volatile operation (including the case where the drive voltage is changed) has been described above. However, the reference capacitor is designed so that the charge amount or the polarization direction changes complementarily. May be configured to detect the "0" and "1" states by comparing the two. In other words, during volatile operation, when charge is stored in one of the ferroelectric capacitors, the other is in a state where no charge is stored. The potential drop is larger on the bit line on the ferroelectric capacitor side, and the bit line on the ferroelectric capacitor side in the charge storage state is determined to be at a higher level. In the nonvolatile operation, if the polarization direction of the ferroelectric capacitor is complementarily changed, the potential of the bit line pair can be fixed as described above. That is, since the potential drop of the bit line on the ferroelectric capacitor side whose polarization is directed to the bit line side is smaller, the bit line on the ferroelectric capacitor side is determined to be at a lower level.

According to the present invention as described above, the ferroelectric capacitor is usually used in a state where no polarization reversal occurs, whereby the write / read cycle time can be shortened and the wear-out phenomenon can be suppressed. Further, since the operation can be switched to the nonvolatile operation while using the same ferroelectric capacitor, the nonvolatile information can be substantially realized. That is, there is no need to perform non-volatization when power is supplied, but only when power is turned off. Compared with the conventional case where separate memories are provided, the present invention has a structure in which high integration is alienated. This is very effective because it is usually a volatile operation without any complication and can be changed to a non-volatile operation at a special time.

(Example) An example of the present invention will be described below.

Embodiment 1 FIG. 3 is a circuit diagram showing an embodiment of the present invention.

One memory cell (31) includes a switching element (311) and a ferroelectric capacitor (312). The switching element (311) is connected to the word line driving section (32) and is selectively driven by the word line (WL31). One electrode of the ferroelectric capacitor (312) is connected to the bit line (BLa) via the switching element (311), and the other electrode is connected to the plate line control means (33) (voltage) via the plate line (PL31). Supply means). This plate line (PL31)
Is set to the Vss level via the switching element (331) driven by the plate line switching line (DC31) from the plate line switching drive unit (333).
It is connected to the plate line drive unit (334) via the switching element (332) driven by the unit (32).

The reference part (34) is basically a reference capacitor (341) and a switching element (343) (344) for volatile operation.
Cell for volatile operation (347) consisting of: Reference capacitor (342) and switching element (345) for nonvolatile operation
(346) and a nonvolatile operation cell (348). One electrode of the reference capacitor (341) is connected to a bit line (BLa ') via a drive switching element (343). The switching element (343) is selectively driven by a dummy word line (DWL31) connected to a dummy word line driving section (39) (reference capacitor selecting means). The other electrode is connected to the Vss level. Both electrodes of the reference capacitor (341) are connected via a switching element (344) for precharging. The precharge switching element (344) is controlled by the precharge drive unit (35). One electrode of the reference capacitor (342) for nonvolatile operation is connected to the Vss level,
The other electrode is connected to the bit line (BLa ') via the switching element (345). The switching element (345) is selectively driven by a dummy word line (DWL32) connected to the dummy word line driving section (39). Both electrodes of the reference capacitor (342) for nonvolatile operation are connected to the electrodes via a switching element (346) for precharging. The switching element for precharge (34
6) is controlled by the precharge drive section (35). One end of the bit line pair (BLa) (BLa ') is a sense amplifier (36)
The other end is connected to the data input / output line (I / O) via the switching element (371) (372) of the column means selection (37).
(I / O '), and further connected to the data input / output unit (38). The column selecting means (37) includes the switching elements (371) and (372) and a column selection line driving section (373) for driving the switching elements. Bit line pair (BLa) (BLa ')
Are connected to the Vcc level via switching elements (SW31) and (SW32) driven by the precharge driving unit (35). In addition, the bit line (BL
a) In order to balance the potential of (BLa '), the bit line pair is connected via a switching element (SW33) driven by a precharge driver (35).

Based on the above configuration, one sensor amplifier is connected to one reference unit and many memory cells to form one column (a). Note that the selection of the ferroelectric capacitor and the reference capacitor is the same as the operation of the folded same as the DRAM. A large number of columns exist in the semiconductor memory device, and each column is selected by column selecting means. The memory cell in the selected column is selected by the word line driving unit.
The reference capacitor is selected according to a volatile operation or a nonvolatile operation. This is a basic circuit configuration, and may be added or changed within a range in which substantially the same operation is performed.

Next, the operation of this embodiment will be described with reference to a timing chart (FIG. 4). Note that the gate line drive is set at 7.5V and the bit line is set at 5V.

The reference capacitor (341) during volatile operation is smaller than the capacitance of the ferroelectric capacitor (312) during volatile operation, that is, smaller than the capacitance without polarization reversal (Cm). It is set to have a capacity. The reference capacitor (342) used in the non-volatile operation stores a charge smaller than the charge flowing into the ferroelectric capacitor (312) at the time of polarization reversal, and has a capacity larger than Cm and is approximately 2 · Cm.
Is set to

(1) Volatile operation mode In this mode, the state where electric charge is accumulated in the ferroelectric capacitor (312) is “1”, and the state where electric charge is not accumulated is “0”. Charge storage in the ferroelectric capacitor (312) is performed by applying a voltage in one direction so as not to cause polarization inversion.

(A) Write operation In the standby state, the precharge line (PC) is in the high level state, and the bit line pair (BLa) (BLa ') is kept at the Vcc level. Also, the reference capacitor (341) is short-circuited. As for the plate line (PL31), the plate line switching drive unit (333) outputs a signal for setting the plate line switching line (DC31) to a high level, and the switching element (331) is turned on by this signal to be connected to the Vss level. It is set as follows.

When the chip enable signal (CE) is input from the outside, the chip is activated and the precharge line (PC) is at a low level, so that the bit line pair (BLa) (BLa ')
Floating state at Vcc level. According to the contents of the address signal of the memory cell and the designation of the operation mode, for example, the word line (WL31) and the dummy word line (DWL31) become high level, the switching elements (311) and (343) turn on, and the ferroelectric capacitor ( 312) and the reference capacitor (341) are connected to the bit lines (BLa) (BLa '), respectively. The potential of the bit line drops according to the charge storage state of the ferroelectric capacitor (312) and the reference capacitor (341). Subsequently, by activating the sense amplifier (36), the potentials of the bit lines (BLa) (BLa ') are complementarily determined to be high and low.

For example, in the "1" state, ferroelectric capacitor (312)
Since the electric charge is accumulated in the bit line (BLa), the potential drop of the bit line (BLa) is small. On the other hand, since the reference capacitor (341) does not accumulate charges, a predetermined amount of potential drop is determined by the capacitance of the reference capacitor (341) and the bit line capacitance.
Therefore, the bit line (BLa) on the ferroelectric capacitor (312) side
The potential of the bit line (BL) on the reference capacitor (341) side is
a ′), and the bit line (BLa) is determined to be at a high level and the bit line (BLa ′) is determined to be at a low level.

On the other hand, in the "0" state, since no charge is stored in the ferroelectric capacitor (312), the charge flows in according to the capacitance, and the potential of the bit line (BLa) decreases. Since the capacitance of the reference capacitor (341) is smaller than the capacitance of the ferroelectric capacitor (312), the bit line (BL
The potential drop of a ') is smaller than that of the ferroelectric capacitor (312). Therefore, the potential of the bit line (BLa) on the ferroelectric capacitor (312) side is lower than the bit line (BLa ') on the reference capacitor (341) side, and the potential of the bit line (BLa') is lower.
At a high level and the bit line (BLa) at a low level.

Thereafter, the column selection line (CSLa) is driven to a high level by the column selection line driving unit (373), the switching elements (371) and (372) are turned on, and the data input / output lines (I /
O) (I / O '). Here, the data input / output line (I /
The bit lines (BLa) and (BLa ') are forcibly rewritten to the setting states of O) and (I / O'). Therefore, data input / output lines (I / O)
Is high, charge is stored in the ferroelectric capacitor (312). If the data input / output line (I / O) is low, no charge is stored. "The state will be remembered.

Return to the precharge state is started when the chip enable signal (CE) returns to the high level, and the word line (WL31), dummy word line (DWL31), and column select line (C
SLa) is set to a low level, and each drive unit issues a signal, and the switching elements (311) (343) (371)
(372) turns off and then the precharge line (PC)
Precharge driver (35) to set to high level
Outputs a signal to end a series of write operations.

When the operation is continuously performed in different columns, the operation may be continued without performing the operation of returning to the precharge state.

In the above description, writing is performed after the potential of the bit line pair is once determined. However, writing from the data input / output line may be performed without waiting for the determination.

(B) Read operation The operation up to the determination of the potential of the bit line pair is the same as (a) the write operation. After that, a high-level signal is output from the column selection line driver (373) to the column selection line (CSLa), the switching elements (371) and (372) are turned on, and the information determined by the sense amplifier (36) is input and output. Line (I / O) (I
/ O ').

The return to the precharge state is similar to (a) the write operation.

(2) Nonvolatile operation mode In this mode, data is stored in the polarization direction of the ferroelectric capacitor (312). When the polarization is oriented in the direction of the plate line (PL31), it is set to "1", and when it is oriented to the bit line (BLa '), it is set to "0".

(A) Write operation In the standby state, the bit line pair (BLa) (BLa ') is kept at the Vcc level, as in the volatile operation. Plate line (PL31) is a plate line switching driver (333)
However, a signal for setting the plate line switching line (DC32) to a high level is output, and the switching element (332) is turned ON to be connected to the plate line driving unit (334). Initially, a low level (Vss) signal is supplied to the plate line (PL31).

When the chip enable signal (CE) is input from the outside, the chip is activated and the precharge line (PC) is at a low level, so that the bit line pair (BLa) (BLa ')
Floating state at Vcc level. According to the contents of the address signal of the memory cell and the designation of the operation mode, for example, the word line (WL31) and the dummy word line (DWL32) become high level, the switching elements (311) and (345) are turned on, and the ferroelectric capacitor ( 312) and the reference capacitor (342) are connected to the bit lines (BLa) (BLa '), respectively. Accordingly, the potential of the bit line decreases.
Subsequently, by activating the sense amplifier (36), the potentials of the bit lines (BLa) (BLa ') are complementarily determined to be high and low.

For example, in the "1" state, ferroelectric capacitor (312)
Are polarized in the direction of the plate line (PL31). That is, the bit line (BLa) is polarized to a high potential state. Therefore, even if the bit line (BLa) in the floating state at the Vcc level is connected, it has the same polarity as the polarization polarity, so that there is only charge inflow for the capacity (Cm) as a capacitor. In contrast, the reference capacitor (342) has a capacitance (2 cm)
Since the electric charge for the current flows into the bit line (BLa ′) on the side of the reference capacitor (342), the potential of the bit line (BLa) is increased to a high level by the sense amplifier (36). ) At a low level.

On the other hand, in the "0" state, the ferroelectric capacitor (312) is polarized in the direction of the bit line (BLa). Therefore, when the floating bit line (BLa) at the Vcc level is connected, an electric field having the opposite polarization polarity is generated in the ferroelectric capacitor (3).
This is applied to 1), and polarization inversion occurs. As a result, a large amount of charge flows into the ferroelectric capacitor (312).
The potential drop of the bit line (BLa) on the side is larger, and the sense amplifier (36) sets the bit line (BLa ') to a high level.
The bit line (BLa) is set to a low level.

Thereafter, the column selection line (CSLa) is driven to a high level by the column selection line driving unit (373), the switching elements (371) and (372) are turned on, and the data input / output lines (I /
O) (I / O '). Here, the data input / output line (I /
The bit lines (BLa) and (BLa ') are forcibly rewritten to the setting states of O) and (I / O'). Plate wire (BL31) as described above
Is initially set to a low level, so when the data input / output line (I / O) is at a high level, the ferroelectric capacitor (312)
Is the polarization direction of the “1” state.

When the data input / output line (I / O) is at a low level, both ends of the ferroelectric capacitor (312) are at a low level, so that no polarization inversion occurs. At this time, the potential of the Vcc level is supplied from the plate line driving unit (334), so that the state of the ferroelectric capacitor (312) is in the polarization direction of the "1" state, so that a voltage having the opposite polarity to the polarization is applied. As a result, polarization inversion occurs, and the polarization direction becomes the “0” state.

Return to the precharge state is started when the chip enable signal (CE) returns to the high level, and the word line (WL31), dummy word line (DWL32), and column select line (C
SLa) is set to a low level, and each drive unit issues a signal, and the switching elements (311) (343) (371)
(372) turns off and then the precharge line (PC)
Precharge drive unit (35) to set to high level
Outputs a signal to end a series of write operations.

When the next operation is continuously performed, the operation may be continued without performing the operation of returning to the precharge state.

In the above description, writing is performed after the potential of the bit line pair is once determined. However, writing from the data input / output line may be performed without waiting for the determination.

(B) Read operation The operation up to the determination of the potential of the bit line pair is the same as (a) the write operation. After that, a high-level signal is output from the column selection line driver (373) to the column selection line (CSLa), the switching elements (371) and (372) are turned on, and the information determined by the sense amplifier (36) is input and output. Line (I / O) (I
/ O ').

The return to the precharge state is similar to (a) the write operation.

 Next, switching of the operation mode will be described.

(3) Volatile operation → Nonvolatile operation The above-mentioned (1) volatile operation mode (b) read operation is performed to determine the potential level of the bit line pair (BLa) (BLa ′). Ferroelectric capacitor (312) if "1"
The bit line (BLa) on the reference capacitor (341) side is determined to be at a high potential if the bit line (BLa) on the side is at a high potential and in the "0" state.

Then, a signal for setting the plate switching line (DC31) to a low level and the plate switching line (DC32) to a high level from the plate line switching driving unit (333) is output, and the switching element (331) is turned off. Is turned ON, the plate line (PL31) is connected to the plate line drive (34
Connect to 4) and switch to nonvolatile operation mode. At this time, nonvolatile storage can be performed at the determined potential of the bit line (BLa). That is, since the plate line (PL31) is initially set to the low level in the non-volatile operation, when "1", the bit line (BLa) is at the high level, and the polarization direction is in the "1" state. Even if the Vcc level potential is continuously supplied from the plate line drive unit, the potentials at both ends of the ferroelectric capacitor (312) are merely equalized, and the polarization state is not inverted and is maintained at "1". Conversely, when it is "0", the bit line (BLa) is at a low level and both ends of the ferroelectric capacitor (312) are at a low level, so that no polarization inversion occurs. At this time, by supplying a Vcc level potential from the plate line driving unit (334),
The ferroelectric capacitor (312) is applied with a voltage having a polarity opposite to that of the polarization, so that a polarization inversion occurs and the polarization direction becomes the “0” state.

(3) Non-volatile operation → volatile operation The (b) read operation of the above-mentioned (2) nonvolatile operation mode is performed to determine the potential level of the bit line pair (BLa) (BLa '). Ferroelectric capacitor (312) if "1"
The bit line (BLa) on the reference capacitor (341) side is determined to be at a high potential if the bit line (BLa) on the side is at a high potential and in the "0" state.

Next, a signal for setting the plate switching line (DC32) to a low level and the plate switching line (DC31) to a high level from the plate line switching drive unit (333) is output, and the switching element (332) is turned off. Is turned on to connect the plate line (PL31) to the Vss level.
This switches to the volatile operation mode. Therefore, writing can be performed in the same manner as (a) writing operation in the above-mentioned (2) volatile operation mode. That is, if the bit line (BLa) is at a high level, the ferroelectric capacitor (31
2) Charge accumulation occurs, and if the level is low, the charge accumulation does not occur. Therefore, information at the time of nonvolatile operation is written as volatile storage.

As described above, the switching of the operation mode can be performed by rewriting the information before the switching as the information in the mode after the switching.

In the above description, the plate line driving unit (334) supplies the high-level and low-level potentials. However, only the high level is supplied, and instead, the plate-line switching driving unit (333)
The switching element (332) is turned ON only when a high-level potential is supplied, and the switching element (331) is turned ON otherwise to supply a Vcc-level potential. The configuration may be such that the potential state of DC32) is controlled.

Although the above description is only for one memory cell,
In an actual device, a large number of memories in the column (a) are sequentially selected and driven under the control of the word line driving section (32), and a large number of columns are sequentially selected and driven under the control of the column selection means (37). Will do.

Embodiment 2 FIG. 5 is a circuit diagram showing another embodiment of the present invention.

The configuration of one memory cell (51) is the same as that of the first embodiment.
The switching element (511) is connected to the word line (WL51) and is driven by the word line driving section (52). One electrode of the ferroelectric capacitor (512) is connected to the bit line (BLa) via the switching element (511), and the other electrode is connected to the plate line control means (53) (voltage) via the plate line (PL51). Supply means). The plate line (PL51) is connected to the Vss level via the switching element (531) driven by the plate line switching line (DC51) from the plate line switching drive unit (533), and is connected to the plate line switching line (DC52). It is connected to the plate line drive section (534) via the driven switching element (532).

This embodiment is different from the first embodiment in that the number of reference capacitors in the reference section is one.

The reference section (54) includes a reference capacitor (541) and switching elements (542) (543). One electrode of this reference capacitor (541) is a driving switching element (54
2) to the bit line (BLa '). The switching element (542) is selectively driven by a dummy word line (DWL51) connected to the dummy word line driving section (59). The other electrode of the reference capacitor (541) is connected to the Vss level. The electrode on the switching element (542) side of the reference capacitor (541) is connected to the precharge potential supply line (DPC51) via the precharge switching element (543). The precharge switching element (543) is driven by a precharge line (PC) to which a signal is supplied by a precharge driver (55). The precharge potential supply line (DPC51) is configured to be supplied with the potentials Vd1 and Vd2 via the switching elements (PC51) and (PC52). Switching of the potential
This is performed by a signal on a potential switching line (DC53) (DC54) connected to the potential switching drive unit (PCS51). This constitutes reference capacitor charge control means.

One end of the bit line pair (BLa) (BLa ') is connected to the sense amplifier (56), and the other end is connected to the data input / output line (I / I / I) via the switching element (571) (572) of the column selection means (57). O) (I / O '), and further connected to the data input / output unit (58). The column selecting means (57) includes the switching elements (571) and (572) and a column selection line driving section (573) for driving the switching elements. Bit line pair (BLa)
(BLa ') is connected to the Vcc level via the switching elements (SW51) and (SW52) driven by the precharge driving unit (55). The bit line pair is connected via a switching element (SW53) driven by a precharge driving section (55).

Based on the above configuration, one reference section and many memory cells are connected to one sense amplifier to form one column (a).

In this embodiment, the amount of charge previously stored in the reference capacitor is controlled by switching the charge voltage at the time of precharging, and the amount of charge flowing in when connecting to the bit line is controlled. The same operation as in the case where the reference capacitor is provided is performed. In this embodiment, the capacitance (C) of the ferroelectric capacitor (512) when the polarization is not inverted is shown.
m) and the capacitance (C
m ′) and (Cf) of the reference capacitor (541) were set so as to substantially satisfy the following relationship.

Cm ′ = 3 · Cm, Cf = 2 · Cm A voltage of Vcc level with respect to the reference potential Vss is applied to the ferroelectric capacitor (512), and the precharge potential (Vd1) of the reference capacitor (541) is applied. Is set to 3/4 Vcc during volatile operation, and Vss during non-volatile operation (Vd2).
(0 V). With this setting, "0" is stored in the ferroelectric capacitor (512) in both volatile operation and non-volatile operation.
In accordance with the storage state of “1”, an electric charge of an intermediate value of the electric charges flowing in flows into the reference capacitor (541). Therefore, both can be accurately determined without biasing the determination by the sense amplifier.

Next, the operation of this embodiment will be described with reference to a timing chart (FIG. 6).

(1) Volatile operation mode In this mode, the state where charge is stored in the ferroelectric capacitor (512) is set to “1”, and the state where no charge is stored is set to “0”. Charge storage in the ferroelectric capacitor (512) is performed by applying a unidirectional electric field without polarization inversion.

(A) Write operation In the standby state, the precharge line (PC) is in the high level state, and the bit line pair (BLa) (BLa ') is kept at the Vcc level. The reference capacitor (541) is connected to the reference potential (V
ss), a potential of Vd1 (= 3/4 · Vcc) is applied. For the plate line (PL51), the plate line switching drive unit (533) issues a signal that sets the plate line switching line (DC51) to a high level, and this signal is used to switch the switching element (531).
Is set to ON and connected to the Vss level.

When the chip enable signal (CE) is input from the outside, the chip is activated and the precharge line (PC) is at a low level, so that the bit line pair (BLa) (BLa ')
Floating state at Vcc level. According to the contents of the address signal of the memory cell and the designation of the operation mode, for example, the word line (WL51) and the dummy word line (DWL51) become high level, the switching elements (511) and (542) are turned on, and the ferroelectric capacitor ( 312) and the reference capacitor (541) are connected to the bit lines (BLa) (BLa '), respectively. The potential of the bit line drops according to the charge storage state of the ferroelectric capacitor (512) and the reference capacitor (541). Subsequently, by activating the sense amplifier (36), the potentials of the bit lines (BLa) (BLa ') are complementarily determined to be high and low.

For example, when in the "1" state, ferroelectric capacitor (512)
Since the electric charge is accumulated in the bit line (BLa), the potential drop of the bit line (BLa) is small. In contrast, the reference capacitor (341)
Only accumulates the charge at the applied voltage of 3/4 Vcc, the remaining 1/4
Charges corresponding to the applied voltage corresponding to Vcc flow into the reference capacitor (541) more than the ferroelectric capacitor (512). Therefore ferroelectric capacitor (512)
The potential of the bit line (BLa) on the side is the reference capacitor (54
Since the bit line (BLa ') is higher than the bit line (BLa') on the 1) side, the bit line (BLa) is set to a high level and the bit line (BLa ') is set to a low level.

On the other hand, in the "0" state, since no charge is stored in the ferroelectric capacitor (512), the charge flows in according to the application of the Vcc level voltage, and the potential of the bit line (BLa) decreases. The reference capacitor (541) has a 1/4
Charges corresponding to Vcc will flow. Therefore,
Since the potential of the bit line (BLa) on the ferroelectric capacitor (512) side is lower than the bit line (BLa ') on the reference capacitor (541) side, the bit line (BLa') is set to a high level, (BLa) is fixed to a low level.

Thereafter, the column selection line (CSLa) is driven to a high level by the column selection line driving section (573), the switching elements (571) and (572) are turned on, and the data input / output lines (I /
O) (I / O '). Here, the data input / output line (I /
O) Return to the precharge state is started when the chip enable signal (CE) returns to the high level, and the word line (WL51), dummy word line (DWL51), and column select line (C
SLa) is set to a low level, and each drive section issues a signal, and the switching elements (511) (542) (571)
(572) is turned off, and then the precharge line (P
C) to the high level so that the precharge driver (5
5) outputs a signal to end a series of write operations.

When the next operation is continuously performed, the operation may be continued without performing the operation of returning to the precharge state.

In the above description, the bit lines (BLa) and (BLa ') are forcibly rewritten to the setting state of the power (I / O') of the bit line pair. Therefore, when the data input / output line (I / O) is at a high level, electric charges are accumulated in the ferroelectric capacitor (512), and when the data input / output line (I / O) is at a low level, electric charges are accumulated. There is no accumulation, and the "1" and "0" states are stored, respectively.

Although the writing is performed after the position is determined, the writing from the data input / output line may be performed without waiting for the determination.

(B) Read operation The operation up to the determination of the potential of the bit line pair is the same as (a) the write operation. After that, a high-level signal is output from the column selection line driving unit (573) to the column selection line (CSLa), the switching elements (571) and (572) are turned on, and information determined by the sense amplifier (56) is input / output data. Line (I / O) (I
/ O ').

The return to the precharge state is similar to (a) the write operation.

(2) Nonvolatile operation mode In this mode, data is stored in the polarization direction of the ferroelectric capacitor (512). When the polarization is oriented in the direction of the plate line (PL51), it is set to "1", and when it is oriented to the bit line (BLa '), it is set to "0".

(A) Write operation In the standby state, the bit line pair (BLa) (BLa ') is kept at the Vcc level, as in the volatile operation. Also, the reference capacitor (541) is
A potential of Vd2 (= Vss) is applied, resulting in a short circuit. For the plate line (PL51), the plate line switching starter (533) issues a signal that sets the plate line switching line (DC51) to low level and (DC54) to high level, and the switching element (532) It is set to be ON and connected to the plate line drive unit (534).

When the chip enable signal (CE) is input from the outside, the chip is activated and the precharge line (PC) is at a low level, so that the bit line pair (BLa) (BLa ')
Floating state at Vcc level. According to the contents of the address signal of the memory cell and the designation of the operation mode, for example, the word line (WL51) and the dummy word line (DWL51) become high level, the switching elements (511) and (542) are turned on, and the ferroelectric capacitor ( 512) and a reference capacitor (541) are connected to the bit lines (BLa) (BLa '), respectively. Accordingly, the potential of the bit line decreases.
Subsequently, by activating the sense amplifier (56), the potentials of the bit lines (BLa) (BLa ') are determined complementarily to high and low levels.

For example, when in the "1" state, ferroelectric capacitor (512)
Are polarized in the direction of the plate line (PL51). That is, the bit line (BLa) is polarized to a high potential state. Therefore, even if the bit line (BLa) in the floating state at the Vcc level is connected, it has the same polarity as the polarization polarity, so that there is only charge inflow for the capacity (Cm) as a capacitor. On the other hand, the reference capacitor (541) has a capacitance (2 cm)
Since the electric charge for the current flows in, the potential of the bit line (BLa ') on the side of the reference capacitor (541) drops greatly, and the sense amplifier (56) sets the bit line (BLa) to a high level and the bit line (BLa'). ) At a low level.

On the other hand, in the "0" state, the ferroelectric capacitor (512) is polarized in the direction of the bit line (BLa). Therefore, when a bit line (BLa) in a floating state at the Vcc level is connected, an electric field having the opposite polarization polarity is applied to the ferroelectric capacitor (51
2), polarization inversion occurs. Therefore, a large amount of charge flows. On the other hand, the same charge inflow as in the “1” state occurs in the reference capacitor (541). Therefore, the potential drop of the bit line (BLa) on the ferroelectric capacitor (512) side is large, and the sense amplifier (56) determines the bit line (BLa ') at a high level and the bit line (BLa) at a low level. I do.

Thereafter, the column selection line (CSLa) is driven to a high level by the column selection line driving section (573), the switching elements (571) and (572) are turned on, and the data input / output lines (I /
O) (I / O '). Here, the data input / output line (I /
The bit lines (BLa) and (BLa ') are forcibly rewritten to the setting states of O) and (I / O'). Plate wire (BL51) as described above
Is initially set to a low level, so when the data input / output line (I / O) is at a high level, the ferroelectric capacitor (512)
Is the polarization direction of the “1” state. Data input / output line (I /
When O) is at a low level, both ends of the ferroelectric capacitor (512) are at a low level, so that no polarization inversion occurs. At this time, by supplying a Vcc-level potential from the plate line driving section (534), the state of the ferroelectric capacitor (512) is in the polarization direction of "1", so that a voltage of the opposite polarity is applied. Then, polarization inversion occurs, and the polarization direction becomes the “0” state.

Return to the precharge state is started when the chip enable signal (CE) returns to the high level, and the word line (WL51), dummy word line (DWL52), and column select line (C
SLa) is set to a low level, and each drive section issues a signal, and the switching elements (511) (542) (571)
(572) turns off and then the precharge line (PC)
Precharge driver (55) to set to high level
Outputs a signal to end a series of write operations.

When the next operation is continuously performed, the operation may be continued without performing the operation of returning to the precharge state.

In the above description, writing is performed after the potential of the bit line pair is once determined. However, writing from the data input / output line may be performed without waiting for the determination.

(B) Read operation The operation up to the determination of the potential of the bit line pair is the same as (a) the write operation. After that, a high-level signal is output from the column selection line driving unit (573) to the column selection line (CSLa), the switching elements (571) and (572) are turned on, and information determined by the sense amplifier (56) is input / output data. Line (I / O) (I
/ O ').

The return to the precharge state is similar to (a) the write operation.

 Next, switching of the operation mode will be described.

(3) Volatile operation → Nonvolatile operation The above-mentioned (1) volatile operation mode (b) read operation is performed to determine the potential level of the bit line pair (BLa) (BLa ′). Ferroelectric capacitor (512) if "1"
The bit line (BLa ') on the reference capacitor (541) side is set to a high potential if the bit line (BLa) on the side is set to the high potential and in the "0" state.

Then, a signal for setting the plate switching line (DC51) to a low level and the plate switching line (DC52) to a high level from the plate line switching driving unit (533) is output, and the switching element (531) is turned off. Is turned on, the plate line (PL51) is connected to the plate line drive (53
4) Connect. This switches to the non-volatile operation mode. Determination of bit line (BLa) (4) Non-volatile operation → volatile operation The above-mentioned (2) Non-volatile operation mode (b) Performs the read operation and performs the non-volatile mode by the potential of the bit line pair (BLa) (BLa ′). I can remember. That is, in the non-volatile operation mode, the plate line (PL51) is initially set to the low level, so that when it is "1", the polarization direction is "1". Even if the potential at the Vcc level is subsequently supplied from the plate line driving section, the potentials at both ends of the ferroelectric capacitor (312) only become equal, the polarization state does not change, and the "1" state is maintained. Conversely, when it is "0", the bit line (BLa) is at a low level, and both ends of the ferroelectric capacitor (512) are at a low level, so that no polarization inversion occurs. At this time, when a potential of Vcc level is supplied from the plate line driving unit (534), a voltage having a polarity opposite to that of the polarization is applied to the ferroelectric capacitor (512). "It becomes the polarization direction of the state.

Is determined. In the “1” state, the bit line (BLa) on the ferroelectric capacitor (512) side is set to the high potential and “0”.
If it is in the state, the bit line (BL
a ′) is determined to be a high potential.

Next, a signal for setting the plate switching line (DC52) to a low level and the plate switching line (DC51) to a high level from the plate line switching driving unit (533) is output, and the switching element (532) is turned off. Is turned on to connect the plate line (PL51) to the Vss level.
This switches to the volatile operation mode. Therefore, writing can be performed in the same manner as (a) writing operation in the above-mentioned (2) volatile operation mode. That is, if the bit line (BLa) is at a high level, the ferroelectric capacitor (51
2) Charge accumulation occurs, and if the level is low, the charge accumulation does not occur. Therefore, information at the time of nonvolatile operation is written as volatile storage.

As described above, the switching of the operation mode can be performed by rewriting the information before the switching as the information in the mode after the switching.

In the above description, the plate line drive unit (534) supplies the high-low binary level potential, but only the high level supply, and instead, the plate line switching drive unit (533)
Therefore, the switching element (532) is turned ON only when a high-level potential is supplied, and otherwise the switching element (531) is turned ON to supply a Vss level potential so that the plate line switching line (DC51) ( The configuration may be such that the potential state of the DC 52) is controlled.

Although the above description is only for one memory cell,
In an actual element, a large number of memories in the column (a) are sequentially selected and driven under the control of the word line driving section (52), and a large number of columns are sequentially selected and driven under the control of the column selection means (57). Will do.

Embodiment 3 FIG. 7 is a circuit diagram showing an embodiment of the present invention.

In the present embodiment, unlike the first and second embodiments, the ferroelectric capacitor is not provided in the reference portion, and instead, the capacitor of the memory cell is constituted by two ferroelectric capacitors having the same characteristics. In the non-volatile operation, a method of changing the polarization direction complementarily is adopted.

One memory cell (71) basically includes ferroelectric capacitors (712) and (714) and switching elements (711) and (713) connected to each of them. One electrode of the ferroelectric capacitor (712) is connected to the bit line (BLa) via the switching element (711), and the ferroelectric capacitor (712) set to have the same characteristics as the ferroelectric capacitor (712). 714) is connected to the bit line (BLa ') via the switching element (713). The switching elements (711) and (713) are connected to the word line (WL71) and are driven by the word line driving section (72). The other electrodes of the ferroelectric capacitors (712) and (714) are connected to the plate line control means (73) via the plate line (PL71). This plate line (PL71) is connected to the plate line switching drive (73
3) The signal is supplied from the plate line switching line (DC71) to the Vss level through the switching element (731) driven by the plate line switching line (DC72), and the plate through the switching element (732) driven by the plate line switching line (DC72). Line drive (7
Connected to 34).

One end of the bit line pair (BLa) (BLa ') is connected to the sense amplifier (76), and the other end is connected to the data input / output lines (I / I / I) via the switching elements (771) and (772) of the column selection means (77). O) (I / O '), and further connected to a data input / output unit (78). The column selecting means (77) includes the switching elements (771) and (772) and a column selection line driving unit (773) for driving the switching elements. Bit line pair (BLa)
(BLa ′) are connected to the Vcc level via switching elements (SW71) and (SW72) driven by a precharge line (PC) that supplies a signal from the precharge drive unit (75). The bit line pair is connected via a switching element (SW73) driven by a precharge line (PC).

On the basis of the above configuration, one memory cell is connected to one sense amplifier to form one column (a).

Next, the operation of this embodiment will be described with reference to a timing chart (FIG. 8).

(1) Volatile operation mode In this mode, a state where electric charge is accumulated in the ferroelectric capacitor (712) is set to “1”, and a state where electric charge is not accumulated is set to “0”. Charge storage in the ferroelectric capacitor (712) is performed by applying a unidirectional electric field without polarization inversion. Further, the ferroelectric capacitors (714) forming a pair are set so that the charge storage state changes complementarily.

(A) Write operation In the standby state, the precharge line (PC) is in the high level state, and the bit line pair (BLa) (BLa ') is kept at the Vcc level. For the plate line (PL71), the plate line switching drive unit (733) outputs a signal for setting the plate line switching line (DC71) to a high level, and this signal is used to switch the switching element (73).
1) is set to ON and connected to the Vss level.

When the chip enable signal (CE) is input from the outside, the chip is activated and the precharge line (PC) is at a low level, so that the bit line pair (BLa) (BLa ')
Floating state at Vcc level. According to the content of the address signal of the memory cell and the designation of the operation mode, for example, the word line (WL71) goes high, the switching elements (711) and (713) are turned on, and the ferroelectric capacitor (712) and the ferroelectric capacitor (714) are connected to the bit lines (BLa) (BLa '), respectively. The potential of the bit line drops according to the charge storage state of the ferroelectric capacitors (712) and (714). Subsequently, by activating the sense amplifier (76), the potentials of the bit lines (BLa) and (BLa ') are determined complementarily to high and low levels.

For example, in the "1" state, ferroelectric capacitor (712)
Since the electric charge is accumulated in the bit line (BLa), the potential drop of the bit line (BLa) is small. In contrast, ferroelectric capacitors (71
4) does not accumulate electric charge because it operates complementarily with the ferroelectric capacitor (712) with respect to the charge accumulation state, and the potential of the bit line (BLa ') on the ferroelectric capacitor (714) side is higher. Bit line (BLa) on ferroelectric capacitor (712) side
The bit line (BLa) is set to a high level and the bit line (BLa ') is set to a low level.

On the other hand, in the "0" state, no electric charge is stored in the ferroelectric capacitor (712), and conversely, electric charge is stored in the ferroelectric capacitor (714). Therefore, the potential decrease of the bit line (BLa ') due to the charge inflow is smaller than the potential decrease of the bit line (BLa). Therefore, the bit line (BL
a ′) is set to a high level, and the bit line (BLa) is set to a low level.

After that, the column selection line driver (773) drives the column selection line (CSLa) to a high level, the switching elements (771) and (772) are turned on, and the data input / output lines (I /
O) (I / O '). Here, the data input / output line (I /
The bit lines (BLa) and (BLa ') are forcibly rewritten to the setting states of O) and (I / O'). Therefore, data input / output lines (I / O)
Is high level, charges are stored in the ferroelectric capacitor (712). If the data input / output line (I / O) is low level, no charges are stored, and "1" and "0" respectively. "The state will be remembered.

The return to the precharge state is started when the chip enable signal (CE) returns to the high level, and each drive unit sets the word line (WL71) and the column selection line (CSLa) to the low level. And the switching elements (711), (713), (771), and (772) are turned off, and then the precharge driver (75) issues a signal so that the precharge line (PC) is set to a high level. End the operation.

When the next operation is continuously performed, the operation may be continued without performing the operation of returning to the precharge state.

In the above description, writing is performed after the potential of the bit line pair is once determined. However, writing from the data input / output line may be performed without waiting for the determination.

(B) Read operation The operation up to the determination of the potential of the bit line pair is the same as (a) the write operation. After that, a high level signal is output from the column selection line drive unit (773) to the column selection line (CSLa), the switching elements (771) and (772) are turned on, and the information determined by the sense amplifier (76) is input / output data. Line (I / O) (I
/ O ').

The return to the precharge state is similar to (a) the write operation.

(2) Nonvolatile operation mode In this mode, data is stored in the polarization direction of the ferroelectric capacitor (712). When the polarization is oriented in the direction of the plate line (PL31), it is set to "1", and when it is oriented to the bit line (BLa '), it is set to "0".

(A) Write operation In the standby state, the bit line pair (BLa) (BLa ') is kept at the Vcc level, as in the volatile operation. Plate line (PL71) is a plate line switching driver (733)
However, a signal for setting the plate line switching line (DC72) to a high level is output, and the switching element (732) is turned on to be set so as to be connected to the plate line driving unit (734). Initially, a low level (Vss) signal is supplied to the plate line (PL31).

When the chip enable signal (CE) is input from the outside, the chip is activated and the precharge line (PC) is at a low level, so that the bit line pair (BLa) (BLa ')
Floating state at Vcc level. According to the contents of the address signal of the memory cell and the designation of the operation mode, for example, the word line (WL71) becomes high level, the switching elements (711) and (713) are turned on, and the ferroelectric capacitors (712) and (714) Each bit line (BLa) (BLa ')
Connected to. Accordingly, the potential of the bit line decreases. Subsequently, by activating the sense amplifier (36), the potentials of the bit lines (BLa) (BLa ') are complementarily determined to be high and low.

For example, in the "1" state, ferroelectric capacitor (712)
Are polarized in the direction of the plate line (PL71). That is, the bit line (BLa) is polarized to a high potential state. Therefore, even if the bit line (BLa) in the floating state at the Vcc level is connected, it has the same polarity as the polarization polarity, so that there is only charge inflow for the capacity (Cm) as a capacitor. On the other hand, since the ferroelectric capacitor (714) is polarized in the opposite polarity to the ferroelectric capacitor (712), V
Polarization inversion is caused by being connected to the cc-level bit line capacitance (BLa '), and a large amount of charge flows in with this. Therefore, the bit line (BL) on the ferroelectric capacitor (714) side
The potential drop in a ′) is larger, and the sense amplifier (76) sets the bit line (BLa) to a high level and the bit line (BLa ′)
To a low level.

On the other hand, in the "0" state, the ferroelectric capacitor (712) is polarized in the direction of the bit line (BLa). Therefore, when the floating bit line (BLa) at the Vcc level is connected, an electric field having the opposite polarization polarity is generated in the ferroelectric capacitor (71).
2), polarization inversion occurs. As a result, a large amount of charge flows in, and a ferroelectric capacitor (712)
The potential drop of the bit line (BLa) on the side is larger, and the sense amplifier (76) sets the bit line (BLa ') to a high level.
The bit line (BLa) is set to a low level.

After that, the column selection line driver (773) drives the column selection line (CSLa) to a high level, the switching elements (771) and (772) are turned on, and the data input / output lines (I /
O) (I / O '). Here, the data input / output line (I /
The bit lines (BLa) and (BLa ') are forcibly rewritten to the setting states of O) and (I / O'). Plate wire (BL71) as described above
Is initially set to a low level, so when the data input / output line (I / O) is at a high level, the ferroelectric capacitor (712)
Is the polarization direction of the “1” state. Data input / output line (I / O)
Is low, both ends of the ferroelectric capacitor (712) are at low level, so that no polarization inversion occurs. At this time, by supplying a potential of Vcc level from the plate line drive unit (734), the storage state of the ferroelectric capacitor (712) is the polarization direction of the "1" state, so that a voltage of the opposite polarity is applied. And the polarization inversion occurs, and the polarization direction becomes the “0” state.

The return to the precharge state is started when the chip enable signal (CE) returns to the high level, and the respective driving units set the signal so that the word line (WL731) and the column selection line (CSLa) are set to the low level. And the switching elements (711) (713) (771) (772) are turned off.
Thereafter, the precharge driver (75) issues a signal so as to set the precharge line (PC) to a high level, and a series of write operations is completed.

When the next operation is continuously performed, the operation may be continued without performing the operation of returning to the precharge state.

In the above description, writing is performed after the potential of the bit line pair is once determined. However, writing from the data input / output line may be performed without waiting for the determination.

(B) Read operation The operation up to the determination of the potential of the bit line pair is the same as (a) the write operation. After that, a high level signal is output from the column selection line drive unit (773) to the column selection line (CSLa), the switching elements (771) and (772) are turned on, and the information determined by the sense amplifier (76) is input / output data. Line (I / O) (I
/ O ').

The return to the precharge state is similar to (a) the write operation.

 Next, switching of the operation mode will be described.

(3) Volatile operation → Nonvolatile operation The above-mentioned (1) volatile operation mode (b) read operation is performed to determine the potential level of the bit line pair (BLa) (BLa ′). Ferroelectric capacitor (712) if "1"
The bit line (BLa) on the reference capacitor (741) side is determined to be at a high potential if the bit line (BLa) on the side is at a high potential and in the "0" state.

Next, a signal for setting the plate switching line (DC71) to a low level and the plate switching line (DC72) to a high level from the plate line switching driving unit (733) is output, and the switching element (731) is turned off. Is turned ON, the plate line (PL71) is connected to the plate line drive (73
4) Connect. This switches to the non-volatile operation mode. At this time, nonvolatile storage can be performed by the determined potential of the bit line.

That is, in the non-volatile operation mode, the plate line (PL71)
Is initially set to a low level, and when "1", the bit line (BLa) is at a high level, and the polarization direction is in the "1" state. Even when the potential at the Vcc level is subsequently supplied from the plate line driving unit, the potential at both ends of the ferroelectric capacitor only becomes equal, the polarization state does not change, and the "1" state is maintained. Conversely, when it is "0", the bit line (BLa) is at a low level, and both ends of the ferroelectric capacitor (712) are at a low level, so that no polarization inversion occurs. At this time, by supplying a Vcc level potential from the plate line driving unit (734),
The ferroelectric capacitor (712) is applied with a voltage having a polarity opposite to that of the polarization, so that a polarization inversion occurs and the polarization direction becomes the “0” state.

(4) Non-volatile operation → volatile operation The above-mentioned (2) Non-volatile operation mode (b) Read operation is performed to determine the potential level of the bit line pair (BLa) (BLa '). Ferroelectric capacitor (712) if "1"
The bit line (BLa) on the side of the ferroelectric capacitor (714) is fixed at a high potential if the bit line (BLa) on the side is at a high potential and in the "0" state.

Next, a signal for setting the plate switching line (DC72) to a low level and the plate switching line (DC71) to a high level from the plate line switching driving unit (733) is output, and the switching element (732) is turned off. Is turned on to connect the plate line (PL71) to the Vss level.
This switches to the volatile operation mode. Therefore, writing can be performed in the same manner as (a) writing operation in the above-mentioned (2) volatile operation mode. That is, if the bit line (BLa) is at a high level, the ferroelectric capacitor (71
2) Charge accumulation occurs, and if the level is low, the charge accumulation does not occur. Therefore, information at the time of nonvolatile operation is written as volatile storage.

As described above, the switching of the operation mode can be performed by rewriting the information before the switching as the information in the mode after the switching.

In the above description, the plate line driving section (734) supplies the high-low binary level potential. However, it supplies only the high level, and instead, the plate line switching driving section (733).
Therefore, the switching element (732) is turned ON only when a high-level potential is supplied, and the switching element (731) is turned ON otherwise to supply a Vss level potential. The configuration may be such that the potential state of the DC 72) is controlled.

Although the above description is only for one memory cell,
In an actual device, a large number of memories in the column (a) are sequentially selected and driven under the control of the word line driving section (72), and a large number of columns are sequentially selected and driven under the control of the column selection means (77). Will do.

In the above embodiment, the operation mode can be switched by appropriately inputting an external signal. In addition, CP
U can be set to supply a switching signal.
For example, the switching from the non-volatile operation to the volatile operation may be performed by first starting up from the non-volatile operation when the power is turned on, and then changing to the volatile operation. The switching from the volatile operation to the nonvolatile operation is required when the power is turned off or when the power is unintentionally turned off. At this time, the operation mode may be switched.

FIG. 9 shows an example of a power supply detection circuit for generating a switching signal.

The voltage supplied from the power line (901) is
02) is stepped down, full-wave rectified by a rectifier circuit (903), wave-shaped to a constant voltage by a diode (905) via a resistor (904), and charges a capacitor (907) via a resistor (906). . The capacitor (907) is connected to the inverter (908), and a signal is output from the inverter (908) according to the terminal voltage of the capacitor (907). In addition, the output signal of the inverter (908) is
9) and outputs a signal of the opposite logic to the inverter (908). The inverter power supply terminal (910) is connected to the inverter (90
8) Connected to (909), this voltage is the capacitor (911)
Backed up by

Here, when the voltage of the power supply line (901) drops, the electric charge accumulated in the capacitor (907) is discharged through the resistor (912), and as a result, the terminal voltage of the capacitor (907) decreases. Therefore, a power-off signal is output from the inverter (908) as positive logic (I). The inverter (90
From 9), a power-off signal is output as negative logic (I). These output signals can also be used as detection signals at power-on.

FIG. 10 shows an example of a backup circuit for backing up the power when the power is turned off.

The DC voltage input section (101) is connected to a voltage supply terminal (103) connected to the semiconductor memory device via the rectifier (102). A backup power supply (104), for example, a rectifier (105) such as a battery or a capacitor, and a resistor (106) connected in parallel to the rectifier (105) are connected to the DC voltage input unit (101). When the voltage supply from the DC voltage supply unit (101) stops, the backup power supply (104)
Thus, a voltage is supplied to the voltage supply terminal (103).

In the semiconductor memory device of the present invention, for example, FIG.
Using the circuit shown in FIG. 10, when power is turned on, a signal indicating power-on is received from the circuit as shown in FIG. 9, information is read out in a nonvolatile operation, and the operation shifts to a volatile operation. When the power is turned off, the operation immediately shifts from the volatile operation to the non-volatile operation in response to the signal indicating the power-off, writes the volatile information to the non-volatile information under the backup power supply, and stores the information in the non-volatile state. Therefore, the operation is normally a volatile operation, and the operation is a volatile operation when the power is turned off. Thus, the memory can be substantially used as a non-volatile memory in spite of a DRAM-like memory.

The following experiment was performed to confirm the improvement of the life.
As shown in FIG. 11, the measuring device includes a ferroelectric capacitor (111), a current detecting resistor (112), a pulse generator (113), and an impedance matching resistor (114). A ferroelectric capacitor is composed of a Pb (Zr, Ti) O ₃ -based material and polarization inversion is generated by the pulse pattern shown in FIG. 12, and polarization inversion is generated by the pulse pattern shown in FIG. no case (period T, the pulse width W FIG. 12 and identical) to change for Pr, based on the Pr ⁽¹⁰⁵⁾ upon application of a voltage pulse 10 ⁵ times, shown by the Pr / Pr (10 ⁵⁾ FIG. 14 is a diagram. The remanent polarization (Pr) is calculated from the polarization inversion charge amount (Qr) and the polarization non-inversion charge amount (Qn) as follows: Pr = (Qr−Q
n) It was determined from the relationship of / 2. As is clear from FIG. 14, in the case without polarization reversal (A), even after the application of 10 ¹³ pulses
When there is almost no decrease in Pr, but with polarization reversal (B)
It can be seen that the decrease in Pr is remarkable after 10 ¹² pulse applications.

The volatile operation of the present invention corresponds to FIG. 14 (A), and the non-volatile operation corresponds to FIG. 14 (B). Therefore, usually (A)
By using the non-volatile operation only when necessary, the life of the non-volatile storage device can be substantially improved.

[Effects of the Invention] As described above, according to the present invention, the problem of short life of a semiconductor memory device using a ferroelectric capacitor is solved, and a long life is obtained while taking advantage of the nonvolatile storage of a ferroelectric capacitor. In addition, it is possible to obtain a semiconductor memory device which has a high writing / reading speed and can be highly integrated. Therefore, it is very large to contribute industrially.

[Brief description of the drawings]

FIG. 1 is a characteristic curve diagram of a ferroelectric capacitor, FIG. 2 is a circuit diagram illustrating the basic operation of the present invention, and FIGS. 3, 5, 7, 9, and 10 are diagrams of the present invention. FIG. 4, FIG. 6, FIG. 8 are timing charts for explaining the embodiment of the present invention, FIG. 11 is a circuit diagram, FIG. 12, and FIG. FIG. 14 is a pulse diagram, and FIG.

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Hiroshi Toyoda 70 Yanagimachi, Yuki-ku, Kawasaki-shi, Kanagawa Prefecture Inside the Toshiba Yanagicho Plant (72) Inventor Mitsuo Harada 70 Yanagimachi, Yuki-ku, Kawasaki-shi, Kanagawa Toshiba Corporation Inside the Yanagimachi Plant (72) Inventor Koji Sakui 1st Toshiba-cho, Komukai-ku, Kawasaki-shi, Kanagawa Prefecture Within Toshiba Research Institute, Inc. (56) References JP-A-3-5996 (JP, A) JP-A-3-16097 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11C 11 /twenty two

Claims (3)

(57) [Claims] 1. A ferroelectric capacitor; a switching element connected to one electrode of the ferroelectric capacitor; and a voltage applied to the ferroelectric capacitor connected to the other electrode of the ferroelectric capacitor. A first voltage application unit for controlling a voltage and applying a voltage that does not change the polarization direction of the ferroelectric capacitor regardless of stored information, and a second voltage application unit that applies a voltage that can change the polarization direction of the ferroelectric capacitor. A voltage supply means for selecting one of the voltage application means; and a capacity set such that when the first voltage application means is selected, a smaller amount of charge flows than the charge flowing into the ferroelectric capacitor. (1) a reference capacitor; and (b) when the second voltage applying means is selected, the amount of charge is smaller than the amount of charge that flows when polarization inversion occurs in the ferroelectric capacitor. A second reference capacitor having a capacity set so that a current larger than the amount of charge flowing when no inversion occurs; a sense amplifier connected to the first and second reference capacitors and the ferroelectric capacitor When the voltage supply means selects the first voltage application means, selects the first reference capacitor; and when selecting the second voltage application means, selects the second reference capacitor. And a reference capacitor selecting means connected to the sense amplifier. 2. A ferroelectric capacitor; a switching element connected to one electrode of the ferroelectric capacitor; and a voltage applied to the ferroelectric capacitor connected to the other electrode of the ferroelectric capacitor. A first voltage application unit for controlling a voltage and applying a voltage that does not change the polarization direction of the ferroelectric capacitor regardless of stored information, and a second voltage application unit that applies a voltage that can change the polarization direction of the ferroelectric capacitor. A voltage supply means for selecting one of the voltage application means; a reference capacitor; a sense amplifier connected to the ferroelectric capacitor and the reference capacitor; When a charge smaller than the charge amount flowing into the ferroelectric capacitor flows into the reference capacitor and the second voltage applying means is selected, the ferroelectric The amount of charge charged to the reference capacitor is controlled such that a smaller amount of charge flows when the polarization inversion occurs in the capacitor and a larger amount of charge flows than the amount of charge flowing when the polarization inversion does not occur. A semiconductor memory device comprising: a reference capacitor selecting unit. 3. The ferroelectric capacitor and the reference capacitor are connected to the sense amplifier via a bit line pair.
The degree of voltage drop caused by the charge flowing into the ferroelectric capacitor and the reference capacitor is amplified by the sense amplifier, and the storage state of the ferroelectric capacitor is read based on the level of the potential of the bit line pair. The semiconductor memory device according to claim 1.