JPH035996A - Nonvolatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To improve the limit of a reading time by using the operation mode of a non-volatile semiconductor memory device separately to a mode to execute volatile operation like a DRAM and a mode to execute non-volatile memory operation. CONSTITUTION:When the output level of a word line WL, which is connected to the gates of transistors Q1 and Q2, or the output level of a drive line DL connected to the capacitor of a ferroelectrics is changed, a potential to be applied to capacitors C1 and C2 is changed. When a high voltage is applied to the capacitors C1 and C2, the ferroelectrics is polarized and the non-volatile memory of data is executed samely as conventional operation. When a low voltage in a degree not to polarize the ferroelectrics is applied to the capacitors C1 and C2, the volatile memory of the data is executed according to the presence and absence of an electric charge which is charged to the capacitors C1 and C2. Accordingly, when it is set to execute the volatile memory at the time of normal data memory operation, the reading time of the data is regardless of the fatigue of the ferroelectrics. Thus, the limit of the reading time can be widely improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application] The present invention relates to a nonvolatile semiconductor memory device including a plurality of memory cells each having a transistor and a capacitor formed of a ferroelectric material.

[Conventional technology]

FIG. 5 shows rE1 electronics+ Feb, 18.
This is a block diagram of a conventional nonvolatile semiconductor memory device published in 1988, page 94 J, and 1 in the figure indicates one of a large number of memory cells. The memory cell 1 is composed of four elements, each consisting of two selection transistors Ql and Q2 and capacitances C1 and C2 formed of ferroelectric material, and the transistors Q1. The drain of Q2 is the bit line BL connected to the sense amplifier 2 and the power supply, respectively.

They are each connected to the inverted bit line BL. Further, the transistor Q1. The respective gates of transistors Q2 are both connected to the word line tag which is the output signal line of the row decoder 4, and the gates of the transistors Q1. Each source of Q2 is connected to one electrode of capacitors C1 and C2, respectively.

The other electrodes of the capacitors C1 and C2 are connected to the drive line ILL, which is the output signal line of the drive line decoder 5.

The row decoder 4. The drive line decoders 5 each have
An address signal output from address buffer 6 is input, and based on the address signal, row decoder 4 selects a predetermined word line hole, and drive line decoder 5 selects a predetermined drive line DL. Note that the output timing of the address signal is controlled by a signal output from the control signal manual buffer 7. Further, the control signal outputted from the control signal human power buffer 7 is input to the sense timing generation circuit 8 and the human output buffer 3, respectively, and based on the control signal (the clock signal is output from the sense timing generation circuit 8 to the sense amplifier 2), While the clock signal is at high level, the sense amplifier 2
A potential difference between the bit line BL and the inverted bit line BL is detected, and the human output buffer 3 takes in the detection signal based on the control signal.

Next, each of the above 11c1. The characteristics of c2 will be explained.

Fig. 6 is a diagram showing the characteristics of capacitances C1 and C2 in Fig. 5. In (a), time is plotted on the horizontal axis, and voltage is plotted on the vertical axis, and in (b) and (C), the horizontal axis is plotted with voltage. The axis is time, and the vertical axis is current. In advance, capacity CI or C
After polarizing the ferroelectric material of capacitor 11c1 or C2 by applying a voltage to the electrode of capacitor tc1 or C2, a constant voltage is applied to capacitor tc1 or C2 for a predetermined time as shown in FIG. 6(a). If the direction of this voltage is the same as the direction of the voltage applied at the time of polarization, that is, if it is different from the direction of polarization of capacitor 1ic1 or C2, the current will flow to charge capacitor C1 or C2 as shown in (c). Flow into. On the other hand, when the stepwise applied voltage is in the same direction as the polarization, as shown in (C), a current flows to charge the capacitor IcI or C2, and a current flows to reverse the polarization. That is, when a voltage is applied to the capacitor ICI or C2 formed of a ferroelectric material, the manner in which the flowing current changes over time differs depending on the polarization direction of the capacitor C1 or C2.

Next, the operation of this nonvolatile semiconductor memory device will be explained.

FIGS. 7 and 8 are explanatory diagrams showing the operation of writing data to a memory cell.

First, the bit line BL is set to high level, and the inverted bit, W
BL is set to low level, and a predetermined drive line OL and word line hole selected based on the address signal are set to high level. As a result, the capacitor 1jlc2 connected to the inverted bit line ■ is polarized in the direction shown by the arrow, that is, in the direction from the electrode of the capacitor C2 connected to the source of the transistor [12] to the electrode connected to the drive line DL. (Figure 7).

Next, when the drive line DL is set to a low level, the capacitor C1 connected to the bit line BL is polarized in the direction from the electrode connected to the drive line DL to the electrode connected to the transistor Q1, that is, in the opposite direction to the capacitor MC2. (Figure 8). In this way, Yong-Ic1. A data ladder 1' is written into the memory cell 1 by polarizing C2 in the direction shown in FIG. Furthermore, by setting the inverted bit line disturbance to high level and setting bit iBL to low level, the capacitors C1 and C2 are polarized in the directions opposite to those shown in FIG. 8, thereby writing data "0" into memory cell 1. It will be done.

FIGS. 9 to 12 are explanatory diagrams showing the operation of sequentially outputting data from memory cells.

When reading the data "1" written in the memory cell 1 as described above, first precharge the bit line BL and the inverted bit line BL with a predetermined voltage, and then charge the selected drive based on the address signal. Set the line opening to low level and the word line hole to high level (Figure 9). As a result, a current that charges the capacitors C1 and C2 flows into the memory cell 1, but the direction of the applied voltage is
Since the direction of polarization is the same as that of capacitor 2, as shown in FIG. 6(C), a larger current flows into capacitor tc2 than capacitor C1.

Therefore, the potential (0■) of the inverted bit line [is the bit line BL
(FIG. 10), and this potential difference is detected by the sense amplifier 2 and amplified to perform reading.

By this reading, the polarization direction of the capacitor IC 2 at the time of writing is reversed as shown in FIG. 10.

Therefore, the drive line DL is set to a high level to return the direction of polarization of the capacitor C2 to the same direction as when writing.
If the polarization of is strengthened (Fig. 12), the original state is restored, that is,
Data “■” is restored to the state written in memory cell 1.

[Problem to be solved by the invention]

As described above, in the conventional nonvolatile semiconductor memory device, data is read by inverting the polarization of any capacitor within the memory cell, which is a so-called destructive read. The number of times a capacitor formed of ferroelectric material can be polarized is 109 to 1012.
Therefore, the number of readings is limited to 10'' to 10'2.
There was a problem that it could only be done once.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to enable a nonvolatile semiconductor memory device to be used in two modes: a volatile operation mode like a DRAM, and a nonvolatile memory operation mode. Therefore, an object of the present invention is to provide a nonvolatile semiconductor memory device that can significantly improve the limit on the number of reads.

[Means to solve the problem]

A nonvolatile semiconductor memory device according to the present invention changes the output level of a word line connected to the gate of a transistor or a drive line connected to a ferroelectric capacitor, and changes the output level of a word line connected to a gate of a transistor or a drive line connected to a ferroelectric capacitor, Volatile memory without polarization is selected.

[Effect]

In the nonvolatile semiconductor memory device of the present invention, when the output level of the word line connected to the gate of the transistor or the drive line connected to the ferroelectric capacitor is changed,
The potential applied to the capacitor changes. When a high voltage is applied to the capacitor, the ferroelectric material becomes polarized, resulting in non-volatile storage of data similar to conventional methods, and when a low voltage is applied to the capacitor, which does not cause polarization of the ferroelectric material, the capacitor is charged. Data is stored in a volatile manner depending on the presence or absence of charge.

[Examples] Hereinafter, the present invention will be specifically described in detail based on drawings showing examples thereof.

FIG. 1 is a block diagram of a nonvolatile semiconductor memory device according to the present invention, and in the figure, 1 indicates one of a large number of memory cells. The memory cells 1 each include two selection transistors (11, Q2 and capacitances CL, C2 formed of ferroelectric materials).
The transistor Q1.
The drain of Q2 is connected to the sense amplifier 2 and the power supply line BL, respectively.

(inverted bit line tag) each connected separately. Further, the transistor Ω1. Each gate of transistor Q2 is connected to a word line hole, which is an output signal line of row decoder 4, via an output switching section 10, and the transistor Q1.

Each source of 02 has a capacity c1. They are each connected to one electrode of c2. And each ic1. The other electrode of c2 is connected to the drive line OL, which is the output signal line of the drive line decoder 5.

The row decoder 4. The drive line decoders 5 each have
An address signal output from address buffer 6 is input, and based on the address signal, row decoder 4 selects a predetermined word line hole, and drive line decoder 5 selects a predetermined drive line DL. Note that the output timing of the address signal is controlled by a signal output from the control signal carrier 7.

Further, the control signal output from the control signal input buffer 7 is input to the mode changeover switch 9, and the mode changeover switch 9 is turned on and off in accordance with this control signal.
An output switching unit 10 that switches the RAM enable signal OE to high level or low level and is connected to the row decoder 4.
and the drive line decoder 5, respectively.

Further, the control signal is input to the sense timing generation circuit 8 and the human output buffer 3, respectively, and a clock signal based on the control signal is provided from the sense timing generation circuit 8 to the sense amplifier 2. While the clock signal is at a high level, the sense amplifier 2 connects the bit lines BL,
The potential difference of the inverted bit line disturbance is detected, and the human output buffer 3 takes in the detection signal based on the control signal.

FIG. 2 is a circuit diagram of the output switching section 10 in FIG. The n-channel transistor q6 is connected to the ground through the series connection, and the power supply voltage V
A voltage Vref that is lower than cc and does not cause polarization of the ferroelectric material of capacitors C1 and C2 is applied to p-channel transistor Q4 and transistor RO5. The structure is grounded via Q6.

The gate of the transistor Q3 is supplied with the signal DE output from the mode changeover switch 9, the gate of the transistor Q4 is supplied with the signal DH which is an inverted version of the signal DE, and the gates of the transistors Q5 and Q6 are supplied with the signal DE output from the mode changeover switch 9. Output is given.

When the signal DB is at a low level, the transistor (
13 is turned on, the transistor Q5 is turned on by the operation of the row decoder 4 based on the address signal, and the power supply voltage Vcc is output to the selected word line hole.

Then, the drive line D selected by the drive line decoder 5
L becomes a high level or a low level according to write and read operations, which will be described later, and nonvolatile storage of data is performed by polarization of the ferroelectric material. That is, to write data "1" to the memory cell 1, first, as shown in FIG. The predetermined drive line DL is set to high level, and the word line hole is set to the power supply voltage Vcc. As a result, the inverted bit line B
The capacitor IC2 connected to the transistor I is polarized in the direction shown by the arrow, that is, in the direction from the electrode of the capacitor C2 connected to the source of the transistor I2 to the electrode connected to the drive line DL.

Next, as shown in FIG. 8, when the drive line OL is set to a low level, the capacitor C1 connected to the bit line BL moves in the direction from the electrode connected to the drive line DL to the electrode connected to the transistor RO1, that is, the capacitor C1 connects to the bit line BL. Polarized in the opposite direction to C2. In this way, by polarizing the capacitor IC2 in the direction shown in FIG. 8, data "1" is written into the memory cell 1. In addition, the inverted bit line ``out'' is set to high level and the bit line BL is set to low level.
, C2 in directions opposite to those shown in FIG. 8, data "O#" is written into the memory cell 1.

When the data "1" written in the memory cell 1 is to be successively written as described above, the bit line BL and the inverted bit line BL are first precharged, respectively, as shown in FIG. Drive line OL to low level,
Further, the word line hole is set to the power supply voltage Vcc. As a result, a current that charges the capacitors CI and C2 flows into the memory cell 1, but since the direction of the applied voltage is the same as the polarization direction of the capacitor C2, as described above, the capacitor C2
More current flows into the capacitor C1 than the capacitor C1. Therefore, the first
As shown in FIG. 0, the potential (OV) of the inverted bit line BL becomes lower than the potential (5V) of the bit line BL, and this potential difference is detected by the sense amplifier 2 and amplified to perform continuous output.

Note that by this reading, the direction of polarization of the capacitor C2 during writing is reversed as shown in FIG. 10. Therefore, by setting the drive line DL to a high level and returning the direction of polarization of the capacitor C2 to the same direction as when writing (Fig. 11), furthermore, by setting the drive line DL to a low level to strengthen the polarization of the capacitor IC1 (Fig. 11). (FIG. 12), the original state is restored again, that is, the state in which data "1" was written in the memory cell 1.

As described above, the nonvolatile memory of the present invention is performed in the same manner as the conventional nonvolatile memory described above.

On the other hand, when the signal DE input to the output switching unit 10 is at the 71 level, the inverted signal surface becomes the low level and the transistor Q4 is turned on, and the word line hole selected in accordance with the address signal is A voltage Vref lower than the power supply voltage Vcc is output. This voltage Vref is applied to the gates of transistors Ql and Q2 in memory cell 1 via selected word line WL. Drive'+M
Fix oL to low level and set Bi-not-line BL to 5■
When the inverted bit line ■ is set to 0■, the transistor Q
While transistor 2 is turned off, a potential appears at the source of transistor 01. This potential becomes 3■ when the voltage Vref is 3■ and the dark value of the transistor 01 is 1■, and this potential is added to the capacitance 1ct. Therefore, in this case, the capacitor IcI, which is polarized by the application of 5V, does not cause polarization.

And ic1. If the capacitance of C2 is C, a charge of 3C is accumulated only in the capacitor C1, and data "1" is written. Also, Bi NodojFQBL is 0■
If the inverted bit/node line (2) is set to 5 (5), a charge of 3C is accumulated only in the capacitor C2, and data "0" is written.

The reading of the data written in this memory cell 1 is as follows:
This is performed by detecting the potentials of f1c1 and C2 with the sense amplifier 2.

In this way, the mode selector switch 9 is used to switch between a nonvolatile storage mode that involves polarization of the ferroelectric material in the capacitor and a DRAM mode that is a volatile mode that performs storage using only the charge accumulated in the capacitor without polarization. If you set it up and set it to operate as a DRAM during normal data storage operations,
The number of data readouts is independent of the fatigue of the ferroelectric material,
The limit on the number of reads is improved.

Next, other embodiments of the present invention will be described.

FIG. 3 is a block diagram showing another nonvolatile semiconductor memory device according to the present invention, in which the output from the drive line decoder 5 is switched in place of the output switching section 10 connected to the row decoder 4 in FIG. An output switching section 11 is provided. The sources of the transistors Q2 and Q2 in the memory cell I are individually connected to one electrode of the capacitor 1cLc2, and the other electrode of each of the transistors [C1 and C2 is connected to the drive line OL, which is the output signal line of the drive line decoder 5. They are connected via an output switching section 11.

Also, row decoder 4. An address signal output from an address buffer 6 is input to each drive line decoder 5 via an address counter 12. The address counter 12 receives the signal DE output from the mode changeover switch 9 and a signal for controlling data transfer, and the address counter 12 receives the address signal only when the signal for controlling data transfer is supplied. Output.

FIG. 4 is a circuit diagram of the output switching section 11 connected to the drive line decoder of FIG. 3. The output switching unit 11 has one end connected to a power supply with a voltage of 1/2 VCC, the other end connected to a drive line port, a p-channel transistor Q7, one end connected to a drive line decoder 5, and the other end connected to a drive line port. It consists of an n-channel transistor Q8 connected to the port. Transistor Q7. A signal DH, which is an inverted version of the signal DH, is applied to each gate of QB.

When the signal DH output from the mode changeover switch 9 is at a low level, the inverted signal DH becomes a high level, the non-volatile storage mode is entered, the transistor 8 is turned on, and the selected drive line DL is connected to the selected drive line DL. Power supply voltage Vc
c or Ov is applied. The bit line BL is set to high level, the inverted bit line layer is set to low level, and the power supply voltage νcc is applied to the drive line DL and word line WL respectively to polarize the capacitor C2, and then the drive line DL is set to Ov.
When the capacitor C1 is polarized in the opposite direction to the capacitor C2, data "1" is written into the memory cell l. Further, the inverted bit line BL is set to high level, and the bit line BL is set to low level.

By polarizing C2 in the opposite direction to the writing of data "1", data "0" is written into the memory cell E. This provides non-volatile storage of data.

On the other hand, when the signal LE is at a high level, the inverted signal DE becomes a low level, and the DRAM mode is entered.
Transistor Q connected to the selected drive line DL
7 is on, and 1/2 Vc is always applied to the drive line inlet.
A voltage of c is applied. Therefore, for example, when the power supply voltage Vcc is 5■, the selected word line WL
5v is applied to the selected drive line OL, and 2.5v is applied to the selected drive line OL. Then, if bit line B is set to 5V and the inverted bit line layer is set to 0, the capacitance of capacitance CI and C2 is set to C
In this case, a charge of 2.50 is accumulated in the capacitor IC1, and a charge of -2.50 is accumulated in the capacitor C2, resulting in data "1".
” is written, and when the bit line BL is set to OV and the inverted bit line layer is set to 5■, the capacitance C1 becomes - contrary to the above case.
At the same time, a charge of 2.50 is accumulated in the capacitor C2, and data "O#" is written.

Then, reading the data written in memory cell 1 is as follows:
This is done by detecting the potentials of the capacitors C1 and C2 with the sense amplifier 2.

That is, in this case, the potential difference that can be used during the readout is 5
■ Become.

On the other hand, in the nonvolatile semiconductor memory device shown in FIG. 1, when the bit line BL is set to 5V and the inverted bit line is set to O■, a charge of 3C is accumulated only in the capacitor CI.
When data "1" is written, and the bit line BL is set to 0■ and the inverted bit line skin is set to 5■, a charge of 3C is accumulated only in the capacitor C2, and data "O" is written.

Since successive reading is performed in the same manner as in the previous case, the potential difference available for reading is 3. Therefore, the capacitances CI and C2 in the nonvolatile semiconductor memory device shown in FIG.
is a normal DRAM that writes data by applying 5■
573 times the capacitance C is required.

Therefore, if the output level of the drive line port during DRAM operation is maintained at 1/2 Vcc as in this embodiment, the DRAM can operate with the capacity of a normal DRAM, and the capacitance of the memory cell 1 can be reduced. can do.

Although the circuit shown in FIG. 4 is used as the output switching unit 11 in this embodiment, the circuit is not limited to this.

Next, the operation of the address counter 12 will be explained.

As described above, the address counter 12 outputs an address signal only when a signal for controlling the transfer of data output from the mode changeover switch 9 is applied. Note that data transfer here refers to reading desired data that has already been stored in the memory cell 1 in a non-volatile or volatile manner, and converting volatile data to non-volatile or non-volatile data to volatile. This means that the data will be transferred again to memory cell 1 as soon as possible.

When the signal that controls the data transfer input to the address counter 12 is at low level, the nonvolatile semiconductor memory device operates as DRA? ? mode or nonvolatile storage mode, and the address signal output from the address buffer 6 is output from the address counter 12 as is.

Based on this address signal, the row decoder 4 selects a predetermined word line hole, and the drive line decoder 5 selects a predetermined drive line OL, thereby performing nonvolatile or volatile storage as described above.

Furthermore, when the signal controlling data transfer is at high level, the output of the address counter 12 is automatically incremented or decremented, and the output of the address counter 12 is automatically incremented or decremented, and the output of the address counter 12 is automatically incremented or decremented.

The data stored in C2 is sequentially read out by the sense amplifier 2. Then, according to the data, the dry line DLt
- Set to high or low level.31 C1.

By polarizing the ferroelectric material of C2, DRAM
To non-volatilely store data accumulated during mode.

The reverse operation, that is, the operation of storing data accumulated in the non-volatile mode in a volatile manner is also performed.

Note that the address counter 12 also serves as a DRAM refresh counter.

In this way, the address counter 1 operates as a refresh counter during DRAM operation, and operates as an address counter that controls data transfer during data transfer.
By providing 2, data can be easily transferred and the chip area can be reduced. When a high voltage is applied to the capacitor through the word line or the drive line, the ferroelectric material is polarized and the data becomes non-volatile as in the past. Data is stored, and when a low voltage that does not cause polarization of the ferroelectric material is applied to the capacitor, data is stored in a volatile manner depending on the presence or absence of charge in the capacitor.

Therefore, if the data is set to be stored in a volatile manner during normal data storage operations, the number of data reads becomes independent of the fatigue of the ferroelectric material, which has the excellent effect of greatly increasing the limit on the number of reads. .

[Brief explanation of drawings]

FIG. 1 is a block diagram of a nonvolatile semiconductor memory device according to the present invention, FIG. 2 is a circuit diagram of the output switching section in FIG. 1, and FIG. 3 is a block diagram of another nonvolatile semiconductor memory device according to the present invention. , FIG. 4 is a circuit diagram of the output switching section in FIG. 3,
FIG. 5 is a block diagram of a conventional nonvolatile semiconductor memory device.
FIG. 6 is a diagram showing the characteristics of the capacitor i(:1.C2) in FIG. It is an explanatory diagram showing the read operation of data to a memory cell. 1... Memory cell 4... Row decoder 5...
Drive line decoder 9...Mode selection switch
10... Output switching section CI, C2... Capacity Ql
, mouth 2...transistor WL-...word line DL
...Drive line BL...Bit line BL...
- Inverted bit line Note that in the figures, the same reference numerals indicate the same or equivalent parts. Deputy agent: Masuo Oiwa 4 Funeral map BL BL Figure BL BL Figure BL BL Figure BL BL 1 Figure BL BL 0 Figure BL BL 2 Self-motivated to write corrections for illustration procedure)

Claims (1)

[Claims] (1) A capacitor made of ferroelectric material and a transistor connected in series to the capacitor, one end of the capacitor is connected to the drive line that selects the capacitor, and the gate of the transistor is connected to the word line that selects the capacitor. A nonvolatile semiconductor memory device that stores data by selectively applying a voltage to the capacitance based on the output of the word line, comprising means for changing the output level of the word line or the drive line, A nonvolatile semiconductor memory device characterized in that, by the operation of the means, it is possible to select a nonvolatile memory that involves polarization of the ferroelectric material or a volatile memory that does not involve the polarization.