JPH06176589A - Non-volatile semiconductor memory - Google Patents

Abstract

PURPOSE:To prevent use less repetition of polarization inversion of ferroelectric and unexpected shortening of the life time of a memory cell 4 by prohibiting useless recall and store owing to a bug or the runaway of a program or the like. CONSTITUTION:This device is provided with a counter 13 for recall and a counter 15 for store which count the number of times of a series of recall modes and store modes. Further, the device is provided with a first switch circuit 14 and a second switch circuit 16 which prohibit performing control of the recall mode or the store mode when these counted values exceeds the number of times same as the number of word lines WL.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device using a ferroelectric material.

[0002]

2. Description of the Related Art Nonvolatile semiconductor memory device (NVDRAM)
As [Non-Volatile Random Access Memory]), D
RAM [Dynamic RAM] and EEPROM [Electrically
Erasable Programmable Read Only Memory] and the one using ferroelectrics.

A nonvolatile semiconductor memory device in which a DRAM and an EEPROM are combined is described in the following document.

(1) "A New Architecture for the NVDRAM
--- An EEPROM Backed-Up DynamicRAM ", IEEE Journal
of Solid State Circuits, vol.23, No.1, issued February 1988. (2) U.S. Patent No. 4,611,309. (3) "A Versatile Stacked Storage Capacitor on Floa
tox Cell for MegabitNVRAM Applications ", 1989
International Electron Devices Meeting Technical D
igest, IEDM89, Sections 595-598. (4) "A 256k-bit Non-Volatile PSRAM with Page Recal
l and Chip Store ", 1991 Sym. VLSI circuit Dig.
Tech. Papers, May, paragraphs 91-92. This non-volatile semiconductor memory device is normally accessed by DR.
The data is stored in the DRAM and stored in the EEPROM immediately before the power is turned off.
Therefore, it is possible to access the DRAM at high speed during normal operation, and this data can be stored in the nonvolatile EEPROM when the power is off.

A nonvolatile semiconductor memory device using a ferroelectric substance is described in the following document.

(1) "An Experimental 512-bit Nonvlatil
e Memory with Ferroelectric Strage Cell "IEEE Jour
nal of Solit State Circuits, vol.23, pp.1171-1175,
October, 1988. (2) "A Ferroelectroc DRAM Cell for High-Density NV
RAM's ", IEEE ElectronDevice Lett., Vol.11, pp.454-4
56, October, 1990. (3) "Current State and Future of Ferroelectric Memories" Monthly Semiconducto
r World, May 1990, pp.118-125. (4) "A 16kb Ferroelectric Nonvolatile Memory with
a Bit Parrallel Architecture ", ISSCC89, February, 19
89, pp.242-243. Nonvolatile semiconductor memory devices using ferroelectrics are known as PZT [l
The memory cell uses a capacitor element having a ferroelectric thin film having a crystal structure of a perovskite [perovskite type] such as ead zirconate titanate], PLZT or PbTiO ₃ . When an AC voltage is applied to the capacitive element in which the ferroelectric substance is interposed in this manner, the polarization state of the ferroelectric substance is as shown in FIG.
Shows the hysteresis characteristics as shown in. That is, when a positive electric field is applied to the ferroelectric substance at the point A which is not polarized at first, the polarization state moves to the point B, but when this electric field is removed, only the point C is returned and a positive remanent polarization occurs. . Next, when a negative coercive electric field is applied, the polarization finally disappears, and when a further large negative electric field is applied, the polarization state is reversed and the point moves to point D, but when the electric field is removed again, E
It returns only to the point and causes a negative remanent polarization. Then, by reversing the polarization of the ferroelectric substance to generate positive or negative remanent polarization, data can be stored in a nonvolatile manner. Further, in this capacitive element, the polarization state of the ferroelectric substance moves only between the points B and C or between the points D and E when only the operation of applying or removing a positive or negative electric field is performed. Therefore, polarization inversion does not occur, and data can be stored in a volatile manner as in a normal DRAM. Such a nonvolatile semiconductor memory device includes a DRAM and an EEPRO.
Since the number of elements constituting the memory cell can be reduced as compared with the combination of M, there is an advantage that the cell area can be reduced and high integration can be achieved.

A non-volatile semiconductor memory device using a two-transistor / cell type ferroelectric will be described below. As shown in FIG. 9, this non-volatile semiconductor memory device has a large number of word lines WL and corresponding plate lines P.
T, which are connected to the word line decoder 1 and the plate line decoder 2, respectively. In addition, a large number of bit line pairs bit and bit bar are provided, and the sense amplifier 3 is provided for each pair.
It is connected to the. However, in FIG. 9, only one set of this bit line pair bit, bit bar and sense amplifier 3 is shown.

A memory cell 4 is arranged at each intersection where the word line WL and the corresponding plate line PT intersect the bit line pair bit, bit bar.
However, FIG. 9 shows only one memory cell 4. This memory cell 4 comprises two capacitive elements C1, C2 and 2
It is composed of individual selection transistors Q1 and Q2. One terminal of each of the capacitive elements C1 and C2 is a bit line pair bit and bit via a selection transistor Q1 and Q2, respectively.
Is connected to the bar and the other terminal is the plate wire PT
It is connected to the. The gates of the selection transistors Q1 and Q2 are connected to the word line WL.

In the nonvolatile semiconductor memory device having the above structure, the word line decoder 1 and the plate line decoder 2 select one word line WL and the plate line PT based on the address input to the address buffer 5, and the control signal The memory cell 4 is accessed in a mode based on the control signal input to the input buffer 6. That is, in the DRAM mode for accessing volatile data, the DRAM mode timing control circuit 7 controls, and in the recall mode for reading non-volatile data, the recall mode timing control circuit 8 controls for writing non-volatile data. In the store mode to be performed, the access operation is performed under the control of the store mode timing control circuit 9. The data to be accessed is the data I / O interface 10
It is communicated with the outside through.

The data write operation in the store mode in the store mode timing control circuit 9 will be described in detail with reference to FIGS. 10 and 11. For example, when writing data “0”, as shown in FIG. 10, 0V is applied to the bit line bit and 5V is applied to the bit line bit bar.
The voltage pulse that changes from 0V → 5V → 0V is applied to the plate line PT in a state where the voltage is applied and the word line WL is activated. Then, one capacitive element C1
Of the ferroelectric substance, the polarization state is C point or E point → B point → in FIG.
The point C is changed, and the ferroelectric substance of the other capacitive element C2 changes the polarization state as point D → point E → point D. Therefore, even if the voltage is removed thereafter, remanent polarizations at points C and E occur in the ferroelectrics of these capacitive elements C1 and C2, respectively, whereby the data "0" is stored in a nonvolatile manner. Further, when writing data of "1", as shown in FIG. 11, the bit line pair bit, b
Voltages of 5 V and 0 V, which are the opposite of the above, are applied to the it bar.
Then, when a voltage is applied in the same procedure thereafter, remanent polarizations at points E and C, which are opposite to the above, occur in the ferroelectrics of the capacitive elements C1 and C2, respectively. To be done.

Next, the data read operation in the recall mode in the recall mode timing control circuit 8 will be described in detail with reference to FIG. In this case, the bit line pair bit, bit bar is precharged to the potential of 0 V and then opened. Then, when the word line WL is activated and the voltage of the plate line PT is changed from 0V to 5V, when the data of "0" is stored, the polarization state of the ferroelectric substance of one capacitance element C1 is changed. In FIG. 8, the point changes from point C to point B, and the polarization state of the ferroelectric substance of the other capacitive element C2 changes from point E to point B. Then, in the case of the ferroelectric substance of the other capacitive element C2, the polarization state is inverted, so that the potential of the bit line bit bar connected thereto becomes higher by a few hundred mV than the potential of the bit line bit.
Therefore, if the potential difference between the bit line pair bit, bit bar is sensed by the sense amplifier 3, the non-volatile data can be read. However, in this case, the polarization states of the ferroelectrics of the capacitive elements C1 and C2 both move to point B and the non-volatile stored data is lost, so destructive reading is performed.

In this recall mode, bit line pair b
Since the potential difference generated at the it and bit bars is proportional to the remanent polarization and inversely proportional to the bit line capacitance, it can be understood that the larger the remanent polarization and the smaller the bit line capacitance, the larger the potential difference is, which facilitates detection by the sense amplifier 3.

The DRAM mode timing control circuit 7
Access in the DRAM mode at the plate line PT
The same procedure as that of the DRAM is performed with 0 V applied to. Then, the polarization state of the ferroelectric substance in the capacitance elements C1 and C2 moves only between the points D and E in FIG. 8, and the volatility due to the charges accumulated in the capacitance elements C1 and C2 is the same as in a normal DRAM. Can be stored and this data can be read.

[0014]

By the way, the above-mentioned nonvolatile semiconductor memory device using the ferroelectric material can be operated only in the store mode of the nonvolatile memory and the recall mode for reading this data. However, the ferroelectrics used for the capacitive elements C1 and C2 of the memory cell 4 have a limited number of polarization inversions, and the recall / store operation is limited to about 10 ⁹ to 10 ¹² times. Under such a limitation, if the continuous access is performed at a cycle period of about 100 ns (nanosecond), the life of the memory cell 4 will be exhausted within several days.

Therefore, in such a nonvolatile semiconductor memory device using a ferroelectric material, access is performed without polarization inversion in the DRAM mode during normal operation, and the nonvolatile memory is used at power-on and power-off. The access is carried out in the recall mode and the store mode only when it is necessary to minimize the number of accesses involving polarization inversion.

However, in the conventional non-volatile semiconductor memory device, as soon as an access instruction in the recall mode or the store mode is repeatedly issued due to a bug or runaway of a program of a computer device controlling the non-volatile semiconductor memory device, it is promptly issued. There is a problem that the number of times of access is reached and the life of the memory cell 4 may be unexpectedly shortened.

Further, since the access in the recall mode in the conventional nonvolatile semiconductor memory device is the destructive read of the data as described above, if the read data is lost for some reason, this data is no longer stored. There was also the problem of not being able to recover.

Further, in the conventional nonvolatile semiconductor memory device, when the charge of the volatile data is accumulated in the capacitive element when the access is performed in the recall mode, it becomes noise to ensure the reading of the nonvolatile data. There was also the problem of being able to do it.

Further, the conventional nonvolatile semiconductor memory device is
When the so-called 1-transistor / cell method is adopted, the dummy cell provided corresponding to the memory cell configured by one capacitive element cannot be formed in the same shape as the normal memory cell, and therefore, the semiconductor device is manufactured. There was also the problem that it would not be easy.

Further, in the conventional nonvolatile semiconductor memory device, the stored data may be destroyed by the store operation immediately after the power is turned on.

The present invention has been made in view of the above circumstances, and it is possible to predict the life of a memory cell due to program runaway or the like by preventing the recall operation and the store operation from being performed a predetermined number of times or more in succession. It is an object of the present invention to provide a non-volatile semiconductor memory device using a ferroelectric substance that is not shortened.

[0022]

A non-volatile semiconductor memory device of the present invention stores non-volatile data in a memory cell based on the polarization effect of a ferroelectric substance interposed in a capacitive element, and A non-volatile semiconductor memory device that recalls the data by detecting a potential generated according to the polarization state of the ferroelectric substance at the other terminal of the capacitive element when a voltage is applied to the terminal, Counting means for counting the number of times of a series of recall operations and resetting the count value according to a signal from the outside, and means for inhibiting the recall operation when the count value of the counting means exceeds a predetermined value. It is provided, and thereby the above-mentioned object is achieved.

Further, in the non-volatile semiconductor memory device of the present invention, a ferroelectric is interposed in the capacitor element, a voltage corresponding to data is applied to one terminal of the capacitor element, and the other terminal of the capacitor element is applied. A non-volatile semiconductor memory device that stores data by applying a pulse to the terminal of the ferroelectric substance to bring the ferroelectric substance into a polarized state corresponding to the data and counting the number of times of a series of store operations. It is provided with counting means for resetting a numerical value according to a signal from the outside, and means for prohibiting the store operation when the count value of the counting means exceeds a predetermined value, whereby the above object is achieved. It

Further, in the nonvolatile semiconductor memory device of the present invention, nonvolatile data is stored in the memory cell based on the polarization action of the ferroelectric substance interposed in the capacitive element, and the voltage is applied to one terminal of the capacitive element. When the voltage is applied, the data is recalled by detecting the potential generated at the other terminal of the capacitance element according to the polarization state of the ferroelectric substance, and the data is applied to one terminal of the capacitance element. Voltage is applied,
A nonvolatile semiconductor memory device for storing data by applying a pulse to the other terminal of the capacitive element to bring a ferroelectric substance into a polarized state corresponding to data, in which a recall operation is started or ended. When the power is turned on, it may be further provided with a means for canceling the prohibition of the store operation, or may be provided with a means for prohibiting the store operation immediately after the power is turned on. .

Further, in the nonvolatile semiconductor memory device of the present invention, nonvolatile data is stored in the memory cell based on the polarization effect of the ferroelectric substance interposed in the capacitive element, and the first terminal of the capacitive element is stored. A nonvolatile semiconductor memory device that recalls the data by detecting a potential generated according to a polarization state of a ferroelectric substance at the other terminal of the capacitive element when a voltage is applied, the capacitive element Means for discharging the electric charge accumulated in the storage capacitor element before applying the voltage to the first terminal of the above.

Further, the nonvolatile semiconductor memory device of the present invention stores nonvolatile data in the memory cell based on the polarization effect of the ferroelectric substance interposed in the capacitive element, and the plurality of bit lines and the plurality of word lines are stored. In a nonvolatile semiconductor memory device in which a memory cell is connected to each intersection with and, the memory cell includes one transistor and one capacitor, and one terminal of the capacitor in the memory cell. Are connected to the plate line, the other terminal of the capacitive element in the memory cell is connected to the transistor, and the two memory cells are connected to the same word. One dummy cell is connected to the bit line connected to each of the cells, thereby achieving the above object.

[0027]

According to the first aspect of the present invention, when the nonvolatile semiconductor memory device is instructed to recall, the recall operation for actually reading data is performed and the recall counter counts the number of times of this recall operation. This recall operation is accompanied by polarization reversal of the ferroelectric substance because it is a destructive reading of data. Then, when the count value exceeds a predetermined number of times, the recall prohibition circuit prohibits the actual recall operation.

Therefore, even if the recall instruction is repeatedly issued due to a bug or runaway of the program of the computer device controlling the nonvolatile semiconductor memory device,
Actually, the recall operation after the predetermined number of times is prohibited in the nonvolatile semiconductor memory device, so that it is possible to prevent the recall operation from being unnecessarily executed due to the repetition of the abnormal recall instruction. However, if, for example, an access is performed in the volatile mode after the recall operation is performed, even if a subsequent recall instruction is given, this is considered to be a normal instruction. Therefore,
For example, in the case of access in this volatile mode, if an operation that is considered to be normal even if a recall instruction continues after that, the count value of the recall counter should be reset. Keep it. Then, there is no fear that the actual recall operation is prohibited by the normal recall instruction in the normal use.

When a recall counter is provided for each set of memory cells in which the recall operation is executed at the same time, when the count value of the recall counter becomes two or more times, the same memory cell continues to be recalled. Since the recall is instructed, the recall operation can be prohibited anytime thereafter. However, for example, when a plurality of memory cells are subjected to a recall operation in units of a page which is a subset of the plurality of memory cells and only one recall counter is provided for a plurality of pages, the plurality of pages are usually used. Since the memory cells are sequentially instructed to be recalled, it is not appropriate to prohibit the recall operation until the count for at least this page number is completed.

When the recall prohibition circuit prohibits the recall operation, reading in the volatile mode can be executed instead. Reading in volatile mode
Since the polarization inversion of the ferroelectric material is not involved, the life of the memory cell is not affected. Even if the recall prohibiting circuit prohibits the recall operation once, in the above example, the count value of the recall counter is reset once the access in the volatile mode is performed, so that the recall prohibition is automatically released. It is also possible to explicitly cancel the recall prohibition by a signal from the outside.

As a result, according to the first aspect of the invention, even if a wasteful recall instruction is repeated many times due to a program runaway or the like, the actual recall operation is prohibited after being executed a predetermined number of times. Therefore, the polarization inversion of the ferroelectric is unnecessarily repeated due to such an accident, and the life of the memory cell is not unexpectedly shortened.

According to the second aspect of the invention, when the nonvolatile semiconductor memory device is instructed to store, the store operation for actually storing the data is performed, and the store counter counts the number of times of this store operation. This store operation is
Since it is a non-volatile storage of data, it involves polarization reversal of the ferroelectric substance. When the count value exceeds the predetermined number of times, the store prohibition circuit prohibits the actual store operation.

Therefore, as in the case of the above-mentioned recall, even when a store instruction is repeatedly issued due to a bug in a program, a runaway, etc., in reality, after a predetermined number of times in the nonvolatile semiconductor memory device. Since the above store operation is prohibited, it is possible to prevent the store operation from being unnecessarily executed by repeating this abnormal store instruction.

However, if, for example, a recall operation is performed after the store operation is once executed, even if there is a store instruction again, this is considered to be a normal instruction. Therefore, if an operation that is considered to be a normal instruction is performed even if a store instruction follows, such as this recall operation, the count value of the store counter is reset. .
Then, there is no fear that the actual store operation is prohibited by the normal store instruction in the normal use.

When a store counter is provided for each set of memory cells for which the store operation is executed at the same time, when the count value of the store counter becomes two or more times, the same memory cells are consecutively stored. Since the store has been instructed, the store operation can be prohibited anytime thereafter. However, for example, when a store operation is performed on a plurality of memory cells in units of pages that is a subset of the plurality of memory cells and only one store counter is provided for a plurality of pages, normally, the plurality of pages are stored. Since the memory cells of are sequentially instructed to store, it is not appropriate to prohibit the store operation until the count for at least this page number is completed.

Even if the store inhibit circuit temporarily inhibits the store operation, in the above example, the count value of the store counter is reset by performing the recall operation once, so that the store inhibit is automatically released. It is also possible to explicitly release this store prohibition by a signal from the outside.

As a result, according to the second aspect of the invention, the actual store operation is prohibited after being executed a predetermined number of times, even if a wasteful store instruction is repeated many times due to a program runaway or the like. Therefore, the polarization inversion of the ferroelectric is unnecessarily repeated due to such an accident, and the life of the memory cell is not unexpectedly shortened.

The recall operation is the destructive reading of data as described above. However, according to the invention of claim 3,
When the data is read by the recall operation, this data is automatically stored again in the same memory cell in a non-volatile manner at the time of the recall.

Therefore, according to the third aspect of the present invention, the data read by the recall operation is stored again in the same memory cell as the non-volatile memory, so that the safety of the data is improved. The re-stored data can be read by executing the recall operation again.

When electric charges are accumulated in the capacitive element that performs the recall operation, the electric charge may affect the potential difference generated at one terminal of the capacitive element as noise, and erroneous data may be read out.

Therefore, according to the invention of claim 4, if the charge discharging means at the time of recall discharges the charges accumulated in this capacitor before applying the voltage to the other terminal of the capacitor during the recall operation, It becomes possible to reliably read the non-volatile data.

According to the fifth aspect of the present invention, one dummy cell in the so-called one-transistor / cell system is connected to two bit lines via the select transistor. Moreover, these two bit lines are connected to two memory cells on the same word line. Therefore, if the capacitances of these two bit lines are the same, the charges of the dummy cells are equally distributed to them, so that the intermediate potential when the charges of the memory cells are read to one bit line is set. Can be given.

Therefore, according to the invention of claim 5, the dummy cell in the non-volatile semiconductor memory device using the so-called one-transistor / cell type ferroelectric can be formed in the same shape as a normal memory cell. It becomes possible to avoid the trouble of design such as forming the size to ½ in order to limit the capacity and facilitate the manufacture of the semiconductor device.

According to the sixth aspect of the invention, normally, when the power is turned on, the stored data is read out. Therefore, when the power is turned on, the count value of the store counter is set, and the second switch circuit The common terminal is connected to the normally open side contact.

Therefore, since the store operation is prohibited immediately after the power is turned on, the safety of the stored data is enhanced.

[0046]

EXAMPLES Examples of the present invention will be described below. One embodiment of the present invention is shown in FIGS. FIG. 1 is a block diagram showing the configuration of the control unit of the nonvolatile semiconductor memory device. FIG. 2 is a block diagram showing the configuration of the memory cell array of the nonvolatile semiconductor memory device. FIG. 3 is a circuit diagram illustrating in detail the configuration on the bit line bit side in FIG. FIG. 4 is a circuit diagram illustrating in detail the configuration on the bit line bit bar side in FIG. FIG. 5 is a time chart showing the operation of the nonvolatile semiconductor memory device in the DRAM mode. FIG. 6 is a time chart showing the operation of the nonvolatile semiconductor memory device in the store mode. Figure 7
FIG. 6 is a time chart showing the operation of the nonvolatile semiconductor memory device in the recall mode. The same numbers are added to the components having the same functions as those of the conventional example shown in FIG.

In this embodiment, the nonvolatile semiconductor memory device of the one-transistor / cell system is described. A ferroelectric is used in this nonvolatile semiconductor memory device.

As shown in FIG. 2, this non-volatile semiconductor memory device has a large number of word lines WL, a corresponding plate line PT, and a large number of bit line pairs bit and bit bars, each of which intersects with each other. A memory cell 4 is arranged in each part. Each of the bit line pair bit and bit bar has the same pair of sense amplifiers 3.
It is connected to the. One dummy cell 11 is connected to the bit line bit for every two adjacent bit line bits. Also to the bit line bit bar, one dummy cell 11 is connected for every two adjacent bit line bit bars.

As shown in FIGS. 3 and 4, each memory cell 4 is composed of one capacitance element C and one selection transistor Q. One terminal of the capacitive element C is connected to the bit line bit or the bit line bit bar via the selection transistor Q, and the other terminal is connected to the plate line PT. The gate of the selection transistor Q is connected to the word line WL. Dummy cell 1
1 is one capacitance element CD and two selection transistors QD
It is composed by. One terminal of the capacitive element CD is connected to two adjacent bit lines bit or bit line bit bar via two selection transistors QD. The other terminal of the capacitive element CD is connected to the dummy cell plate line PTD. The gate of the selection transistor QD is connected to the dummy cell selection line φDL or the dummy cell selection line φDR. The capacitive element CD of the dummy cell 11 has the same shape as the capacitive element C of the memory cell 4 and has the same capacitance.

Here, one memory cell 4 connected to a certain bit line bit and a bit line bit paired with this memory cell 4.
FIG. 1 shows the configuration of the control unit of the nonvolatile semiconductor memory device, which focuses on one dummy cell 11 connected to the bar.

In FIG. 1, the word line WL connected to the gate of the selection transistor Q of the memory cell 4 is the selection transistor Q of the word line decoder 1 and the dummy cell 11.
It is connected to the gate of D. The plate line PT connected to one of the terminals of the capacitive element C which is not connected to the selection transistor Q has a plate line decoder 2 and one of the capacitive elements CD of the dummy cells 11 which is not connected to the selection transistor QD. Connected to the terminal. The word line decoder 1 and the plate line decoder 2 select one word line WL and the corresponding plate line PT based on the address input to the address buffer 5. The sense amplifier 3 is the data I / O interface 1
Data is transmitted and received with the outside via 0. The bit line bit bar is connected to the sense amplifier 3. However, this bit line bit bar is not shown in FIG.

Address buffer 5 and sense amplifier 3
The data I / O interface 10 and the like are DRAM
It is controlled by the mode timing control circuit 7, the recall mode timing control circuit 8 or the store mode timing control circuit 9. The DRAM mode timing control circuit 7 controls the memory cell 4 in the volatile DRAM mode.
Is a control circuit for accessing. The recall mode timing control circuit 8 is a control circuit for reading out the nonvolatile data of the memory cell 4 in the recall mode. The store mode timing control circuit 9 is a control circuit for writing nonvolatile data in the memory cell 4 in the store mode.

The DRAM mode timing control circuit 7, the recall mode timing control circuit 8 and the store mode timing control circuit 9 are the control signal input buffer 6
One of them is selected based on the control signal input to. The first output terminal of the control signal input buffer 6 is
It is connected to the input terminal of the OR circuit 12 and the reset input R of the recall counter 13. The output terminal of the OR circuit 12 is connected to the input terminal of the DRAM mode timing control circuit 7. The second output terminal of the control signal input buffer 6 is the common terminal of the first switch circuit 14,
It is connected to the count input CL of the recall counter 13 and the reset input R of the store counter 15. The third output terminal of the control signal input buffer 6 is the common terminal of the second switch circuit 16 and the store counter 15
Is connected to the count input CL. The normally closed side terminal of the first switch circuit 14 is connected to the recall mode timing control circuit 8, and the normally opened side terminal is connected to the other input terminal of the OR circuit 12. The normally closed terminal of the second switch circuit 16 is connected to the store mode timing control circuit 9. The normally open side terminal of the second switch circuit 16 is
Not connected.

The recall counter 13 counts the number of times the recall mode selection signal input to the count input CL is input. When the DRAM mode selection signal is input to the reset input R of the recall counter 13, the recall counter 13 is reset. When the number of input of the recall mode selection signal exceeds the number of word lines WL, the first switch circuit 14 is switched so that the common terminal of the first switch circuit 14 is connected to the normally open side terminal. The store counter 15 counts the number of times the store mode selection signal input to the count input CL is input. When a recall mode selection signal is input to the reset input R of the store counter 15, the store counter 15
Is reset. When the number of input of the store mode selection signal exceeds the number of word lines WL, the second switch circuit 16 is switched so that the common terminal of the second switch circuit 16 is connected to the normally open side terminal.

When the DRAM mode selection signal is output from the control signal input buffer 6 or when the recall counter 13 connects the first switch circuit 14 so that the common terminal of the first switch circuit 14 is connected to the normally open side terminal. The switching and control signal input buffer 6 is connected to the first switch circuit 14
When a recall mode selection signal is output via
R circuit 12 to DRAM mode timing control circuit 7
Then, the DRAM mode selection signal is input. After the recall counter 13 is reset, the number of input of the recall mode selection signal exceeds the number of word lines WL, and when the recall mode selection signal is output from the control signal input buffer 6, the recall mode timing A recall mode selection signal is input to the control circuit 8. Further, after the store counter 15 is reset, the number of times the store mode selection signal is input is determined by the word line WL.
The store mode selection signal is input to the store mode timing control circuit 9 until the number of lines is exceeded and the store mode selection signal is output from the control signal input buffer 6.

In the nonvolatile semiconductor memory device shown in FIGS. 1 to 4, the word line WL1 and the plate line PT1 corresponding to the word line WL1 are selected by the address input to the address buffer 5, and then connected to the word line WL1. The operation when the memory cell 4 is accessed will be described.

When the DRAM mode is selected, D
According to the signal output from the RAM mode timing control circuit 7, the plate line PT1 and the dummy cell plate line PTD are grounded. Therefore, as shown in FIG. 5, the plate line PT1 and the dummy cell plate line PTD are maintained at 0V. Signal line φEQ shown in FIGS. 3 and 4
While the VCC level is being applied, the bit line pair bit
Since the bit line and the bit bar are grounded, the potential of the bit line pair bit and the bit bar is 0V. Further, since the signal line φP also becomes the ground level in the initial stage of the DRAM mode, the capacitive element CD of the dummy cell 11 is precharged to the VCC level. Next, the word line WL1 and the dummy word line D
When the potential of WR becomes Vcc + Vth level, the charge accumulated in the capacitive element C of the memory cell 4 connected to this word line WL1 is read out to the bit line bit, so that FIG.
As shown in, the potential of the bit line bit rises. In addition, the word line WL1 and the dummy word line DWR are VCC +
At the Vth level, the dummy cell selection line φDR also becomes the Vcc level, and the charge is charged from the capacitive element CD precharged to the Vcc level in the dummy cell 11 to the bit line bit.
Since it is read by the bar, the potential of the bit line bit bar also rises as shown in FIG. However, the dummy cell 11
Since the charge accumulated in one of the two bit lines is read out to the two bit line bit bars, the potential of each bit line bit bar becomes an intermediate potential between the potential of the bit line bit and 0V. As the potential of the bit line pair bit and bit bar rises, the signal line φIS becomes VCC + Vth level and the signal line φSEN becomes VCC level. When the potential difference between the bit line pair bit and the bit bar is sensed by the sense amplifier 3, the bit line pair b
Based on the data stored in the memory cell 4, the potentials of the it and bit bars are fixed at the VCC level or the 0V level.

In the store mode, in addition to the read operation in the DRAM mode, as shown in FIG. 6, according to the signal output from the store mode timing control circuit 9,
A voltage pulse changing from 0V → VCC → 0V level is applied to the plate line PT1 and the dummy cell plate line PTD, respectively. DRA when store mode is selected
A read operation in the M mode is performed. After the volatile data of the memory cell 4 is output to the bit line pair bit and bit bar, a pulse is applied to the plate line PT1. By applying this pulse, the polarization state of the ferroelectric substance of the capacitive element C is changed from point E → point B → point C or point D → point E → in FIG.
It is moved to point D, and polarization inversion is performed according to the data stored in this memory cell. By this polarization reversal, this data is again stored in the memory cell 4 in a nonvolatile manner, and then a pulse is applied to the dummy cell plate line PTD during the subsequent precharge period, whereby the polarization state is shown in FIG. Dummy cell 1 so that it moves to point E
The polarization state of the ferroelectric substance of the capacitive element CD in 1 is changed.

In the recall mode, in response to the signal output from the recall mode timing control circuit 8, as shown in FIG. 7, first, the signal line φEQ is set to the VCC level and the bit line pair bit and bit bar are grounded. It Further, since the signal line φP also becomes the ground level in the initial stage of the recall mode, the capacitive element CD of the dummy cell 11 is precharged to the VCC level. Next, the word line WL1 and the dummy word line DWR transit to the level of Vcc + Vth. Since the signal line φEQ becomes VCC level again in synchronization with this transition,
The electric charge accumulated in the capacitive element C of the memory cell 4 is discharged. On the other hand, when a voltage of Vcc level is applied to the plate line PT1, the polarization state of the ferroelectric substance of the capacitive element C in the memory cell 4 changes from point C to point B or point E to point B as shown in FIG. Since it moves to the point, the potential of the bit line bit rises according to the data stored in the memory cell 4.
Further, when the potential of the dummy cell plate line PTD becomes VCC level, the polarization state of the ferroelectric substance of the capacitive element CD in the dummy cell 11 moves from point E to point B as shown in FIG. The potential of the bar rises. However, since the charges accumulated in one of the dummy cells 11 are read out to the two bit line bit bars, the potential of each bit line bit bar is equal to the potential of the bit line bit and 0 V.
It becomes an intermediate potential. When the plate line PT1 becomes 0V, the potentials of the bit line pair bit and bit bar also slightly drop according to the change of the plate line PT1. On the other hand, in synchronization with the change of the plate line PT1, the signal line φI
After the potential of S becomes VCC + Vth, the signal line φSEN becomes VCC level. When the potential of the signal line φSEN is VCC,
The sense amplifier 3 senses. When the sense amplifier 3 senses, the potentials of the bit line pair bit and bit bar are set to VCC or 0V based on the data stored in the memory cell 4, and the data is read.

This destructive read data is non-volatilely stored in the same memory cell 4 again by applying a voltage pulse to the plate line PT1 again. In this way, the memory cell 4 storing the data again in the nonvolatile manner is
When accessed in the RAM mode, for example, the polarization state of the ferroelectric substance at point C or point E in FIG.
After moving to the point, the nonvolatile data is destroyed because both of them return to the point E. Dummy cell plate line PT
A voltage pulse is applied to D again during the precharge period after access in the DRAM mode, and the polarization state of the ferroelectric substance of the capacitive element CD in the dummy cell 11 is shown in FIG.
Move to point E as shown in.

As described above, when the recall mode timing control circuit 8 sequentially executes the control in the recall mode for all the word lines WL, the count value of the recall counter 13 reaches the number of the word lines WL. In normal operation, the count value of the recall counter 13 is reset after the DRAM mode timing control circuit 7 executes the control in the DRAM mode. After this reset, when the recall mode is selected again via the control signal input buffer 6, the recall mode timing control circuit 8 outputs a signal instructing execution of the control in this recall mode. DR
Even when the power is turned off after the control in the store mode is executed without executing the control in the AM mode, the count value of the recall counter 13 is reset at the next power-on.

The store mode timing control circuit 9
When the control by the store mode is sequentially executed for all the word lines WL, the count value of the store counter 15 becomes equal to the number of the word lines WL. In normal operation, the recall mode timing control circuit 8
Outputs a signal for executing the control in the recall mode. Since the count value of the store counter 15 is reset according to the output signal, when the signal for selecting the store mode is input again via the control signal input buffer 6, the store mode timing control is performed. The circuit 9 can execute control according to this store mode. When the power is turned on after the power is turned off without the control in the recall mode being executed, the count value of the store counter 15 is reset.

As another embodiment, normally, when the power is turned on, the stored data is read out. Therefore, the count value of the store counter 15 is set when the power is turned on, and the common value is set in the second switch circuit 16. Make sure that the terminal is connected to the normally open contact. As a result, the store operation immediately after the power is turned on is prohibited, and the safety of the stored data is improved.

However, if a recall mode or store mode instruction is repeatedly issued due to a bug or runaway of the program of the computer device controlling the nonvolatile semiconductor memory device of this embodiment, the recall Since the counter 13 or the store counter 15 counts without being reset, this count value exceeds the number of word lines WL. When the count value exceeds the number of word lines, the common contact of the first switch circuit 14 or the second switch circuit 16 is switched so as to be connected to the normally open side contact, so that the recall mode timing control circuit 8 or the store mode. Unnecessary control by the timing control circuit 9 in the recall mode and the store mode is not executed. Recall counter 13
When the count value of 1 exceeds the number of word lines WL, the common contact of the first switch circuit 14 is switched so as to be connected to the normally open side contact, so that the recall is performed via the control signal input buffer 6. The signal that selects the mode is OR
DRAM mode timing control circuit 7 via circuit 12
Entered in. Therefore, instead of the recall mode involving the polarization reversal of the ferroelectric substance, D without the polarization reversal of the ferroelectric substance
The data reading in the RAM mode is executed, and the volatile data read by the execution of the control in the first recall mode is repeatedly read.

As described above, according to the nonvolatile semiconductor memory device of the present embodiment, even if a wasteful recall mode or store mode instruction is repeated many times due to a program runaway, etc., these recall modes and Execution of store mode is prohibited. Therefore, the polarization reversal of the ferroelectric material is not unnecessarily repeated due to program runaway and the like, and the life of the memory cell is not unexpectedly shortened.

In the recall mode, the non-volatile data is once destroyed, but since it is non-volatilely stored and stored again in the original memory cell 4 after reading, the data safety is improved. Further, in the recall mode, since the non-volatile data is read after discharging the electric charge accumulated in the capacitive element C of the memory cell 4, noise due to the accumulated electric charge is removed to ensure the non-volatile data reading. You will be able to do it.

In addition, in this embodiment, by using the dummy cell 11, the memory cell 4 of the 1-transistor / cell system is formed.
However, since the dummy cell 11 is connected to two adjacent bit lines bit or bit line bit bar, it can be formed in the same shape as the memory cell 4, and the semiconductor device can be manufactured. Can be easy.

[0068]

As is apparent from the above description, according to the inventions of claims 1 and 2, useless recall operation and store operation are prohibited, so that the polarization reversal of the ferroelectric substance becomes unnecessary. Repeatedly, the life of the memory cell is not unexpectedly shortened.

According to the third aspect of the present invention, the data read by the recall operation is stored again in the same memory cell as the non-volatile memory, so that the safety of the data is improved.

Further, according to the invention of claim 4, since the electric charge accumulated in the capacitive element is discharged before the recall operation, the nonvolatile data can be surely read.

According to the invention of claim 5, the dummy cell in the non-volatile semiconductor memory device using the so-called 1-transistor / cell type ferroelectric can be formed in the same shape as a normal memory cell. The semiconductor device can be easily manufactured.

Further, according to the invention of claim 6, the store operation is prohibited immediately after the power is turned on, so that the safety of the stored data is enhanced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a control unit of a nonvolatile semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a memory cell array of a nonvolatile semiconductor memory device according to an embodiment of the present invention.

FIG. 3 is a circuit diagram illustrating an embodiment of the present invention and is a detailed description of the configuration on the bit line bit side in FIG. 2.

FIG. 4 is a circuit diagram illustrating an embodiment of the present invention and is a detailed description of the configuration on the bit line bit bar side in FIG.

FIG. 5 is a time chart showing the operation of the nonvolatile semiconductor memory device in the DRAM mode according to the embodiment of the present invention.

FIG. 6 is a time chart showing an operation of the nonvolatile semiconductor memory device in a store mode according to an embodiment of the present invention.

FIG. 7 is a time chart showing an operation of the nonvolatile semiconductor memory device in a recall mode according to an embodiment of the present invention.

FIG. 8 is a diagram showing a hysteresis characteristic of a polarization state of a ferroelectric substance interposed in a capacitive element.

FIG. 9 is a block diagram showing a conventional example and showing a configuration of a control unit of a nonvolatile semiconductor memory device.

FIG. 10 is a circuit diagram of a memory cell for explaining the operation when storing data “0” in the 2-transistor / cell system.

FIG. 11 is a circuit diagram of a memory cell for explaining the operation when storing data “1” in the 2-transistor / cell method.

FIG. 12 is a circuit diagram of a memory cell for explaining a recall operation in the 2-transistor / cell system.

[Explanation of symbols]

 3 Sense Amplifier 4 Memory Cell 13 Recall Counter 14 First Switch Circuit 15 Store Counter 16 Second Switch Circuit C Capacitive Element

Claims (6)

[Claims] 1. Non-volatile data is stored in a memory cell based on the polarization effect of a ferroelectric substance interposed in a capacitive element,
A nonvolatile semiconductor memory that recalls the data by detecting a potential generated at the other terminal of the capacitance element according to the polarization state of the ferroelectric substance when a voltage is applied to one terminal of the capacitance element. A device for counting the number of times of a series of recall operations and resetting the count value according to a signal from the outside, and a recall operation when the count value of the counting means exceeds a predetermined value. A non-volatile semiconductor memory device having a prohibition means. 2. A ferroelectric is interposed in the capacitive element, a voltage corresponding to data is applied to one terminal of the capacitive element, and a pulse is applied to the other terminal of the capacitive element to enhance the strength. A non-volatile semiconductor memory device that stores data by setting a dielectric state in a polarization state corresponding to data. It counts the number of series of store operations and resets this count value in response to an external signal. A non-volatile semiconductor memory device, comprising: a counting unit that performs a storing operation and a unit that prohibits a store operation when the count value of the counting unit exceeds a predetermined value. 3. Nonvolatile data is stored in a memory cell based on the polarization effect of a ferroelectric substance interposed in a capacitive element,
When a voltage is applied to one terminal of the capacitance element, the data is recalled by detecting the potential generated at the other terminal of the capacitance element according to the polarization state of the ferroelectric substance, and A voltage corresponding to data is applied to one terminal of the element, and a pulse is applied to the other terminal of the capacitive element to bring the ferroelectric substance into a polarized state corresponding to the data, thereby storing data. 3. The nonvolatile semiconductor memory device according to claim 2, further comprising means for canceling prohibition of the store operation when the recall operation is started or ended. 4. Nonvolatile data is stored in a memory cell based on a polarization effect of a ferroelectric substance interposed in a capacitive element,
A non-volatile semiconductor that recalls the data by detecting a potential generated at the other terminal of the capacitance element according to the polarization state of the ferroelectric substance when a voltage is applied to the first terminal of the capacitance element. A non-volatile semiconductor memory device comprising: a memory device, which discharges electric charges accumulated in a storage capacitor element before a voltage is applied to a first terminal of the capacitor element. 5. Nonvolatile data is stored in a memory cell based on a polarization action of a ferroelectric substance interposed in a capacitive element,
In a nonvolatile semiconductor memory device in which memory cells are connected to respective intersections of a plurality of bit lines and a plurality of word lines, the memory cells include one transistor and one capacitor One terminal of the capacitive element in the cell is connected to the plate line, the other terminal of the capacitive element in the memory cell is connected to the transistor, and two memory cells are connected to the same word. A non-volatile semiconductor memory device in which one dummy cell is connected to a bit line connected to each of the two memory cells. 6. A non-volatile data is stored in a memory cell based on a polarization effect of a ferroelectric substance interposed in the capacitive element, and when a voltage is applied to one terminal of the capacitive element, the capacitive element is stored. A non-volatile semiconductor memory device that recalls the data by detecting a voltage generated according to the polarization state of the ferroelectric substance at the other terminal of The nonvolatile semiconductor memory device according to claim 2.