JP3793021B2 - Nonvolatile multi-value storage device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a non-volatile multi-value storage device, and more particularly to a non-volatile multi-value storage device that includes a dielectric capacitor made of a ferroelectric material and is capable of multi-value storage with a gigabit or higher capacity.
[0002]
[Prior art]
In recent years, storage devices (ferroelectric memories) using a ferroelectric thin film as a storage medium have been developed, and some of them have already been put into practical use. Ferroelectric memory is non-volatile, and its memory contents are not lost even after the power is turned off. In addition, when the film thickness is sufficiently thin, spontaneous polarization reversal is fast, and writing is as fast as DRAM (dynamic random access memory). , And the like.
[0003]
At present, two types of configurations have been proposed as semiconductor memory devices using ferroelectric thin films. In these two types of structures, a ferroelectric capacitor is formed by a ferroelectric film, and a ferroelectric gate transistor is formed.
[0004]
When a ferroelectric capacitor is formed, it is combined with a selection transistor to form a 1-bit memory cell. On the other hand, when forming a ferroelectric gate transistor, it is combined with one ferroelectric gate transistor or one or two selection transistors to form a 1-bit memory cell.
[0005]
In contrast to such a method of storing 1 bit in one memory cell, a method of storing multiple values in one memory cell has been proposed as a more efficient method.
[0006]
One of the methods is a method in which a plurality of upper electrodes are connected to one ferroelectric capacitor to generate a plurality of polarization states in the ferroelectric capacitor (for example, Japanese Patent Publication No. 854165). However, according to this method, the number of upper electrodes increases in proportion to the number of memory bits, and the area of the ferroelectric capacitor also increases. Therefore, the original purpose of achieving high density with the same chip area is achieved. It is difficult to do.
[0007]
As another method, there are methods in which a plurality of write voltages are applied to a ferroelectric capacitor to generate a plurality of polarization states (for example, JP-A-10-312691 and JP-A-11-45584).
[0008]
This storage method will be described with reference to FIG.
[0009]
FIG. 29 is a graph illustrating a hysteresis curve representing the relationship between the voltage applied to the ferroelectric capacitor and the amount of polarization. That is, first, the voltage V0 is applied to the ferroelectric capacitor to reverse the polarization to the minus side. After that, by applying voltages V2 to V3 smaller than the voltage V1 that is completely inverted to the plus side, in addition to the charge P0 in the completely inverted state on the minus side and the charge P1 in the completely inverted state on the plus side, Multivalue storage can be realized by using the corresponding charges P2 to P3.
[0010]
On the other hand, in the read operation, the stored charge P0 to P3 is applied by turning on the select transistor of each cell and applying a read voltage, as in a normal one-transistor one-capacitor FRAM (ferroelectric random access memory) or DRAM. Multi-value reading is performed by reading to the bit line capacitance and comparing the bit line potential corresponding to the accumulated charge with the potential from the potential generator.
[0011]
[Problems to be solved by the invention]
However, there are some problems in realizing a highly integrated ferroelectric memory by the above write and read operations.
[0012]
The first problem relates to the write operation, and this point will be described with reference to FIG. In the original PV hysteresis curve of the ferroelectric capacitor, polarization inversion occurs at constant coercive voltages V0 and V1, as illustrated in FIG. Capacitors using bulk ferroelectric single crystals have long been known to have this behavior, and epitaxial PZT (lead zirconate titanate: PbZr) prepared by CVD also in thin films. _x Ti _1-x O ₃ ) It is known that a capacitor or the like behaves similarly. That is, since a ferroelectric capacitor causes polarization inversion at a single voltage, it is inherently impossible to realize a partial inversion state using a plurality of voltages.
[0013]
In other words, the ferroelectric characteristic in which the PV curve is inclined as shown in FIG. 29 means that the ferroelectric film is not uniform and deteriorates and varies for some reason. When there are variations in coercive voltage due to many domains constituting the ferroelectric capacitor, the center of hysteresis is shifted, or when a thin paraelectric layer is formed at the interface between the ferroelectric and the electrode, FIG. A tilted PV curve as shown in FIG. Generally speaking, as the PV curve is inclined (the inclination Δy / Δx is smaller), the ferroelectric properties such as the polarization amount, the holding property of the polarization, and the fatigue property are deteriorated. As the crystallinity of the dielectric improves, the PV curve tends to rise vertically (inclination Δy / Δx increases). If the ferroelectric characteristics of one capacitor are taken out, it seems that multi-value writing with a plurality of voltages is possible at first glance.
[0014]
However, the amount of slope in the PV curve is essentially a “variation” component, and it is well known that the PV curve changes greatly depending on the dielectric film formation conditions, the presence or absence of microfabrication, and the presence or absence of heat treatment. It is a fact that has been. In other words, since the coercive voltage and its dispersion greatly change due to slight variations in process parameters, ferroelectrics that require guaranteeing the operation of individual memory cells on the premise that a large number of wafers with a large number of capacitors will be created. It should be understood that in a memory, it is essentially impossible to perform multi-level writing by voltage control to individual ferroelectric capacitors.
[0015]
The second problem relates to the reading method. Read sensitivity in a DRAM using a memory cell composed of one transistor and one paraelectric capacitor is mainly determined by the relative relationship between the ratio CS / CB of the cell capacitance CS and the bit line capacitance CB and the sensitivity of the sense amplifier. In other words, if the bit line capacity and the sensitivity of the sense amplifier are constant, there is a minimum cell capacity necessary for storing 1 bit, which is 20 to 40 fC in DRAM. The biggest eye of DRAM capacitor development is how to secure the minimum cell capacity within the limitation of the cell area reduced for each generation.
[0016]
The same scheme is basically applied to the FRAM using one transistor and one ferroelectric capacitor. Similar to reading out the charge accumulated in the paraelectric capacitor in the DRAM to the bit line, in the FRAM, the residual polarization charge in the ferroelectric capacitor is read out to the bit line and determined by the sense amplifier. Ferroelectric film PZT and SBT (strontium bismuth tantalate: SrBi) used in FRAM ₂ Ta ₂ O ₉ ), The residual polarization amount is 30 μC / cm, respectively. ² 15 μC / cm ² Degree. Therefore, the minimum processing dimension is F and the cell area is 8F. ² , Capacitor area 3F ² If the layout is created, the cell charge amount is reduced to 20 fC in the 0.15 μm generation and the 0.20 μm generation. In other words, the subsequent reduction is impossible unless the ferroelectric capacitor cell is three-dimensionally formed. However, since the ferroelectric film is large in thickness, it is very difficult to make it three-dimensional.
[0017]
A memory reading method using ferroelectric multilevel storage reads out the charge of the ferroelectric capacitor to the bit line capacitance as described above, and compares the bit line potential with the reference potential from the potential generator by a sense amplifier. As long as this method is used, the amount of charge per bit is smaller in multi-value reading than in binary reading, and the required amount of charge becomes more difficult to secure as miniaturization occurs. Therefore, it becomes difficult to realize the purpose of increasing the density of the memory by multi-leveling.
[0018]
As described above, several proposals have already been made for a multi-level memory using a ferroelectric capacitor. However, even if any method is used, the degree of integration greatly exceeds that of a conventional binary ferroelectric memory. It is difficult to realize a multi-level ferroelectric memory.
[0019]
The present invention has been made on the basis of recognition of such a problem, and an object of the present invention is to solve the above-mentioned problems relating to multi-level writing to a ferroelectric capacitor in a semiconductor multi-level memory using a ferroelectric capacitor. An object of the present invention is to overcome the problems relating to multi-level read sensitivity and to provide a non-volatile multi-level storage device having a degree of integration greatly exceeding that of a binary ferroelectric memory.
[0020]
[Means for Solving the Problems]
In the Japanese Unexamined Patent Publication No. 2000-156472 (P2000-156472A), the present inventors use a ferroelectric capacitor as a capacitor for storing data, and store binary data of “0” level and “1” level. A storage device is disclosed.
[0021]
FIG. 28 is a conceptual diagram showing the main part of the storage device disclosed in the publication. That is, this figure shows the configuration of the memory cell of the storage device, and the storage capacitor C in the storage node Ns. _M (Hereinafter referred to as “CM”), reference capacitor C _REF (Hereinafter referred to as “CREF”), control transistor Q _C One end (hereinafter referred to as “QC”), a reading transistor Q _READ Each of the control electrodes (hereinafter referred to as “QREAD”) represents a connected circuit.
[0022]
According to this configuration, it is possible to provide a storage device that can stably store binary data, can be scaled, can be easily integrated, and has a simple manufacturing process.
[0023]
Based on this configuration, the inventor further proceeds with trial manufacture, and invents a non-volatile multilevel storage device having a unique configuration and capable of stably writing / reading multilevel data of three or more values. It came to.
[0024]
That is, in order to achieve the above object, a nonvolatile multilevel storage device according to the present invention includes a storage capacitor for storing data according to a polarization state of a ferroelectric, and a buffer capacitor connected in series to the storage capacitor. A read transistor having a gate electrode connected to a storage node that is a connection point between the storage capacitor and the buffer capacitor, and a control transistor having a main electrode connected to the storage node,
By making the capacitance of the buffer capacitor variable, it is possible to write charges corresponding to the partial polarization state of the storage capacitor.
[0025]
Here, the amount of charge read to the storage node is determined according to the capacity of the buffer capacitor using a connected read transistor, thereby including the partial polarization state of the storage capacitor. The value data can be read out.
[0026]
The buffer capacitor has a capacitor block formed by connecting a plurality of capacitors in series or in parallel, and the capacitance can be varied by selecting a part of the plurality of capacitors.
[0027]
Alternatively, the nonvolatile multi-value storage device of the present invention includes a storage capacitor that stores data according to a polarization state of a ferroelectric, a buffer capacitor connected in series to the storage capacitor, the storage capacitor, A read transistor having a gate electrode connected to a storage node that is a connection point to the buffer capacitor, a control transistor having a main electrode connected to the storage node, and a multiple write control circuit,
The multi-time write control circuit can change the number of times of writing charges to the storage capacitor to form a partial polarization state and a complete polarization state of the storage capacitor, respectively.
[0028]
Alternatively, the nonvolatile multi-value storage device of the present invention includes a storage capacitor that stores data according to a polarization state of a ferroelectric, a buffer capacitor connected in series to the storage capacitor, the storage capacitor, A read transistor having a gate electrode connected to a storage node that is a connection point to the buffer capacitor, a control transistor having a main electrode connected to the storage node, and a multiple-time read control circuit,
The multiple-time readout control circuit reads out the multi-value data including the partial polarization state of the storage capacitor by changing the number of times of reading the electric charge from the storage capacitor.
[0029]
Here, the charge is written to the storage capacitor by supplying a charge from the buffer capacitor to the storage capacitor after applying a precharge voltage to the buffer capacitor or by connecting the buffers connected in series. The write voltage may be applied to both ends of the storage capacitor and the storage capacitor.
[0030]
In addition, after a precharge voltage is applied to the buffer capacitor, a charge is read from the storage capacitor to the buffer capacitor, or a read voltage is applied to both ends of the buffer capacitor and the storage capacitor connected in series. By determining the operation state of the read transistor in accordance with whether to apply or not, multi-value data including the partial polarization state of the storage capacitor can be read.
[0031]
[Means for Solving the Problems]
According to one aspect of the present invention, a storage capacitor for storing data according to a polarization state of a ferroelectric, a buffer capacitor connected in series to the storage capacitor, the storage capacitor, and the buffer capacitor, A read transistor having a gate electrode connected to the storage node, a control transistor having a main electrode connected to the storage node, and the buffer capacitor after applying a variable precharge voltage to the buffer capacitor A non-volatile multi-value storage comprising: a write voltage control circuit capable of supplying a charge from a capacitor to the storage capacitor to form a partial polarization state and a complete polarization state of the storage capacitor, respectively An apparatus is provided.
[0032]
Alternatively, the nonvolatile multi-value storage device of the present invention includes a storage capacitor that stores data according to a polarization state of a ferroelectric, a buffer capacitor connected in series to the storage capacitor, the storage capacitor, A read transistor having a gate electrode connected to a storage node that is a connection point to the buffer capacitor, a control transistor having a main electrode connected to the storage node, and a read voltage control circuit,
The read voltage control circuit reads a charge from the storage capacitor to the buffer capacitor after applying a variable precharge voltage to the buffer capacitor, or the buffer capacitor and the storage capacitor connected in series The multi-value data including the partial polarization state of the storage capacitor is read by either method of applying a variable read voltage to both ends.
[0033]
Here, the precharge voltage or the read voltage may be a voltage of two or more levels corresponding to any of three or more multi-value data.
[0034]
The storage capacitor includes a plurality of storage cells connected in parallel to each other, and each of the plurality of storage cells includes a selection MOS transistor and a ferroelectric capacitor connected in series. can do.
[0035]
Further, the storage capacitor has a plurality of storage cells connected in series with each other, and each of the plurality of storage cells has a selection MOS transistor and a ferroelectric capacitor connected in parallel. can do.
[0036]
The storage capacitor includes a plurality of selection MOS transistors connected in series to each other, storage electrodes respectively connected to a common main electrode of the selection transistors, a plate electrode facing the storage electrode, It can be a NAND type memory cell array comprising a storage capacitor having a storage electrode and a ferroelectric thin film sandwiched between the plate electrodes.
[0037]
The effective capacitance in the operating voltage range of the buffer capacitor may be not less than 1/10 and not more than twice the effective capacitance in the operating voltage range of the storage capacitor.
[0038]
The buffer capacitor may be a ferroelectric capacitor or a paraelectric capacitor.
[0039]
That is, the first main point of the present invention is that a pseudo constant charge multi-value write method using a buffer capacitor is adopted instead of the constant voltage multi-value write method of the ferroelectric capacitor for storage which has been conventionally proposed. is there. By adopting the pseudo-constant charge writing method, it becomes possible to write a multi-valued charge amount even to a ferroelectric capacitor having a good square PV curve inherent in ferroelectrics, and process parameters. Even when the shape of the PV hysteresis is changed due to the fluctuation of the above, there is an advantage that the fluctuation of the write charge amount becomes much smaller.
[0040]
However, even in a conventional method called constant voltage writing, strictly speaking, when precharging a bit line and writing it into a ferroelectric capacitor, strictly speaking, it is not a complete constant voltage writing but via a bit line capacitance. It is a written. However, the present invention has a buffer capacitor dedicated to independent writing (and reading) different from the bit line, and the bit line capacity is about 5 to 10 times the equivalent capacity of the cell. On the other hand, in order to realize writing and reading operations with sufficient resolution, there is a clear difference that the equivalent capacitance of the buffer capacitor is preferably about 1/10 to 2 times the equivalent capacitance of the storage capacitor.
[0041]
Further, the present invention has means for connecting a storage capacitor and a buffer capacitor in series; and connecting the gate electrode of the read transistor and the main electrode of the control transistor to the connection point; The second feature is that the semiconductor memory device performs the above.
[0042]
In addition, by applying a plurality of levels of voltages corresponding to multi-value data of two or more values to both capacitors during the read operation, multi-value data can be determined by the read transistor.
[0043]
In addition, by repeating the read operation after applying the precharge voltage or the voltage application read operation after connecting the buffer capacitor and the storage capacitor a plurality of times corresponding to multi-value data of two or more values, the read transistor Multi-value data can be determined.
[0044]
The buffer capacitor comprises a capacitor block formed by connecting a plurality of buffer capacitors in series or in parallel; a number of the buffer capacitors corresponding to multi-value data of two or more values are connected in series with a storage capacitor. By applying a voltage after the connection, multi-value data can be determined by the reading transistor.
[0045]
On the other hand, the second main point of the present invention is to call the charge of the conventionally proposed storage ferroelectric capacitor to the bit line capacitance, and compare the bit line potential and the potential from the potential generator with a sense amplifier to obtain multiple values. Instead of the data determination method, the charge of the storage ferroelectric capacitor is called to the buffer capacitor, and the potential of the storage node that is the connection point between the storage capacitor and the buffer capacitor is added to the gate electrode of the read transistor. A method of directly determining multi-value data with a reading transistor is employed. In the method using the bit line capacitance and the sense amplifier, as described in detail in the conventional example, the cell charge amount needs to be a constant value that enables reading, and therefore the ferroelectric capacitor has a large charge. There has been a problem that reading becomes difficult when the values are divided into values or as the miniaturization progresses. However, by adopting this method, it is possible to use a buffer capacitor with a capacity corresponding to the amount of charge divided into multiple values of the ferroelectric capacitor. However, there is a great advantage that the read sensitivity does not become a problem.
[0046]
According to a third aspect of the present invention, the storage capacitor is a storage cell block in which a plurality of unit cells each having a selection MOS transistor and a storage ferroelectric capacitor connected in series are connected in parallel to a sub bit line. Features.
[0047]
That is, a multi-value memory cell composed of a storage capacitor, one or a plurality of buffer capacitors, and a read transistor has a larger memory cell area than a normal 2-bit FRAM memory cell composed of one transistor and one capacitor. . On the other hand, by replacing one storage capacitor with a storage cell block including a plurality of storage unit cells, the memory cell occupation area per storage capacitor can be drastically reduced. By appropriately selecting the transistors, the advantage that random access is possible can be simultaneously maintained.
[0048]
According to the present invention, the storage capacitor is a storage cell column (called a chain cell column) in which a plurality of unit cells in which a selection MOS transistor and a storage ferroelectric capacitor are connected in parallel are connected in series. Is the fourth feature.
[0049]
That is, a multi-value memory cell composed of a storage capacitor, one or a plurality of buffer capacitors, and a read transistor has a larger memory cell area than a normal 2-bit FRAM memory cell composed of one transistor and one capacitor. . On the other hand, the memory cell occupation area per storage capacitor can be drastically reduced by replacing one storage capacitor in the chain cell row, and by appropriately selecting a selection transistor, The advantage that random access is possible can be maintained at the same time.
[0050]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
First, as a first embodiment of the present invention, a nonvolatile multi-value storage device including a variable-capacitance buffer dielectric capacitor will be described.
[0051]
FIG. 1 is a conceptual diagram showing the main configuration of the nonvolatile multilevel storage device of this embodiment. That is, this figure is a circuit diagram for explaining a basic configuration using a variable capacitance buffer paraelectric capacitor. In the circuit of FIG. 1, a storage ferroelectric capacitor CM and a buffer paraelectric capacitor CR are connected in series, and a storage node NS which is a connection portion thereof, and a gate electrode of a read transistor QREAD, The main electrode of the control transistor QC is connected.
[0052]
First, the writing operation of this circuit will be described.
[0053]
FIG. 2 is a graph for explaining the basic write operation of this circuit.
[0054]
First, the control transistor QC is turned on, and a positive write voltage VW0 higher than the inversion voltage of the memory ferroelectric capacitor CM as shown in FIG. By returning to, the memory state “0” completely polarized in the positive direction can be obtained.
[0055]
When writing the memory states “1” to “3” corresponding to the partial polarization or the negatively inverted polarization, after writing “0” according to the above sequence, the control transistor is turned off again to turn off the storage node NS. And a write voltage VW is applied between the terminals A and B through buffer capacitors CR having capacitances C1 to C3, respectively, as shown in FIGS. As a result, polarization corresponding to the storage states “1” to “3” can be written. That is, the capacity of the buffer capacitor CR is variable, and the storage state “1” is written to the storage capacitor CM when the capacitance is C1, the storage state “2” is written to the capacitance C2, and the storage state “3” is written to the storage capacitor CM. Can be.
[0056]
On the other hand, the writing method by precharge can be similarly performed.
[0057]
First, “0” is written as shown in FIG. 2A according to the sequence similar to the above. Thereafter, the capacity of the buffer capacitor CR is appropriately set to C1 to C3, and negative writing as shown in any of FIGS. 2B to 2D is performed between the terminals CB while the control transistor QC remains on. The voltage VW is applied to precharge the read charge to the buffer capacitor CR.
[0058]
Next, the control transistor QC is turned off so that the terminals A and B have the same potential and are written in the storage capacitor CM. Thereafter, the control transistor QC is turned on to short-circuit the storage node NS to release the stored charge.
[0059]
In this manner, the storage state corresponding to “1”, “2”, or “3” can be stored in the storage capacitor CM.
[0060]
Next, the reading operation of this circuit will be described.
[0061]
FIG. 3 is an operation diagram for explaining the basic read operation of the circuit of this embodiment. First, the control transistor QC is turned on to release the charge accumulated in the storage node NS from the terminal C. Thereafter, the control transistor QC is turned off again to make the storage node NS floating, and then the data is read through the buffer capacitor CR having the capacities C1 to C3 as shown in FIGS. 3 (a) to 3 (c). A voltage VR is applied. At this time, the voltage induced in the storage node NS changes according to the stored polarization “0” to “3”.
[0062]
For example, as shown in FIG. 3A, when the storage state is “0”, the read transistor QREAD is turned on through the buffer capacitor CR having any capacitance of C1 to C3.
[0063]
If the storage state is “1” as shown in FIG. 3B, the read transistor QREAD is turned off only through the buffer capacitor CR having the capacity of C3, and the other C2, It is turned on when the buffer capacitor CR having the capacity of C3 is passed.
[0064]
In this manner, by providing the buffer capacitor CR having three types of capacitance, it becomes possible to determine the quaternary storage state. Of course, three read operations are not necessarily required. First, the upper bits “0”, “1”, “2”, and “3” are discriminated by using a buffer capacitor CR having a capacity of C2. Depending on the result, a buffer capacitor CR having a capacity of C1 or C3 can be used to discriminate between “0” and “1”, or “2” and “3”.
[0065]
Next, as a modified example of the present embodiment, a configuration in which a ferroelectric capacitor is employed as the buffer capacitor CR instead of the paraelectric capacitor will be described.
[0066]
FIG. 4 is a conceptual diagram showing the main configuration of the nonvolatile multilevel storage device according to this modification. FIG. 5 is a write operation diagram based on this circuit, and FIG. 6 to FIG. 7 are read operation diagrams.
[0067]
The configuration of this modification is substantially the same as the configuration of FIG. 1 except that a ferroelectric capacitor is used instead of a paraelectric capacitor as the buffer capacitor CR, as illustrated in FIG.
[0068]
The operation is also almost the same as the write and read operations of the circuit illustrated in FIG. The only difference is that immediately before the precharge, write, and read voltage application operations are performed, the control transistor QC is turned on, and the buffer capacitor CR is supplied with an inverted voltage in a direction opposite to the precharge, write, and read operation voltages. It is necessary to turn off the control transistor and apply the storage node NS to the floating state after the voltage is applied between the terminals CB and returned to the same potential between the terminals CB. Except for this, the write operation corresponding to the multi-value as shown in FIG. 5 and the read operation corresponding to the multi-value as shown in FIGS. 6 to 7 can be performed in the same manner.
[0069]
Further, when a ferroelectric capacitor is used as the buffer capacitor CR, a rewrite operation after reading can be easily performed.
[0070]
FIG. 8 is an operation diagram corresponding to the read / rewrite operation when the polarization state “2” is stored in the storage capacitor CM. The charge read from the storage capacitor CM to the buffer capacitor CR by applying the read voltage VR is easily returned to 0 by applying the rewrite voltage VW in the reverse direction, so that the polarization “2” which is the initial state can be easily obtained. Can be rewritten. In particular, when the squareness ratio of the buffer ferroelectric capacitor CR is good, accurate rewriting can be performed without precisely controlling the rewriting voltage VW.
[0071]
The conceptual configuration, basic write operation, and read operation of the nonvolatile multilevel storage device of this embodiment have been described above.
[0072]
Next, a specific example of the buffer capacitor block for making the capacitance of the buffer capacitor CR variable will be described.
[0073]
FIG. 9 shows a configuration example of a variable capacity buffer capacitor block including a plurality of buffer capacitors connected in series or in parallel.
[0074]
First, FIG. 9A illustrates a configuration in which a plurality of buffer paraelectric capacitors CR0, CR1, CR2,. In this configuration, by appropriately turning on the buffer capacitor selection transistors QR0, QR1, QR2,..., A plurality of buffer capacitors CR0, CR1, CR2,. be able to.
[0075]
FIG. 9B illustrates a configuration in which a plurality of buffer ferroelectric capacitors CR0, CR1, CR2,. In this configuration, a plurality of buffer ferroelectric capacitors CR0, CR1, CR2,... Are arbitrarily connected in parallel by appropriately turning on buffer capacitor selection transistors QR0, QR1, QR2,. The capacity can be increased.
[0076]
In FIG. 9 (c), a plurality of buffer capacitors CR0, CR1, CR2,... And selection transistors QR0, QR1, QR2,. An example of a so-called chain connection) is shown. In this buffer capacitor block, a plurality of buffer paraelectric capacitors CR0, CR1, CR2,... Are arbitrarily connected in series by appropriately turning off the selection transistors QR0, QR1, QR2,. The capacity can be reduced.
[0077]
As described above, the basic configuration of the nonvolatile multi-value storage device of this embodiment is a multi-value memory cell including a storage capacitor CM, a variable-capacitance buffer capacitor CR, and a read transistor QREAD. Compared to a 2-bit FRAM memory cell consisting of one transistor and one capacitor, the area occupied by the memory cell is somewhat larger.
[0078]
On the other hand, by replacing the storage capacitor CM with a storage cell block including a plurality of storage unit cells, the area occupied by the memory cell per storage capacitor can be drastically reduced. By selecting appropriately, the advantage that random access is possible can be simultaneously held.
[0079]
FIG. 10 is a conceptual diagram showing a specific example in which the storage capacitor CM is configured by a memory cell block including a plurality of storage capacitors.
[0080]
That is, FIG. 5A shows a unit cell in which selection MOS transistors QM0, QM1, QM2,... And storage ferroelectric capacitors CM0, CM1, CM2,. It is an example of a structure of the memory cell block CM connected to SBL in parallel. The target storage capacitors CM0, CM1, CM2,... Can be selected by turning on the selection transistors QM0, QM1, QM2,... Of the unit cells to be written or read in the cell block. In this circuit, a block selection transistor QMS is provided so that the entire memory cell block can be selected.
[0081]
On the other hand, in FIG. 10B, a plurality of unit cells in which selection MOS transistors QM0, QM1, QM2,... And storage ferroelectric capacitors CM0, CM1, CM2,. This is a configuration example of a memory cell block (referred to as “chain cell block”) CM. A target storage capacitor can be selected by turning off the selection transistor of a unit cell to be written or read in the cell block and turning on all other selection transistors.
[0082]
The ferroelectric capacitor CM for memory is made of a ferroelectric film of PZT (lead zirconate titanate), SBT (strontium bismuth titanate), or epitaxial BSTO (barium strontium titanate). Thin film capacitors can be used. In terms of stability and film thickness, epitaxial BSTO capacitors are particularly excellent.
[0083]
As the buffer capacitor CR, a paraelectric capacitor using silicon oxide, tantalum oxide, or BSTO, or the above-described ferroelectric capacitor can be used. Of course, a wiring capacitance such as a sub-bit line capacitance can be used as a buffer capacitor.
[0084]
(Second Embodiment)
Next, as a second embodiment of the present invention, a configuration in which a buffer capacitor having a constant capacitance is provided and a substantially constant write / read voltage is applied a plurality of times corresponding to multiple values will be described.
[0085]
FIG. 11 is a conceptual diagram showing the main configuration of the nonvolatile multilevel storage device of this embodiment.
[0086]
That is, in the present embodiment, the storage ferroelectric capacitor CM and the buffer dielectric capacitor CR are connected in series, and the gate electrode of the read transistor QREAD is further connected to the storage node NS that is the connection portion thereof. The main electrode of the control transistor QC is connected. The gate of the control transistor QC is connected to a multiple-time write control circuit CW, and a gate control signal for performing the operation described in detail below is appropriately input.
[0087]
Next, the write operation of the circuit of this embodiment will be described.
[0088]
FIG. 12 is an operation diagram showing the write operation of the circuit of FIG.
[0089]
First, the control transistor QC is turned on, and as shown in FIG. 12A, a positive write voltage VW0 that is equal to or higher than the inversion voltage is applied between the terminals A and C, and then, By returning the voltage to 0, a memory state “0” completely polarized in the positive direction can be obtained.
[0090]
After writing “0”, in order to write one of the memory states “1” to “3” corresponding to partial polarization or negatively inverted polarization, the control transistor QC is turned off and the storage node NS is floated. The negative write voltage VW as shown in FIG. 12B is applied between the terminals A and B, and then the write voltage is returned to 0, the control transistor QC is turned on, and the storage node NS is short-circuited. The sequence of releasing the accumulated charge is repeated several times. This series of operation control is executed based on a control signal from the multiple-time write control circuit CW. In this way, as shown in FIGS. 12B to 12D, storage states corresponding to “1”, “2”, and “3” can be achieved in order.
[0091]
The writing method using precharge is exactly the same.
[0092]
First, according to the same sequence as described above, as shown in FIG. 12A, after writing “0”, the control transistor QC remains on as shown in FIG. 13B between the terminals CB. A negative write voltage VW is applied to precharge read charges to the buffer capacitor CR. Based on the control signal from the multiple write control circuit CW, the control transistor QC is turned off to bring the terminals A and B to the same potential, the control transistor QC is turned on and the storage node NS is short-circuited. By repeating the sequence of releasing charge a plurality of times, as shown in FIGS. 12B to 12D, storage states corresponding to “1”, “2”, and “3” can be achieved in order.
[0093]
Such a series of operations is also executed based on a control signal from the multiple-time write control circuit CW.
[0094]
Next, a plurality of read operations in the circuit illustrated in FIG. 11 will be described with reference to an operation diagram of FIG.
[0095]
First, the control transistor QC is turned on to release the charge accumulated in the storage node NS from the terminal C, the control transistor QC is turned off and the storage node NS is floated, and then as shown in FIG. A second read voltage VR is applied. At this time, the voltage induced in the storage node NS changes according to the polarizations “0” to “3” stored in the storage capacitor CM. If the memory state is “0” or “2”, the read transistor QREAD is turned on. Only in the memory state “3”, the read transistor QREAD is turned off.
[0096]
After that, by returning the applied voltage to 0, the polarization for one time is read, the memory state “0” changes to “1”, “1” changes to “2”, “2” changes to “3” To do.
[0097]
Thereafter, as illustrated in FIGS. 13B to 13C, the storage state of the storage capacitor CM can be sequentially determined by repeating the above-described operation.
[0098]
These multiple read operations may be performed by a control signal from the multiple write control circuit CW, or a read control circuit (not shown) may be provided separately from the control circuit CW.
[0099]
As described above, according to the present embodiment, since the write / read operation is performed a plurality of times, the operation speed of the storage device is slowed down by the multi-value multiplexing, but the conventional binary write / read operation is slowed down. There is a great merit that a large threshold voltage range can be obtained by the low voltage operation similar to the case.
[0100]
(Third embodiment)
Next, as a third embodiment of the present invention, a configuration in which a buffer capacitor having a constant capacity is provided and a write / read voltage corresponding to multiple values is applied to this capacitor will be described.
[0101]
FIG. 14 is a conceptual diagram illustrating the main configuration of the nonvolatile multilevel storage device according to this embodiment.
[0102]
That is, also in the present embodiment, the storage ferroelectric capacitor CM and the buffer dielectric capacitor CR are connected in series, and the gate electrode of the read transistor QREAD is further connected to the storage node NS which is the connection portion thereof. The main electrode of the control transistor QC is connected. A write voltage control circuit CA is connected to one end B of the buffer capacitor CM and the gate of the control transistor QC, and a gate control signal for performing the operation described in detail below is appropriately input.
[0103]
FIG. 15 is an operation diagram for explaining the write operation of the circuit of FIG.
[0104]
That is, first, the control transistor QC is turned on, and a positive write voltage VW0 higher than the inversion voltage is applied to the memory ferroelectric capacitor CM between the terminals A and C as shown in FIG. Further, by returning the voltage to 0, it is possible to obtain a memory state “0” that is completely polarized in the positive direction.
[0105]
Next, memory states “1” to “3” corresponding to partial polarization or negatively inverted polarization are written. Specifically, after writing “0” into the storage capacitor CM according to the above sequence, the control transistor QC is turned off, the storage node NS is brought into a floating state, and the terminal AB is shown in FIG. It can be achieved by applying negative write voltages VW1 to VW3 as exemplified in (d).
[0106]
In a series of operations, on / off control of the control transistor QC and control of the magnitude of the write voltage VW are executed by the write voltage control circuit CA.
[0107]
On the other hand, the same applies to the case of employing a precharge writing method.
[0108]
That is, after “0” is written according to the above sequence, negative write voltages VW1 to VW3 as shown in FIGS. 15B to 15D are applied between the terminals CB while the control transistor QC remains on. By applying the precharge charge to the buffer capacitor and turning off the control transistor so that the terminals A and B have the same potential, the partial polarization state is exactly the same as when the direct read voltage is applied. Writing to can be achieved.
[0109]
Next, a reading operation in the circuit of FIG. 14 will be described.
[0110]
FIG. 16 is an operation diagram for explaining a read operation of the circuit of FIG. In FIG. 16, the voltage indicated as “VT” represents the threshold voltage of the read transistor QREAD, and the read transistor is turned on at a voltage equal to or higher than VT, and turned off in the following.
[0111]
First, the control transistor QC is turned on to release the charge accumulated in the storage node NS from the terminal C. Thereafter, the control transistor QC is turned off to make the storage node NS floating, and then the read voltages VR1 to VR3 are sequentially applied as shown in FIGS. At this time, the voltage induced in the storage node NS changes according to the stored polarization “0” to “3”.
[0112]
For example, as shown in FIG. 16A, if the storage state is “0”, the read transistor QREAD is turned on regardless of the voltage VR1 to VR3. Further, as shown in FIG. 16B, if the memory state is “1”, the read transistor QREAD is turned off only when the voltage VR1 is applied, and the other voltages VR2 and VR3 are applied. Turns on. A sequence of a series of operations is performed by the write voltage control circuit CA or a control circuit provided separately.
[0113]
In this way, it is possible to determine the quaternary storage state by applying a three-level read voltage. Of course, three read operations are not necessarily required. First, VR2 is applied to discriminate upper bits “0”, “1” and “2”, “3”, and VR1 is determined according to the result. Alternatively, it is possible to apply VR3 to discriminate between “0” and “1” or “2” and “3”.
[0114]
The basic configuration of the present invention has been described above as the first to third embodiments of the present invention. Next, first to third embodiments of the present invention will be described with reference to the drawings. In the drawings referred to in the following description, the same or similar elements are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones. Therefore, specific thicknesses and dimensions should be appropriately determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.
[0115]
Example 1
FIG. 17 is a conceptual diagram showing the circuit configuration of the main part of the nonvolatile multilevel storage device according to the first example of the present invention. In this memory device, a ferroelectric capacitor is used as a memory capacitor and a buffer capacitor.
[0116]
As shown in FIG. 17, the memory device according to this embodiment includes a plurality of selection MOS transistors QM0, QM1, QM2, QM3,..., QM15 connected in series, and a common main electrode of these selection transistors. A chain type memory cell block composed of a plurality of memory ferroelectric capacitors CM0, CM1, CM2, CM3,..., CM15 connected in parallel to each other, and a block selection connected to the end of the memory cell block A transistor QBS, a plurality of buffer selection transistors QR0, QR1, QR2 connected in series, and a plurality of buffer ferroelectric capacitors CR0, CR1, CR2 connected to each common main electrode of the buffer selection transistors; NAND type buffer cell block consisting of, and the connection point between the memory cell block and the buffer cell block Constitutes at least it includes the memory cell blocks and a read transistor QREAD having a gate electrode connected to a storage node NS as a basic unit.
[0117]
Each of the storage capacitors CM0, CM1, CM2, CM3,..., CM15 is disposed opposite to the first electrode connected to the first main electrode of the memory cell selection transistor. And at least a second electrode connected to the second main electrode of the selection transistor and a ferroelectric thin film sandwiched between the first and second electrodes. In addition, each of the buffer capacitors CR0, CR1, and CR2 is disposed opposite to the first electrode connected to the common main electrode of the buffer cell selection transistor, and is connected to the plate line PL. At least a second electrode and a ferroelectric thin film sandwiched between the first and second electrodes.
[0118]
A plurality of the chain type storage cell columns are arranged in a matrix. Word lines WL0, WL1, WL2, WL3,..., WL15 are connected to the gate electrodes of the memory cell selection transistors QM0, QM1, QM2, QM3,.
[0119]
Similarly, word lines RL0, RL1, and RL2 are connected to the gate electrodes of the buffer cell selection transistors QR0, QR1, and QR2. A read power line VL is connected to one main electrode of the read transistor QREAD of each memory cell block, and a read output line SL is connected to the other main electrode.
[0120]
FIG. 18 is a conceptual diagram showing a connection relationship with peripheral circuits. Word lines WL0, WL1, WL2, WL3,..., WL15 of each memory cell are used as a row decoder, and word lines RL0, RL1, RL2 of each buffer cell are used as a multi-bit decoder, and each bit line BL0, BL1,. Are connected to a column decoder.
[0121]
In the circuit configuration shown in FIGS. 17 and 18, in order to select a desired memory cell indicated by the intersection of BLx (x = 0, 1) and WLy (y = 0, 1, 2,..., 15), All the word lines other than WLy are set to “1 (high level)”, all the selection transistors other than QMy are turned on, the word line WLy is set to “0 (low level)”, the selection transistor Qmy is turned off, and a potential is applied to BLx. Achieved by adding.
[0122]
In order to select each buffer capacitor CR0 in the buffer cell block, all the word lines from RL0 to WLz are set to “1 (high level)” and all the buffer cell selection transistors from QR0 to QRz are turned on. Further, this is achieved by setting the word line RLz + 1 to “0 (low level)” and turning off the buffer cell selection transistor QRz + 1.
[0123]
FIG. 19 is a timing chart showing the read / write sequence of the storage device of this embodiment.
[0124]
First, before the read / write operation is performed, the polarization operations of all buffer ferroelectric capacitors CR0, CR1, and CR2 are performed. That is, after the bit line BLx is set to the high level and the block selection transistor QBS is turned on, the buffer cell selection transistors QR0, QR1, and QR2 are turned on to polarize the buffer ferroelectric capacitors CR0, CR1, and CR2.
[0125]
Next, the memory cell selection transistor QMy of the memory cell to be selected is turned off, the storage node is brought into a floating state, the bit line BLx is set to the low level, and the plate line PL is set to the high level, so that multilevel reading is sequentially performed.
[0126]
That is, first, when the transistor QR0 of the buffer cell 0 is turned on, the stored value is “0” if the read transistor QREAD is turned on, “1” if QR1 is read on, and “1” if QR2 is read on. It can be seen that it is “3” if the read transistor QREAD is off.
[0127]
Next, rewriting to the storage capacitor CMy is performed by setting the bit line BLx to the high level and the plate line PL to the low level, and returning the charge read to the buffer capacitor to the storage capacitor.
[0128]
FIG. 20A is a plan view of an essential part of the nonvolatile multi-value storage device of this example, and FIG. 20B is a cross-sectional view taken along the line BB ′ of FIG. Is a conceptual diagram showing only the lower layer.
[0129]
One block connected to the bit line includes 16 storage cells, a read transistor QREAD, and 3 buffer cells. Memory cell size is 4F ² The area other than the memory cells per block is 34F. ² Therefore, (4 + 34/32) F per memory cell ² become. In this embodiment, the ferroelectric capacitor is 20 μC / cm. ² It was found that even if 32 memory cells were connected in series, the device with stable remanent polarization was used. Therefore, 5.9F per memory cell ² 1.59F per bit ² It became the size of.
[0130]
Further, as shown in FIG. 20B, the memory device of this example is configured by an n-MOS transistor formed on a silicon substrate. The main electrode region of each of the memory cell selection transistors QM0, QM1, QM2, QM3,..., QM15 has storage capacitors CM0, CM1, CM2, CM3 made of a lower electrode LE, an upper electrode TE and a ferroelectric film. ... CM15 is formed. Similarly, buffer capacitors CR0, CR1, and CR2 each formed of a lower electrode LE, an upper electrode TE, and a ferroelectric film are formed in the main electrode region of each buffer cell selection transistor QR0, QR1, and QR2.
With such a circuit configuration, the operation of a highly integrated non-volatile multilevel memory could be confirmed.
[0131]
(Example 2)
FIG. 21 is a conceptual diagram showing the circuit configuration of the main part of the nonvolatile multilevel storage device according to the second embodiment of the present invention. In this memory device, a ferroelectric capacitor is used as a memory capacitor, and a paraelectric capacitor is used as a buffer capacitor.
[0132]
As shown in FIG. 21, the memory device according to this embodiment includes a plurality of selection MOS transistors QM0, QM1, QM2, QM3,..., QM15 connected in parallel, and main electrodes of these selection transistors. A memory cell block composed of a plurality of memory ferroelectric capacitors CM0, CM1, CM2, CM3,..., CM15 connected in series to each other, a buffer cell transistor QR, and main electrodes of these buffer cell transistors And at least a read transistor QREAD having a gate electrode connected to a storage node SN that is a connection point between the memory cell block and the buffer cell. The memory cell block is configured as a basic unit.
[0133]
Each of the storage capacitors CM0, CM1, CM2, CM3,..., CM15 is disposed opposite to the first electrode connected to the first main electrode of the memory cell selection transistor. And at least a second electrode connected to the storage node and a ferroelectric thin film sandwiched between the first and second electrodes. The buffer capacitor CR includes a first electrode connected to the main electrode of the buffer cell selection transistor, a second electrode disposed opposite to the first electrode and connected to the storage node, and these And at least a dielectric thin film sandwiched between the first and second electrodes.
[0134]
A plurality of memory cell blocks are arranged in a matrix. Word lines WL0, WL1, WL2, WL3,..., WL15 are connected to the gate electrodes of the memory cell selection transistors QM0, QM1, QM2, QM3,.
[0135]
Similarly, a word line RL is connected to the gate electrode of the buffer cell transistor QR. A word line CL is connected to the gate electrode of the control transistor QC. A read power line VL is connected to one main electrode of the read transistor QREAD of each memory cell block, and a read output line SL is connected to the other main electrode.
[0136]
FIG. 22 is a conceptual diagram showing a connection relationship with peripheral circuits. Word lines WL0, WL1, WL2, WL3,..., WL15 of each memory cell are used as row decoders, word lines RL of buffer cells and word lines CL of control transistors are used as multi-bit decoders, and bit lines BL0, BL1 ,... Are connected to a column decoder.
[0137]
In the circuit configuration shown in FIGS. 21 and 22, in order to select a desired memory cell indicated by the intersection of BLx (x = 0, 1) and WLy (y = 0, 1, 2,..., 15), All the word lines other than WLy are set to “0 (low level)”, all the selection transistors other than QMy are turned off, the word line WLy is set to “1 (high level)”, the selection transistor Qmy is turned on, and a potential is applied to BLx. Achieved by adding.
[0138]
FIG. 23 is a timing chart showing the read sequence of the storage device of this embodiment.
[0139]
In order to perform reading, the selected bit line BLx is set to the high level and the plate line 0PL0 is set to the low level, and multi-value reading is sequentially performed.
[0140]
First, the memory cell selection transistor QMy and the reference cell transistor RL to be selected are turned on and the first reading is performed. If the reading transistor QREAD is turned on, the stored value can be determined to be “3”. Next, the control transistor is turned on, the storage node is shorted to release the first read charge, and then floated again, and the memory cell selection transistor QMy and the reference cell transistor RL are turned on to turn on the second time. When reading is performed and the reading transistor QREAD is turned on, the stored value can be determined to be “2”. The same sequence is repeated, and it is understood that the stored value is “1” if the reading transistor QREAD is turned on even in the third reading, and “0” if it is turned off.
[0141]
FIG. 24 is a timing chart showing the write sequence of the storage device of this embodiment.
[0142]
In order to perform writing, first, the selected bit line BLx is set to the low level and the plate line 1PL1 is set to the high level, and a voltage is directly applied to the storage capacitor to write “0”. Next, in exactly the same manner as the read operation, the selected bit line BLx is set to the high level, the plate line 0PL0 is set to the low level, and “1” and “2” are sequentially written.
[0143]
FIG. 25A is a plan view of the main part of the nonvolatile multi-value storage device of this example, and FIG. 25B is a cross-sectional view taken along the line BB ′ of FIG. Is a conceptual diagram showing only the lower layer.
[0144]
In one block connected to the bit line, 16 storage cells, a read transistor QREAD, a buffer cell, and a control transistor are included. Memory cell size is 6F ² The area other than the memory cells per block is 24F ² Therefore, (6 + 24/16) F per memory cell ² become. In this embodiment, the ferroelectric capacitor is 20 μC / cm. ² Therefore, it was found that even if 16 memory cells are connected in series, the device operates stably. Therefore, 7.5F per memory cell ² 1.88F per bit ² It became the size of.
[0145]
Further, as shown in FIG. 25B, the storage device of this embodiment is configured by an n-MOS transistor formed on a silicon substrate. The main electrode region of each of the memory cell selection transistors QM0, QM1, QM2, QM3,..., QM15 has storage capacitors CM0, CM1, CM2, CM3 made of a lower electrode LE, an upper electrode TE and a ferroelectric film. ... CM15 is formed. Similarly, a buffer capacitor CR including a lower electrode LE, an upper electrode TE, and a dielectric film is formed in the main electrode region of the buffer cell transistor QR.
With such a circuit configuration, the operation of a highly integrated non-volatile multilevel memory could be confirmed.
[0146]
Example 3
In the third embodiment of the present invention, the basic memory cell block is exactly the same as in the second embodiment, but a variable voltage generator is added as a peripheral circuit, and a plurality of write / write operations in the second embodiment are performed. In this embodiment, multi-valued writing / reading by a variable voltage is possible instead of the reading method.
[0147]
FIG. 26 is a conceptual diagram illustrating a connection relationship with a peripheral circuit. Word lines WL0, WL1, WL2, WL3,..., WL15 of each memory cell are used as row decoders, word lines RL of buffer cells and word lines CL of control transistors are used as multi-bit decoders, and bit lines BL0, BL1 ,... Are connected to a column decoder. A variable voltage generator is connected to the multi-bit decoder and the column decoder.
[0148]
FIG. 27 is a timing chart showing the read / rewrite sequence of the storage device of this embodiment.
[0149]
To perform reading, first, the memory cell selection transistor QMy and the reference cell transistor QL to be selected are turned on. Next, when the first read voltage V1 is applied to the selected bit line BLx and the first read is performed, and the read transistor QREAD is turned on, the stored value can be determined to be “3”. Subsequently, the second read voltage V2 is applied to perform the second read. When the read transistor QREAD is turned on, the stored value is “2”, and the third read voltage V3 is added to perform the third read. It is understood that the stored value is “1” when the read transistor QREAD is turned on and “0” when the read transistor QREAD is turned off.
[0150]
In order to perform rewriting, the storage node is kept in a floating state, the selected bit line BLx is returned to the low level, the plate line 0PL0 is set to the high level, and the charge once read from the storage capacitor is written again. Can be achieved.
[0151]
With such a circuit configuration and read / write sequence, it was possible to confirm the operation of a highly integrated nonvolatile multilevel memory.
[0152]
【The invention's effect】
As described above in detail, according to the present invention, a semiconductor multilevel memory using a ferroelectric capacitor can be realized, and an ultra-highly integrated non-volatile multilevel memory device can be realized. It is.
[Brief description of the drawings]
FIG. 1 is an equivalent circuit diagram of a memory cell for explaining a basic configuration when a variable capacitor paraelectric capacitor for a buffer according to the present invention is used.
FIG. 2 is a schematic diagram for explaining a write operation when the variable capacitance paraelectric capacitor for a buffer according to the present invention is used.
FIG. 3 is a schematic diagram for explaining a read operation when the variable capacitance paraelectric capacitor for a buffer according to the present invention is used.
FIG. 4 is an equivalent circuit diagram of a memory cell for explaining a basic configuration in the case of using a variable capacitor ferroelectric capacitor for a buffer according to the present invention.
FIG. 5 is a schematic diagram for explaining a write operation in the case where the variable capacitor ferroelectric capacitor for buffer according to the present invention is used.
FIG. 6 is a schematic diagram for explaining a read operation when using a variable capacitor ferroelectric capacitor for a buffer according to the present invention.
FIG. 7 is a schematic diagram for explaining a read operation when using a variable capacitor ferroelectric capacitor for a buffer according to the present invention.
FIG. 8 is a schematic diagram for explaining read and rewrite operations when the variable capacitor ferroelectric capacitor for buffer according to the present invention is used.
FIG. 9 is an equivalent circuit diagram for explaining a basic configuration of a buffer cell block when the variable capacitor for buffer of the present invention is used.
FIG. 10 is an equivalent circuit diagram for explaining a basic configuration of a memory cell block according to the present invention.
FIG. 11 is an equivalent circuit diagram of a memory cell for explaining a basic configuration in the case where the multiple write control circuit of the present invention is provided.
FIG. 12 is a schematic diagram for explaining a plurality of write operations when the buffer paraelectric capacitor of the present invention is used.
FIG. 13 is a schematic diagram for explaining a plurality of read operations when the buffer paraelectric capacitor of the present invention is used.
FIG. 14 is an equivalent circuit diagram of a memory cell for explaining a basic configuration when the write voltage control circuit of the present invention is provided.
FIG. 15 is a schematic diagram for explaining a variable voltage writing operation when the buffer paraelectric capacitor of the present invention is used.
FIG. 16 is a schematic diagram for explaining a variable voltage read operation when the buffer paraelectric capacitor of the present invention is used.
FIG. 17 is a diagram showing a circuit configuration of main parts of the semiconductor memory device according to the first example of the present invention;
FIG. 18 is a diagram showing a circuit configuration of main parts including a peripheral circuit in the semiconductor memory device according to the first example of the present invention;
FIG. 19 is a timing chart showing a read / write sequence of the semiconductor memory device according to the first example of the present invention.
20A is a plan view and FIG. 20B is a cross-sectional view of a semiconductor memory device according to a first example of the present invention. FIG.
FIG. 21 is a diagram showing a circuit configuration of main parts of a semiconductor memory device according to a second example of the present invention;
FIG. 22 is a diagram showing a circuit configuration of main parts including a peripheral circuit in a semiconductor memory device according to a second example of the present invention;
FIG. 23 is a timing chart showing a read sequence of the semiconductor memory device according to the second example of the present invention.
FIG. 24 is a timing chart showing a write sequence of the semiconductor memory device according to the second example of the present invention.
25A is a plan view and FIG. 25B is a cross-sectional view of a semiconductor memory device according to a second example of the present invention.
FIG. 26 is a diagram showing a circuit configuration of main parts including a peripheral circuit in a semiconductor memory device according to a third example of the present invention;
FIG. 27 is a timing chart showing a read / write sequence of the semiconductor memory device according to the third example of the present invention.
FIG. 28 is a conceptual diagram showing a main part of a storage device disclosed by the present inventors.
FIG. 29 is a schematic diagram for explaining a multilevel write operation in a conventional example.
FIG. 30 is a schematic diagram for explaining an inherent PV hysteresis curve of a ferroelectric substance.
[Explanation of symbols]
CM memory capacitor
CR buffer capacitor
CREF reference capacitor
NS storage node
QC control transistor
QREAD transistor for reading

Claims (15)

A storage capacitor for storing data according to the polarization state of the ferroelectric;
A buffer capacitor connected in series to the storage capacitor;
A read transistor having a gate electrode connected to a storage node that is a connection point between the storage capacitor and the buffer capacitor;
A control transistor having a main electrode connected to the storage node;
With
A non-volatile multi-value storage device characterized in that a charge corresponding to a partial polarization state of the storage capacitor can be written by making the capacitance of the buffer capacitor variable.   By determining the amount of charge read to the storage node according to the capacity of the buffer capacitor using a connected read transistor, multi-value data including the partial polarization state of the storage capacitor 2. The nonvolatile multi-value storage device according to claim 1, wherein reading is performed.   2. The buffer capacitor has a capacitor block formed by connecting a plurality of capacitors in series or in parallel, and the capacitance is variable by selecting a part of the plurality of capacitors. The nonvolatile multi-value storage device according to 2. A storage capacitor for storing data according to the polarization state of the ferroelectric;
A buffer capacitor connected in series to the storage capacitor;
A read transistor having a gate electrode connected to a storage node that is a connection point between the storage capacitor and the buffer capacitor;
A control transistor having a main electrode connected to the storage node;
A multiple write control circuit;
With
The non-volatile circuit characterized in that the multiple-time write control circuit can form a partial polarization state and a complete polarization state of the storage capacitor by changing the number of times of writing of charges to the storage capacitor. Multi-value storage device. A storage capacitor for storing data according to the polarization state of the ferroelectric;
A buffer capacitor connected in series to the storage capacitor;
A read transistor having a gate electrode connected to a storage node that is a connection point between the storage capacitor and the buffer capacitor;
A control transistor having a main electrode connected to the storage node;
A multiple read control circuit;
With
The multiple-time read control circuit reads out multi-value data including the partial polarization state of the storage capacitor by changing the number of times of reading of charges from the storage capacitor. Value storage device. The charge is written to the storage capacitor by supplying a charge from the buffer capacitor to the storage capacitor after applying a precharge voltage to the buffer capacitor,
Applying a write voltage across the buffer capacitor and the storage capacitor connected in series,
The non-volatile multi-value storage device according to claim 1, wherein the non-volatile multi-value storage device is performed according to any one of the above. Read the charge from the storage capacitor to the buffer capacitor after applying a precharge voltage to the buffer capacitor,
Applying a read voltage across the buffer capacitor and the storage capacitor connected in series, or
The multi-value data including the partial polarization state of the storage capacitor is read by determining the operation state of the read transistor according to any one of the above. Nonvolatile multi-value storage device described in 1. A storage capacitor for storing data according to the polarization state of the ferroelectric;
A buffer capacitor connected in series to the storage capacitor;
A read transistor having a gate electrode connected to a storage node that is a connection point between the storage capacitor and the buffer capacitor;
A control transistor having a main electrode connected to the storage node;
A write voltage that can supply a charge from the buffer capacitor to the storage capacitor after applying a variable precharge voltage to the buffer capacitor to form a partial polarization state and a complete polarization state of the storage capacitor, respectively. A control circuit;
A non-volatile multi-value storage device comprising: 9. The non-volatile multi-value storage device according to claim 8 , wherein the precharge voltage or the read voltage is a voltage of two or more levels corresponding to any of multi-value data of three or more values. The storage capacitor has a plurality of storage cells connected in parallel to each other,
9. The non-volatile multilevel memory device according to claim 8 , wherein each of the plurality of memory cells includes a selection MOS transistor and a ferroelectric capacitor connected in series. The storage capacitor has a plurality of storage cells connected in series with each other,
The nonvolatile multi-value storage device according to claim 1, wherein each of the plurality of storage cells includes a selection MOS transistor and a ferroelectric capacitor connected in parallel. . The storage capacitor is
A plurality of selection MOS transistors connected in series with each other;
A storage capacitor having a storage electrode connected to each common main electrode of the selection transistors, a plate electrode facing the storage electrode, and a ferroelectric thin film sandwiched between the storage electrode and the plate electrode; ,
The nonvolatile multi-value storage device according to claim 1, wherein the non-volatile multi-value storage device is a NAND-type storage cell string.   The effective capacitance in the operating voltage range of the buffer capacitor is 1/10 or more and 2 or less of the effective capacitance in the operating voltage range of the storage capacitor. The nonvolatile multi-value storage device described.   The nonvolatile multilevel storage device according to claim 1, wherein the buffer capacitor is a ferroelectric capacitor.   The nonvolatile multi-value storage device according to claim 1, wherein the buffer capacitor is a paraelectric capacitor.

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