JPH0369099A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To prevent data from being erased and to improve reliability by reading out and rewriting the data in the main body of an EPROM by an internal EPROM control signal and an address signal. CONSTITUTION:When a refresh control signal REF is made '1', a ready signal RDY is made '0' and outputted by a control circuit 3. The control circuit 3 selects an internal address signal ADI from an internal address generating circuit 4 and selects an EPROM internal control signal CNI to be peculiarly generated. The signal CNI instructs a main body 1 of the EPROM to read out the data of the address designated by the signal ADI and the read data are stored in a data holding circuit 2 by an internal read control signal OEI. Next, the signal CNI instructs the main body 1 to write the data and the data of the circuit 2 are outputted by a signal WEI and written into the main body 1. Next, the circuit 4 is activated by an internal address generating signal ADG and the next internal address signal is generated. Afterwards, the read, write and internal address signals of the data are successively repeatedly generated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device that can be erased and electrically written.

[Conventional technology]

Conventionally, this type of semiconductor memory device (hereinafter referred to as EPROM)
Although it is a non-volatile memory, the stored data can be erased and written electrically, making it useful for small-volume, high-mix production, short TAT, etc., and its field of use is rapidly expanding. I've been doing it.

EPROMs can be roughly classified into two types depending on the data erasing method. One is UVE P ROM (ULTR), which erases data by irradiating the chip with ultraviolet light.
a violet erasable and ele
critically programmable re
ad-only me++ory), and the other is EEP R, which can electrically erase data.
OM (electrically erasable
and programmable raed-onl
y memory).

Both are based on the same principle in terms of writing data.

In a memory cell (MOS) transistor, a floating gate surrounded by an insulating film is provided between the control gate and the substrate, and the threshold voltage of the MOS transistor is changed by injecting charge into the floating gate. . As a result, by applying a constant voltage to the control gate and operating it, it is possible to obtain two states of conduction and non-conduction of this MOS transistor.
'1'.

Erasing data is nothing more than dissipating the charge on the floating gate described above by using ultraviolet light or high voltage.

[Problem to be solved by the invention]

The conventional semiconductor memory device described above has a structure in which data storage is achieved by charging the floating gate of the MOS transistor of the memory cell, so the floating gate is completely surrounded by an insulating film.
- Although a charged electric charge does not dissipate easily, it is inevitable that the electric charge will gradually be lost over time, and as the electric charge is lost, the threshold voltage will also change. , there is a drawback that eventually "311%"1" of the data becomes unidentifiable.

These data retention characteristics deteriorate as the temperature increases,
This poses a major problem in terms of reliability.

An object of the present invention is to provide a semiconductor memory device that can prevent data loss and improve reliability.

[Means to solve the problem]

The semiconductor memory device of the present invention is an EPROM that writes and reads data according to EPROM control signals and address signals.
The ROM main body and the data read from this EPROM main body are held according to an internal read control signal, and the held data is written to the EPROM main body according to an internal write control signal.
When the data holding circuit and the refresh control signal supplied to the main body are at active level, the EPROM internal control signals including the internal read control signal and the internal write control signal and the internal address generation signal are output, and the selection signal is
an internal address generation circuit that sequentially generates internal address signals according to the internal address generation signal; and an internal address generation circuit that selects the internal address signal when the selection signal is at a first level and outputs the internal address signal at a second level. a first selection circuit that selects an external address signal and outputs it as the address signal when the selection signal is at a first level, and selects the EPROM internal control signal when the selection signal is at a first level and an external read control signal when the selection signal is at a second level; , and a second selection circuit that selects an EPROM external control signal including an external write control signal and outputs it as the EPROM control signal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

This embodiment is an EPRO that writes and reads data according to the EPROM control signal CN and address signal AD.
The data on the data bus 7 read from the M main body 1 and this EPROM main body is held in accordance with the internal read control signal OEI, and the held data is transferred to the EPROM main body 1 via the data bus 7 in accordance with the internal write control signal WEI.
When the refresh control signal REF is at active level, the internal read control signal OEI
, EFROM internal control internal control signal CN section including internal write control signal WEI outputs the address generation signal ADG and sets the selection signal SL to the first level to set the ready signal RDY.
is set to the second level and output, and the refresh control signal R
When EF becomes inactive and the refresh end signal ED is input, the control circuit 3 outputs the selection signal SL at the second level and the ready signal RDY at the first level, and sequentially according to the internal address generation signal ADG. An internal address generation circuit 4 that generates an internal address signal ADI selects the internal address signal ADI when the selection signal SL is at the first level, selects the external address signal ADO when it is at the second level, and outputs it as the address signal AD. A first selection circuit 5 selects an EPROM internal control signal CNI when the selection signal SL is at a first level, and selects an EPROM external control signal CNO including an external read control signal and an external write control signal when the selection signal SL is at a second level. The configuration includes a second selection circuit 6 that selects and outputs the selected signal as an EPROM control signal CN.

Next, the operation of this embodiment will be explained.

First, the refresh control signal REF is at an inactive level “
When it is O''°, it is in a normal operating state.

At this time, the control circuit 3 inhibits the output operation of the data holding circuit 2 by at least the internal write control signal WEI, and selects the EPROM external control signal CNO and the external address signal ADO by the selection signal SL.

Therefore, the EPROM main body 1 can perform normal data reading or writing according to the EFROM external control signal CNO and external address signal ADO.

Next, the refresh control signal REF is at the active level “1”.
”, it enters the refresh operation state. Refreshing here refers to restoring the charge on the floating gate of the MOS transistor, which is a memory cell in the EPROM main body 1, to the initial state immediately after data writing. The control is as follows.

First, the control circuit 3 detects that the refresh control signal REF is
'', the ready signal RDY as a recognition signal is immediately changed to "O'" and output.Here, the ready signal RDY is
This semiconductor memory device is in refresh operation (“0
This is a signal indicating whether the control circuit 3
uses the selection signal SL to select the internal address signal ADI output from the internal address generation circuit 4, and also selects the control signal for the EPROM main body 1, that is, the EFROM internal control signal CNI, which is generated independently by the control circuit 3.

Next, the EPROM internal control signal CNI instructs the EPROM main body 1 to read data at the address specified by the internal address signal ADI, and the read data is sent to the data holding circuit 2 via the data bus 7 by the internal read control signal OEI. Stored by

Next, in the state of the same address, the EPROM internal control signal CNI instructs the EPROM main body 1 to write, and the internal write control signal WEI outputs the data held in the data holding circuit 2, and the data bus 7 The data is transferred to the EPROM main body 1 through the program and written therein.

After writing is completed, internal address generation circuit 4 is activated by internal address generation signal ADG to generate the next internal address signal. After that, sequential data reading,
Writing and generation of internal address signals are repeated.

The internal address generation circuit 4 detects the address at which the refresh operation should end, and when this condition is met, outputs a refresh end signal ED, and the control circuit 3 generates a ready signal RD based on this refresh end signal ED.
While returning Y to "'1°°, the EPROM control signal C
N and address signal AD are returned to their normal states from the outside.

If the refresh control signal REF is set to "0" when the ready signal RDY is "O" (refresh operation in progress), one refresh cycle at that time (reading and writing of data at the current address, and the next internal address signal After completion of the generation, the control circuit 3 outputs the ready signal RDY as "1" and returns the EPROM control signal CN and address signal AD to the normal operating state from the outside.The internal address generation circuit 4 at this time holds the address,
When the refresh control signal REF becomes 1' next time, the refresh operation will be restarted from this held address.

Note that the refresh control signal R used in this embodiment
The method of starting and stopping the refresh operation using EF and the ready signal RDY is only one example; for example, other methods include:
The refresh operation is activated by the input of an external pulse signal requesting refresh, and all addresses are refreshed at - times, or the control circuit 3 has a built-in timer and refreshes externally at regular intervals. It is also possible to apply a method of outputting a request signal and performing a refresh operation based on a refresh permission signal from the outside.

FIG. 2 is a circuit diagram showing a more specific example of the embodiment shown in FIG. 1, and FIG. 3 is a timing diagram of signals of various parts for explaining the operation of this embodiment.

First, the configuration will be explained with reference to FIG.

The EPROM body 1 is an EEFROM having a storage capacity of 8 bytes. Address signal AD is AO-
It becomes the 13-bit input of A12, and the data DT is Do~
It is 8 bits of D7 and can be used for both input and output. EPR
The OM control signal CN includes a chip select signal CE, a read control signal OE, and a write 1tilJ III signal WE, all of which become active at "O".

The data holding circuit 2 includes an 8-bit latch circuit 21 and an output control circuit 22 in accordance with the bit width of data in the EPROM body 1.

The control circuit 3 for refresh operation is composed of a timing generation circuit 31 and a ready signal control circuit 32.

The internal address generation circuit 4 has a binary 13-bit counter 41 corresponding to the number of bits of the address signal of the EPROM main body 1, and an I counter 41 that has a maximum value at a 13-bit address.
The decoding circuit 42 detects FFFH (hexadecimal).

The selection circuit 6 is composed of logic gates, and receives an external read control signal OEO, an external write control signal WE○, and an external chip.
EPROMPROM external control signal containing select signal CEO Internal read control signal OEI generated by CN port 3
, the EPROM internal control signal CNI including the internal write control signal WEI.

The selection circuit 5 is composed of output control circuits 51 and 52, and selects either the external address signal ADO or the internal address signal ADI generated by the internal address generation circuit 4.

Next, the operation of this embodiment will be explained with reference to FIG.

First, when the refresh control signal REF is "0", the ready signal control circuit 32 sets the ready signal RDY to "1" and outputs it.
The selection circuit 5 selects the external address signal ADO, and the selection circuit 6 also selects the external address signal ADO.
M external control signal CN input.

Further, at this time, the timing generation circuit 31 is in a stopped state, and each control signal that is outputted is also in an inactive state. Therefore, the data holding circuit 2 is disconnected from the data bus 7, and the internal address generating circuit 4 also stops operating.

Next, the refresh control signal REF changes from “O” to “1”
When the signal changes to “0”, the ready signal control circuit 32 immediately changes to “0”.
At the same time, the selection circuit 5 selects the output of the 13-bit counter 41, and the selection circuit 6 outputs the ready signal RDY as the chip select signal CE.
The internal read control signal O of the timing generation circuit 31 is used as the read control signal OE and the write control signal WE, respectively.
EI and internal write control signal WEI are selected.

These v and city signals from the timing generation circuit 31 are as follows:
It is generated as a periodic timing signal as shown in FIG.

First, the internal read control OEI becomes It OIT for a certain period of time, and the data D at the address value n is transferred from the EPROM main body 1.
T is read out and output to the data bus 7. In addition, the latch signal of the 8-bit latch circuit 21 internal read control signal OEI
The read data output to the data bus 7 is taken into the 8-bit latch circuit 21 during the "o" period.

Next, the internal write control signal WEI becomes “0” for a certain period at certain intervals, and the data DT on the data bus 7 becomes
For PROM body 1, the same address value n as when reading
Writing is performed in . The data DT on the data bus 7 at this time is the output of the 8-bit latch circuit 21, and its output control signal in this case is the internal write control signal WEI.

Next, the write time is counted by the counter built in the timing generation circuit 31, and after the write is completed, the internal address generation signal becomes "1", and the 13-bit counter 4
1 is activated and the next refresh cycle address (n+
1) internal address signal ADI is generated.

By repeating the above operations, when the address of the generated 13-bit internal address signal ADI reaches the maximum value IFFFH, the decoding circuit 42 outputs the refresh end signal ED, and at the timing of the internal address generation signal ADG, the ready signal RDY is output. is changed from “0” to °1, and E
PROM control signal CN to EPROM external control signal C
The refresh operation is completed by returning to NO.

〔Effect of the invention〕

As explained above, in the present invention, the internal EPROM control signal and the -address signal from the outside are
Generates control signals and address signals, and outputs these internal EPs.
By configuring the EPROM main body to read and rewrite data using ROM control signals and address signals, the EPROM main body can be refreshed, data loss can be prevented, and the reliability of written data can be improved. There is an effect that can be done.

Furthermore, with the present invention, EPROMs can be used in fields where EPROMs could not be used up until now, such as fields where the usage environment is high temperature for a long time or where high reliability of data is required over a very long period of time. This has the effect of expanding its uses.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a circuit diagram showing more specific parts of the embodiment shown in FIG. 1, and FIG. 3 is a block diagram showing an embodiment of the invention shown in FIG. FIG. 4 is a timing diagram of signals of various parts for explaining the operation of the example. 1... EPROM main body, 2... data retention circuit, 3
...control circuit, 4...internal address generation circuit, 5,
6...Selection circuit, 7...Data bus, 21...8
Bit latch circuit, 22... Output control circuit, 31...
- Timing generation circuit, 32... Ready signal control circuit, 41... 13-bit counter, 42... Decoding circuit, 51.52... Output control circuit.

Claims (1)

[Claims] The EPROM main body, which writes and reads data according to EPROM control signals and address signals, and this EPR
a data holding circuit that holds data read from the OM main body according to an internal read control signal and supplies the held data to the EPROM main body according to an internal write control signal; a control circuit that outputs an internal read control signal, an EPROM internal control signal including the internal write control signal, and an internal address generation signal, and outputs a selection signal at a first level; and an internal address signal that is sequentially output according to the internal address generation signal. and a first selection circuit that selects the internal address signal when the selection signal is at a first level, selects the external address signal when it is at a second level, and outputs it as the address signal. When the selection signal is at a first level, the EPROM internal control signal is selected, and when the selection signal is at a second level, an EPROM external control signal including an external read control signal and an external write control signal is selected as the EPROM control signal. A semiconductor memory device comprising a second selection circuit that outputs an output.