JPH04147492A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce a cycle time by terminating the selection of a memory cell in a prescribed timing without awaiting the delivery of a change of an external timing signal specifying selection / non-selection of memory access into a non-selection level, inactivating a sense amplifier and starting precharging. CONSTITUTION:A word driver WDRV and a sense amplifier SA activated once by the memory access are inactivated without awaiting the change of an external timing signal phiwdrv instructing selection / non-selection of semiconductor memory access into a disable level through an internal delay. Thus, the precharging of a bit line is started in an early timing by the share. Thus, while the required precharge time is secured, the cycle time is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory of a type in which a bit line to which dynamic memory cells are connected is precharged before the start of operation, such as a pseudo-static RAM (PS).
RAM; Pseude 5tatic Rand.

m Access Memory) and dynamic RA
This relates to a technique that is effective when applied to M, etc.

[Conventional contact]

In a semiconductor memory using a dynamic memory cell, the bit line to which the memory cell is connected is precharged before the start of a read operation, and the charge on the bit line is redistributed according to the amount of accumulated charge in the selected memory cell. Data is read by detecting and amplifying level changes with a sense amplifier. Therefore, in a data read operation in which the accumulated charge of the memory cell is redistributed between the bit line and the bit line, the accumulated charge information is destroyed, so the bit line amplification operation by the sense amplifier is not determined. The word line selection operation and sense amplifier amplification operation must be maintained until the original charge information is rewritten into the memory cell.

When the data read operation is completed, the bit line is precharged after completing the word line drive operation and sense amplifier amplification operation so that the stored charge information in the rewritten memory cell is not destroyed. The next access is only possible after waiting for the state to be restored.

Because of its information retention mechanism, dynamic RAM has a shorter cycle time (from the start of reading/writing to the next reading/writing) than the access time (the time from when a reading/writing instruction is given until the reading/writing is completed). It has a general property that the time required to start reading/writing is long.

Conventionally, operation timing control in such dynamic RAM involves sequentially internally delaying changes in external timing signals such as chip enable signals that define selection/non-selection of memory access operations and supplying them to each circuit block. Once activated by chip selection, the word driver and sense amplifier remain activated until the chip non-selection instruction is sequentially internally delayed and transmitted to the relevant circuit. The precharging operation of the bit line etc. is started only after it is deactivated.

An example of a document describing DRAM is "LSI Handbook", published by Ohmsha on November 30, 1980, pages 486 to 499.

[Problem to be solved by the invention]

However, according to studies conducted by the present inventors, there is an internal delay in the chip non-selection instruction to deactivate the word driver and sense amplifier before the bit line precharge operation starts during the chip non-selection period. They found that they had to wait for the process to complete, essentially wasting time in cycle time. For this reason, when trying to speed up the operation of a dynamic RAM whose cycle time is longer than the access time, it is possible to do this by shortening the precharge period, which has a relatively long margin of operation, but at least Since a certain amount of precharge time must be ensured, there is a limit to this, and it is not possible to fully satisfy the demands for faster operation or shorter cycle time.

An object of the present invention is to provide a dynamic semiconductor memory that can shorten cycle time.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, the memory cell selection operation is completed and the sense amplifier is disabled at a predetermined timing without waiting for the change of the external timing signal that defines the selection/nonselection of the memory access operation to the nonselection level to be transmitted. A timing generating means for activating and starting a precharge operation is employed in a dynamic semiconductor memory.

For example, in order to perform such timing control, a set/deactivation control for word drivers is required.
A reset logic, a set/reset logic for controlling the activation/deactivation of the sense amplifier, and a set/reset logic for controlling the activation/deactivation of the precharge circuit are provided, and for these, A reset signal for deactivating the sense amplifier and the word driver and a set signal for activating the precharge circuit are generated by respectively delaying the change of the external timing signal to the selection level, or It is possible to generate the amplification operation confirmation signal by delaying the detection of the amplification operation confirmation by the detection means for detecting the confirmation of the amplification operation of the sense amplifier.

[For production]

According to the above-mentioned means, the word driver and sense amplifier, once activated by a memory access operation, wait for the external timing signal that instructs the selection/non-selection of the semiconductor memory access operation to change to the disable level through an internal delay. It is deactivated without waiting for the transmission, and the bit line precharging operation is started at a correspondingly earlier timing. This achieves shortening of cycle time while securing the necessary precharge time.

〔Example〕

FIG. 1 shows a DRAM according to an embodiment of the present invention.

The circuit elements constituting each block in the figure are conventional CMO
8 (complementary MO8) manufacturing technology on a single semiconductor substrate, such as single crystal silicon. In the figures below, the MOSFET with an arrow added to the channel (back gate) section is of the q-P channel type, and is shown to be distinguished from the N-channel MO8FET with no arrow added.

In the DRAM of this embodiment, the memory array M-ARY
Although not particularly limited, it is a two-intersection (folded bit line) system, and n+1 sets of complementary bit lines Do-D (1 (symbol * indicates inverted or low enable) are arranged in the horizontal direction of the figure. (meaning)~Dn-Dn, m+1 word lines WO-Wm arranged vertically, and (n+1)X (m+1) arranged in a grid at the intersections of these complementary bit lines and word lines. memory cells.

Each memory cell of the memory cell array M-ARY is a so-called one-element type dynamic memory cell, and each memory cell has an information storage capacitor (hereinafter also simply referred to as storage capacitor).
It is composed of Cs and an address selection MO8FETQm. MO8FETQ for address selection of m+1 memory cells arranged in the same column of memory array M-ARY
The drain of m is connected to the corresponding complementary bit line Do -Do
! ~Dn-On + are alternately coupled to non-inverted signal lines or inverted signal lines with a predetermined regularity. Further, the gates of the address selection MO8FETQm of n+1 memory cells arranged in the same row of the memory array M-ARY are commonly coupled to the corresponding word lines WO to Wm, respectively. A predetermined cell plate voltage VPL is commonly supplied to the other electrode of the information storage capacitor Cs of each memory cell, that is, the cell plate.

Word lines WO to Wm forming memory array M-ARY
is coupled to the output terminal of the word driver WDRV, and is alternatively driven to the selection level by the output selection signal of the row address decoder RDCH. The word driver W
DRV is activated/deactivated by a timing signal φwdrv, and the row address decoder RDEC is activated/deactivated by a timing signal φrdee.

The row address decoder RDCR receives a complementary internal address signal ax of a predetermined plurality of bits from the address buffer ADB.
(Here, for example, a non-inverted internal address signal and an inverted internal address signal are collectively expressed as a complementary internal address signal ax. The same applies hereinafter) is supplied. Row address decoder RDEC is activated when timing signal φrdec is set to high level, decodes complementary internal address signal aX, and outputs a word line selection signal.

Word driver WDRV that receives this word line selection signal
is activated when the timing signal φwdrv is set to high level, and drives one word line designated by the word line selection signal to the selection level.

Address buffer ADB has external address signal ADR8.
is supplied and activated by the timing signal φadb.
Deactivation controlled.

Complementary bit lines D forming the memory array M-ARY
o-Do *~Dn-Dn * are each equipped with an N-channel type equalizing MO8FETQI and an N-channel type precharge MO supplying a level half of the power supply voltage vcc.
8FETQ2. Q3 are coupled together to form a precharge circuit PCG. Precharge circuit P
The operation of CG is controlled by the timing signal φpeg, and the timing signal φpC is controlled during the chip non-selection period.
By setting g to high level, the complementary bit line Do
- Precharge the Dot-Dn-Dn umbrella to about half the level of the power supply voltage vcc.

Complementary bit lines D forming the memory array M-ARY
O.DO* to Dn-Dn* are coupled on one side to the sense amplifier SA.

Sense amplifier SA is P channel MO8FETQIO
, Qll and N-channel MO8FET Q12. Q13
The basic configuration is a CMOS latch circuit consisting of: The input/output nodes of these latch circuits are respectively coupled to the non-inverting signal line and the inverting signal line of the corresponding complementary bit lines Do-Do* to Dn/Dn umbrella. In addition, the sense amplifier SA is supplied with the power supply voltage Vcc of the circuit via the P-channel drive MO8FET Q9, and the ground potential Vss of the circuit via the N-channel drive MO8FET'Q8, although this is not particularly limited. be done. Drive MO3
Timing signal φsa is applied to FETQ8 (7) gate I.
is supplied. Further, the gate of the drive MO8FETQ9 is connected to an inverter circuit INV of the timing signal φsa.
An inverted signal by I is provided. timing signal φsa
is normally set to a low level, and is set to a high level when a minute read signal output from a memory cell coupled to a word line selected in a DRAM chip selection state is established on a corresponding complementary bit line. . By setting the timing signal φSa to a high level, the drive MO8
FETs Q8 and Q9 are both turned on, activating sense amplifier SA all at once and putting it into operation.

In its operating state, the sense amplifier SA receives minute read signals output from the n+1 memory cells coupled to the selected word line via the corresponding complementary bit lines Do-DCI to Dn-Dn*. 9 amplification to produce a high level or low level binary readout signal. These two
The value read signal is rewritten into the corresponding memory cell when r) the RAM is placed in a read mode or a refresh cycle, and a refresh operation of stored data is performed. In other words, by selectively setting the word lines WO-Wm to a high-level selected state and activating the sense amplifiers SA all at once, the refresh operation of the dynamic memory cells can be realized.

Complementary bit lines DO and configuring memory array M-ARY
Do* to Dn-Dn* are coupled on the other hand to the corresponding switch MO8FET of column switch C8W. Column switch C8W connects complementary bit lines DO/D
n+1 pair of switches MO3FETQ36 provided corresponding to O*~Dn-DnII+. It is composed of Q37. One of these MO8FET switches is coupled to the corresponding complementary bit line, and the other is commonly connected to the non-inverted signal line CD and the inverted signal line CD* of the complementary common data line, respectively. The gates of each pair of switches MO8FET are connected in common, and each corresponding line selection signal YO-Yn is supplied from a column address decoder CDCR. As a result, each pair of switches MO8FET constituting the column switch C8W is turned on by the corresponding line selection signals YO to Yn being alternatively set to a high level, and a specified set of complementary bit lines and the common complementary bit line CD-CDI are selectively connected.

Note that the column address decoder CDCR is supplied with a complementary internal address signal ay of a predetermined plurality of bits from the address buffer ADB.

The column address decoder CDCR is selectively brought into operation when the timing signal φy supplied thereto is set to a high level. In this operating state, the column address decoder CDCR decodes the complementary internal address signal ay and the corresponding line selection signal YO-Y.
Alternatively, n is set to a high level.

The main amplifier MA is connected to the complementary common data line CD-CD umbrella.
The input terminals of the data buffer DIR are coupled together with the output terminals of the data manual buffer DIR.

The output terminal of main amplifier MA is further coupled to the input terminal of data output buffer DOB.

The main amplifier MA further amplifies the binary read signal outputted from the selected memory cell of the memory array M-ARY via the corresponding complementary bit line and complementary common data line CD-CDI, and outputs the binary read signal to the data output buffer DOB. to communicate. The data output buffer DOB is selectively activated when the DRAM is placed in a read operation mode;
In this operating state, the data output buffer DOB is
The memory cell read signal transmitted from main amplifier MA is output to the outside. The data human buffer DIO is
When the RAM is put into write operation mode.

The write data supplied from the outside is used as a complementary write signal, and the complementary common data line CD-CD1 is enabled for operation.
supply g.

Various internal timing signals of the DRAM are formed based on a chip enable signal CEP, a write enable signal WE, an output enable signal OE*, and a refresh enable signal RE* supplied from the outside. The write enable signal WE* is a signal that instructs a write operation at its low level, the output enable signal OE* is a signal that instructs a data output operation at its low level, and the refresh enable signal RE* is at its low level. This signal is used to instruct a refresh operation. A circuit block that inputs these signals and forms an internal timing signal is simply illustrated as TG in the figure. The chip enable signal CEm is a signal that instructs chip selection/non-selection, and is regarded as an external timing signal that defines the access cycle of the DRAM.

Next, the logic for forming the internal timing signal based on the chip enable signal CE* will be explained in detail.

The chip enable signal CE* is transmitted in a predetermined order to multiple stages of delay circuits DELL to DEL7, each having a predetermined delay time. Regarding the address buffer ADB, row address decoder RDEC, and column address decoder CDEC, a delay circuit DEL is provided.
The outputs of L, DEL2°DEL7 are used as they are as timing signals φadb, φrdec, and φy, and the level change of the chip enable signal CE* is delayed to determine the levels of the timing signals φadb, φrdeci, and φy. That is, the chip enable signal CE*
When the timing signal φadb is changed to a low level (or a high level), the timing signal φadb is changed to a high level (or a low level) after the delay time set in the delay circuit DELI has elapsed, and the timing signal φadb is changed to a high level (or a low level). The timing signal φrd is output after the delay time set in
ec is changed to high level (or low level), and after a predetermined delay time has elapsed, timing signal φy is changed to high level (or low level).

Note that the input of the delay circuit DEL7 is not particularly limited;
This is the output of the delay circuit DEL4.

On the other hand, word driver WDRV, precharge circuit PC
Regarding G and sense amplifier SA, corresponding timing signals φwdrv, φpQg+φSa are formed via set/reset logics 5RLI to 5RL3, respectively, and the output of the delay circuit is used as the set signal and reset signal. I am using it. For example, the set/reset logics 5RLL-8RL3 are constituted by set/reset type flip-flop circuits.

The set/reset logic 5RLL receives the set signal φs1 output from the delay circuit DEL3 and the reset signal φr1 output from the delay circuit DEL5, and sets the timing signal φWdrv to high level in the set state achieved by the high level set signal φs1. The timing signal φwdrv is asserted, and the timing signal φwdrv is negated to a low level in the reset state achieved by the reset signal φr1 at a high level. Therefore, the word driver WDRV activated based on the change of the chip enable signal CE* to low level is activated by the chip enable signal CE*.
In other words, it becomes possible to deactivate the chip enable signal CEIk at an early timing without waiting for the negation change of the chip enable signal CEIk to a high level.

The set/reset logic 5RL2 receives the set signal φS2 output from the delay circuit DEL4 and the reset signal φr2 output from the delay circuit DEL6, and sets the timing signal φSa to high level in the set state achieved by the high level set signal φS2. In the reset state achieved by the high level reset signal φr2, the timing signal φSa is negated to a low level. Therefore, the sense amplifier SA activated based on the change of the chip enable signal CE to low level is activated based on the change of the chip enable signal CE* to low level.
It becomes possible to deactivate the E umbrella at the required early timing without waiting for the negate change to the high level to be transmitted.

Also, the set/reset logic 5RL3 is a delay circuit DEL.
Set signal φS3 and reset signal φr output from 6
3, the timing signal φpQg is asserted to high level in the set state achieved by the high level set signal φs3, and the high level reset signal φr is asserted.
3, the timing signal φpcg is negated to a low level. The reset signal φr3 is not particularly limited, but the timing signal φadb or φrdec is used.

Therefore, the precharge circuit PCG whose operation has been deselected based on the change of the chip enable signal CEI to the low level is activated based on the change of the chip enable signal CEI to the low level. The precharge operation is enabled at the required early timing without waiting for the negation change to high level to be transmitted.

FIG. 2 shows an example of read operation timing of a DRAM.

When the chip enable signal CE* is asserted to a low level and placed in a chip selection state, in accordance with the level change, the timing signal φadb is set to a high level to activate the address buffer ADB, and the timing signal φrdec is set to a high level. row address decoder RDEC is activated, and then set signal φS1 is changed to high level and set/reset logic 5RLI is activated.
is in the set state and the timing signal φw is at high level.
word driver WDRV is activated by drv, thereby driving a predetermined word line specified by address signal ADR8 to the selection level. In the figure, the bit line precharge operation by the precharge circuit PCG is stopped by changing the reset signal φr3 to a high level at a timing synchronized with the change in the timing signal φrdec.

When a word line is driven to a selection level, a minute signal corresponding to the amount of accumulated charge in a memory cell whose selection terminal is coupled to the word line is applied to complementary bit lines Do, DO* to Dn, Dn*.
given to. Then, when the set signal φs2 is changed to high level and the set/reset logic 5RL2 is set, and the sense amplifiers SA are activated all at once by the high level timing signal φSa, this causes the complementary bit lines Do, Dos- The minute signal level difference between Dn and Dn+ is amplified by the sense amplifier SA.

At the timing when this amplification operation is determined, the timing signal φy is changed to high level, and the column address decoder CDEC activated thereby decodes the address signal ADR3, and a pair of column switches MO8FETQ36 . Q37 is turned on to transfer the data of one memory cell to complementary common data lines CD and C.
Give to Monkey D. This read data is amplified by main amplifier MA and outputted to the outside as read data DOUT.

According to this embodiment, when the main amplifier MA starts the amplification operation, the reset signal φr1 outputted from the delay circuit DEL5 is changed to a high level, and the set/reset logic 5RLI goes into the reset I~ state and the timing The signal φwdrv is inverted to a low μ level, the word driver WDRV is inactivated, and the memory cell selection operation is completed.

As is clear from FIG. 2, this operation is instructed by the internally delayed reset signal φr1 when the chip enable signal CEI changes to a low level, and in FIG. 2, the chip enable signal CE* then changes to a high level. Negate. The subsequent deactivation of the sense amplifier SA and the start of the precharge operation are also instructed by internally delaying the change of the chip enable signal CE to the low level. That is, the set/reset logic RS L 2 is reset by the high-level reset signal φr2 and set signal φS3 that are output at almost the same timing from the delay circuit DEL6 that receives the internal delay signal of the high-level change of the chip enable signal GE. and the set/reset logic R3L3 is set to the set state, whereby the timing signal φSa is inverted to low level, the sense amplifier SA is inactivated, and the timing signal φp is
cg is inverted to high level and precharge circuit PCG
A precharge operation is started. When the precharge operation is completed, the DRAM is returned to a state in which it can start the next memory cycle.

FIG. 3 shows an example of read operation timing in a conventional DRAM. The timing shown in the figure relates to a control form in which activation/deactivation control of internal circuits is performed simply by sequentially internally delaying changes in the chip enable signal for a required period of time and supplying them to each circuit block. The word driver and sense amplifier, once activated, are negated to high level in accordance with the change to high level of the word driver timing signal and sense amplifier timing signal, which are formed by sequentially internally delaying the change of the chip enable signal to low level. The changes in the chip enable signal that have been activated are also sequentially delayed internally and remain activated until the word driver timing signal and sense amplifier timing signal are inverted to low level, and only after this is deactivated. Pip I
~ Precharging of lines etc. starts.

Comparing FIG. 2 and FIG. 3, in the conventional case of FIG. 3, by the time the complementary bit line precharge operation is started during the chip non-selection period, which is the high level period of the chip enable signal, It is necessary to wait for an internal delay time until the chip enable signal changes to high level and the word driver timing signal and sense amplifier timing signal are inverted to the inactivation level, which essentially wastes time when the chip is not selected. period, which increases cycle time.

On the other hand, in the case of FIG. 2, the word driver WDRV and sense amplifier SA, once activated by the memory access operation, receive the change of the chip enable signal CE* to the disable level through an internal delay. The precharging operation on the complementary bit lines Do, Dos-Dn, and Dn+ is started at a correspondingly earlier timing, thereby reducing the cycle time while securing the necessary precharging time. It is possible to shorten the time.

FIG. 4 shows a DRAM according to another embodiment of the present invention.

The DRAM shown in the figure is different from the configuration shown in FIG. 1 in the delay input of the delay circuit DEL5. That is.

A detection means for detecting the confirmation of the amplification operation by the sense amplifier SA is provided, and the detection of the confirmation of the amplification operation by the detection means is used as an input to the delay circuit DEL5.

In this embodiment, the detection means is a P-channel type MO8FETQIO in the sense amplifier SA.

It is composed of a two-manual type NAND gate NAND that receives the common source voltage of Qll and the timing signal φadb, and an inverter INV2 that inverts the output. The output φdtc of the inverter INV2 is input to the delay circuit DEL5. activated t:/suf'/pSA (7)
Changes in the common source potential PP in MO8FETs QIO and Qll are caused by the sense amplifier SA as shown in Figure 2.
The level is raised in accordance with the progress of the amplification operation. At this time, the input logic threshold voltage of the NAND gate NAND is M
It is set near the common source voltage in O8FETQIO, Ql1. Therefore, sense amplifier SA
Immediately after the amplification operation is confirmed, the output φdtc of the inverter INV2 is inverted to high level and the delay circuit DEL
5, word driver WDRV and sense amplifier S at a predetermined timing synchronized with this timing.
A is deactivated and a precharge operation by the precharge circuit PCG is started.

In this embodiment as well, the word driver WDR once activated by the memory access operation is used as in the above embodiment.
V and sense amplifier SA are deactivated without waiting for the change of the chip enable signal CE to the disable level to be transmitted through an internal delay, and the complementary bit lines Do, DO* are activated at an earlier timing. ~Dn, the precharging operation of the Dn umbrella will start, so this will ensure the necessary precharging time and the cycle timer will start. q time can be shortened. In particular, in this embodiment, the completion of the amplification operation of the complementary pin 1 to line by the sense amplifier SA is detected, and at a predetermined timing synchronized with this, the word driver WDRV and the sense amplifier SA are deactivated, and the precharge circuit PCG is activated. Since the precharge operation is started, there is no need to secure a sufficient operation margin in advance and set the delay time, compared to the configuration shown in FIG. Cycle time can be further reduced. In the configuration of FIG. 1, delay circuit DEL5. The delay time of DEL6 etc. is optimized by taking a necessary operating margin by logic simulation or the like.

Although the invention made by the present inventor has been specifically described above based on examples, the present invention is not limited thereto and can be modified in various ways without departing from the gist thereof.

For example, although the above embodiment describes a non-address multiplex type DRAM, the present invention is not limited thereto;
It can also be applied to RAM. Furthermore, the set/reset logic is not limited to the R8 type flip-flop circuit, and other logics may also be employed. Further, the number of stages and arrangement of delay circuits are not limited to those in the above embodiments, and can be changed as appropriate. Furthermore, the common source voltage of the N-channel MOS FET may be used to confirm the amplification operation of the sense amplifier. Furthermore, the format of the memory cell is not limited to the one-transistor type. Furthermore, the refresh format may be auto-refresh or self-refresh. Furthermore, the memory array M-ARY may be configured by a plurality of memory mats. The common source voltage supply to the sense amplifier may be divided into several stages.

In the above description, the invention made by the present inventor was mainly applied to DRAM, which is the background field of application, but the present invention is not limited thereto, and includes, for example, pseudo-static RAM, etc. Various semiconductor memories with dynamic memory cells,
The present invention can be widely applied to various semiconductor integrated circuits such as logic LSIs such as microcomputers incorporating the semiconductor memory. The present invention can be applied to at least conditions that require shortening of the cycle time of dynamic memory.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In other words, during the period when the semiconductor memory operation is not selected by the external timing signal, by the time the precharging operation of the bit line etc. is started, the change in the disable level of the external timing signal has passed through the internal delay circuit to the word driver. There is no need to wait for the signal to arrive at the signal or sense amplifier, saving time that would have traditionally been wasted by waiting for such internal delays.
This has the effect of shortening the cycle time while ensuring the necessary precharge time.

In addition, a configuration is adopted in which the determination of the bit line amplification operation by the sense amplifier is detected, and at a predetermined timing synchronized with this, the word driver and the sense amplifier are deactivated, and the precharge circuit starts the precharge operation. This makes it unnecessary to secure a sufficient operating margin in advance and set the delay time, compared to a configuration in which the operation timing is exclusively defined by the delay time, so that the cycle time can be further shortened in this respect. There is an effect.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a DRAM according to an embodiment of the present invention. FIG. 2 is a timing chart of an example of a read operation in the DRAM of FIG. 1. FIG. 3 is a timing chart of an example of a read operation in a conventional DRAM. , FIG. 4 is a block diagram of a DRAM according to another embodiment of the present invention. M-ARY...Memory array, Qm...MO8 for selection
FET, Cs... Information storage capacitor, DO1Do
t~Dn, Dn'k...Complementary bit line, SA...Sense amplifier, PCG...Precharge circuit, WDRV
・Word driver, DELL to DEL7...Delay circuit, 5RLI to 5RL3...Set/reset logic, φ
sl, φs2. φs3...Set signal, φr1) φr
2. φr3-reset signal, φrdec. φwdrv, φsa, pcg'' timing signal, NA
ND...Nands gate, φdtc...detection signal.

Claims (1)

[Claims] 1) A bit line to which a dynamic memory cell is coupled, and a precharge circuit that precharges the bit line before starting a read operation, and according to the amount of accumulated charge of a selected memory cell. A semiconductor memory in which a sense amplifier detects and amplifies a level change in a bit line to which charge is to be redistributed, and a change to a non-select level of an external timing signal that defines selection/non-selection of a memory access operation is transmitted. 1. A semiconductor memory comprising timing generating means for terminating a memory cell selection operation, inactivating a sense amplifier, and starting a precharge operation at a predetermined timing without waiting for the 1st period. 2) The timing generation means includes: a set/reset logic for controlling activation/deactivation of a word driver for driving a selection terminal of a memory cell to be selected to a selection level; and activation of the sense amplifier. set/reset logic for controlling activation/deactivation of the precharge circuit; set/reset logic for controlling activation/deactivation of the precharge circuit; and activation based on a change of the external timing signal to a selection level. A reset signal to deactivate the activated word driver, a reset signal to deactivate the sense amplifier activated at a later timing than the word driver, and a reset signal to deactivate the activated sense amplifier with a timing later than that of the word driver, synchronized with the change of the external timing signal to the selected level. and delay means for generating a set signal for activating a precharge circuit that has been deactivated by delaying the change of the external timing signal to the selected level, respectively. The semiconductor memory according to claim 1, characterized in that: 3) The timing generating means includes: a set/reset logic for controlling activation/deactivation of a word driver for driving a selection terminal of a memory cell to be selected to a selection level; and activation of the sense amplifier. /set/reset logic for controlling activation/deactivation of the precharge circuit; set/reset logic for controlling activation/deactivation of the precharge circuit; detection means for detecting confirmation of amplification operation by the sense amplifier; A reset signal for deactivating a word driver activated based on a change in an external timing signal to a selected level, and a reset signal for deactivating a sense amplifier activated at a timing later than that of the word driver. and a set signal for activating the deactivated precharge circuit in synchronization with the change of the external timing signal to the selection level by delaying the detection of the amplification operation confirmation by the detection means. 2. The semiconductor memory according to claim 1, further comprising: means. 4) The semiconductor memory according to claim 3, wherein the detection means includes determination logic for determining the level of a power supply node of a sense amplifier constituted by a static latch circuit.