JPH04144242A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To simultaneously reduce both gate length and gate resistance, by a method wherein the boundary between a semiconductor active layer and an insulating layer is positioned in an aperture of photo resist subjected to gate-patterning. CONSTITUTION:On a semiconductor active layer 2, an insulating layer 8 whose etching rate is different from that of the layer 2 is formed. A photo resist 9 is patterned, which is used as a mask, and the layer 8 is etched. Source.drain electrode metal 30 is stuck on the whole surface by a vacuum evaporation method or the like, and the insulating layer 8 is left between a source and a drain by a lift-off method. After photo resist 10 is patterned, the insulating film 8 is etched by using the photo resist 10 as a mask, and the photo resist 10 is eliminated. Thereby a part where the semiconductor active layer 2 is exposed and a part where the insulating layer 8 exists are formed between the source and the drain. Gate-patterning is performed by a photolithography technique. In this process, an aperture part of photo resist 5 is made to overlap with the end portion of the insulating layer 8, and the boundary between the semiconductor active layer 2 and the insulating layer 8 is positioned in the aperture.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming a gate electrode of a gallium, arsenic field effect transistor (GcAs FET), etc.

[Conventional technology]

11 to 14 are cross-sectional views of a semiconductor device showing a conventional method for manufacturing a semiconductor device in order of steps.

In the figure, (1) a semiconductor substrate made of #i gallium arsenide, etc., (2) a semiconductor active layer formed on the semiconductor substrate (1), and (3) a drain formed on the semiconductor active layer (2). The electrode (4) is a source electrode formed on the semiconductor active layer (2), (5) is a photon resistor), (6) is a recess formed on the semiconductor active layer (2), and (7) is a recess (6). ), and (7o) is the gate electrode metal.

Next, the manufacturing method will be explained. As shown in Figure n,
A drain electrode (3) and a source electrode (4) are formed at a predetermined interval on a semiconductor active layer (2) formed on a semiconductor substrate (1).

Next, as shown in Figure 1, for forming the gate electrode (7),
After the photoresist (5) is applied over the entire surface, a wider opening is formed during photolithography. Next, as shown in Figure K13, the semiconductor active layer (2) is dug to a desired depth using a 7mm photoresist (5mm) as a mask to form a recess (6), and then the gate electrode metal (6) is deposited using a vacuum evaporation method or the like. 7o) on the entire surface. Apply photoresist (5o) using the lift-off method.
) and the unnecessary gate electrode metal (7o) on the photoresist (5) are removed, a gate Tt grandchild (7) is formed in the recess (6), and the semiconductor device is completed as shown in FIG.

[Problem to be solved by the invention]

Since the conventional semiconductor device manufacturing method is carried out as described above, in the photolithography process for forming the gate electrode, the photoresist is thicker in the region where gate buttering is performed, as shown in Fig. source electrode,
Since the opening is recessed relative to the photoresist on the drain electrode, the width of the opening is limited to about 0.3 μm in conventional contact exposure methods. In order to improve the performance of semiconductor devices, it is necessary to shorten the gate length Lg as shown in FIG. Obtaining the length Lg is a solid phase, and the cross-sectional shape of the gate electrode is tapered into a trapezoidal shape, so there is a problem that even if the gate length Lg can be shortened, the gate resistance will increase.

This invention was made to solve the above-mentioned problems, and even if the conventional photolithography technology is used, the gate length Lg! An object of the present invention is to obtain a method for manufacturing a semiconductor device that can reduce IM shrinkage and gate resistance.

[Means to solve the problem]

The method for manufacturing a semiconductor device according to the present invention includes forming a thin insulating layer made of a silicon nitride film, a non-doped semiconductor, etc. on a semiconductor active layer, and leaving a thin insulating layer between a north drain after forming a source electrode and a drain electrode. After that, the insulating layer between the source and drain is etched so that the desired amount remains on the drain side, and gate patterning is performed. A gate electrode is formed by forming a recess on the 0th order of patterning, followed by vapor deposition and step 7.0 [Function] The method for manufacturing a semiconductor device according to the present invention is to form a gate electrode between a source and a drain. Since the pattern is overlapped with the end of the remaining insulating layer, the gate length Lg is shortened even if the opening @L of the photoresist is about the same as before. Moreover.

When gate electrode metal is deposited on the entire surface using a vacuum evaporation method or the like to form a gate electrode, a pine mushroom-shaped gate electrode is obtained in which the part that contacts the semiconductor active layer is thin and the cross-sectional shape of the upper part is large, which reduces the gate length ILg. The gate resistance can be reduced.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. ji
There is no K1 diagram! FIG. 10 is a cross-sectional view of a semiconductor device showing a method for manufacturing a semiconductor device in order of steps, and in the figure,
(1)'(7) and (7o) are the same as those shown in the conventional examples shown in FIGS. 11 to 14, so their explanation will be omitted. (8) is an insulating layer, (9) and (K) are photoresists, and (3o) is a source/drain electrode metal.

Next, the manufacturing method will be explained.

First, in FIG. 1, nine semiconductor active layers (2) formed on a semiconductor substrate (1) are coated with a silicon nitride film (81Nx), a silicon-containing FM (8to2), and a silicon nitride film (81Nx), which has a different etching rate from the semiconductor active layer (2). Oxide film (Si
An insulating layer (8) made of a thin film of A/303 or a non-doped semiconductor is formed. In Figure 2, photoresist (9) is used to form the drain electrode.
is patterned, and the insulating layer (8) is etched using the photoresist (9) as a mask. Next, as shown in Fig. 3, a source/drain electrode metal (3o) is deposited on the entire surface by vacuum evaporation method, etc., and a photoresist (9
) and the source/drain electrode metal (30) on the photoresist (9) are removed to leave an insulating layer (8) between the source and drain as shown in FIG. Next, as shown in FIG. 5, the photoresist (G) is patterned.

iIl! As shown in FIG. 6, the insulating layer (8) is etched using the photoresist αQ as a mask to remove the photoresist (T). This creates an exposed portion of the semiconductor active layer (2) and a portion where the insulating layer (8) is present between the source and drain. Next, as shown in Figure $7, gate patterning is performed using the same conventional photolithography technique. At this time,
The opening of the photoresist (5) is made to overlap the end of the insulating layer (8) so that the boundary between the semiconductor active layer (2) and the insulating layer (8) is contained within the opening. After digging the semiconductor active layer (2) and forming a recess (6) as shown in Figure (8), gate electrode metal (7o) is coated over the entire surface by vacuum evaporation method as shown in Figures 1 to 9 After letting.

The photoresist (6) and the unnecessary gate electrode metal (7o) on the photoresist (5) are removed by the 7-to-7 method and fjf! A semiconductor device is completed as shown in FIG.

In addition.

In FIG. 10, the insulating layer (8) is left as is.

It may be removed if necessary.

〔Effect of the invention〕

As explained above, according to the present invention, since the boundary between the semiconductor active layer and the insulating layer is placed within the opening of the gate-patterned photoresist, even if the width of the opening is about the conventional width, the gate length Lg can be shortened. In addition, since the cross-sectional shape of the gate electrode is a pine mushroom type in which the upper part is larger, gate resistance can be reduced at the same time.

[Brief explanation of drawings]

1 to 1O are cross-sectional views of a semiconductor device showing a method for manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps;
FIGS. n to 14 are cross-sectional views of a semiconductor device showing a conventional method for manufacturing a semiconductor device in order of steps. In the figure, (1) is a semiconductor substrate, (2) is a semiconductor active layer, (3) is a drain electrode, (4) is a source electrode, (
5), (9) αQ is photoresist, (6) is recess, (7) a gate electrode, (8) is insulating layer, (3o)
td drain electrode metal. (7o) is the gate metal. In each figure, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] A step of forming an insulating layer on a semiconductor active layer formed on a semiconductor substrate, a step of forming a source electrode and a drain electrode by leaving the above insulating layer between the source and drain, and a step of forming an upper front insulating layer remaining between the source and drain. a step of etching away the desired amount of the semiconductor active layer on the source electrode side or the drain electrode side; a step of gate patterning so that the boundary between the semiconductor active layer and the insulating layer is located within the opening of the photoresist; A method for manufacturing a semiconductor device, comprising the steps of forming a recess in a layer and forming a gate electrode by a vacuum evaporation method, a lift-off method, or the like.