JPH04144143A - Connection of semiconductor device - Google Patents
Connection of semiconductor deviceInfo
- Publication number
- JPH04144143A JPH04144143A JP2266506A JP26650690A JPH04144143A JP H04144143 A JPH04144143 A JP H04144143A JP 2266506 A JP2266506 A JP 2266506A JP 26650690 A JP26650690 A JP 26650690A JP H04144143 A JPH04144143 A JP H04144143A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- electrode
- semiconductor device
- electrodes
- bump
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 238000009713 electroplating Methods 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 claims description 13
- 239000010949 copper Substances 0.000 abstract description 14
- 238000007747 plating Methods 0.000 abstract description 11
- 238000007772 electroless plating Methods 0.000 abstract description 8
- 239000002184 metal Substances 0.000 abstract description 6
- 229910052751 metal Inorganic materials 0.000 abstract description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052802 copper Inorganic materials 0.000 abstract description 5
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract 1
- 229910000679 solder Inorganic materials 0.000 description 11
- 238000010438 heat treatment Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 206010070834 Sensitisation Diseases 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000008313 sensitization Effects 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 description 1
- 101100028920 Neurospora crassa (strain ATCC 24698 / 74-OR23-1A / CBS 708.71 / DSM 1257 / FGSC 987) cfp gene Proteins 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910052770 Uranium Inorganic materials 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229920000728 polyester Polymers 0.000 description 1
- 241000894007 species Species 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
Landscapes
- Chemically Coating (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、半導体素子のフリップチップ実装方法に於け
る半導体素子の接続方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for connecting semiconductor elements in a flip-chip mounting method for semiconductor elements.
（従来の技術）
従来、このような分野の技術としては、例えばｒハイブ
リッドマイクロエレクトロニクス」発行所■ンーエムン
ー、 １９８５年９月２５日発行、 Ｐ、２１０〜２
１３に記載されるものがあった。(Conventional technology) Conventionally, as a technology in this field, for example, "R Hybrid Microelectronics" Publisher: ■Moon, Published September 25, 1985, P, 210-2
There were 13 items listed.
第２図は従来の半導体接続方法の一例を示す半田バンブ
を用いたフリンプチノブ実装工程断面図である。FIG. 2 is a sectional view of a flimp tip mounting process using solder bumps, showing an example of a conventional semiconductor connection method.
まず、第２図（ａ）に示すように、半導体素子１には、
Ｐｂ−３ｎ系の半田バンプ２が形成されている。また、
基板３には基板電極４が形成されており、半田バンブ２
を接続する箇所以外には半田の流れ防止のために、半田
が濡れない膜（例えばＳ＋０２．Ｓｅｘ Ｎａ、Ｃｒ等
）が半田ダム５として形成され、接続を行う箇所には予
め、半田６が形成されている。これらの半導体素子ｌと
基板３を所定の位置となるようにアライメントを行う。First, as shown in FIG. 2(a), the semiconductor element 1 includes:
Pb-3n solder bumps 2 are formed. Also,
A substrate electrode 4 is formed on the substrate 3, and a solder bump 2
In order to prevent the flow of solder, a film (for example, S+02.Sex Na, Cr, etc.) that does not get wet with solder is formed as a solder dam 5 at locations other than those where the connection is to be made, and solder 6 is formed in advance at the locations where the connection is to be made. has been done. Alignment is performed so that these semiconductor elements 1 and substrate 3 are in predetermined positions.
次いで、第２図（ｂ）に示すように、半田バンブ２と半
田６が溶融するように、融点より高い温度（Ｐｂ−３ｎ
共晶で２１０〜２３０°Ｃ）で加熱を行い、半田バンブ
２と基板電極４との接続を行う。Next, as shown in FIG. 2(b), the temperature is higher than the melting point (Pb-3n) so that the solder bump 2 and the solder 6 melt.
The solder bumps 2 and the substrate electrodes 4 are connected by heating at 210 to 230° C. with eutectic.
（発明が解決しようとする課題）
以上述べたようにフリンブチップ接続方法によれば、−
括で全電極を接続することができ、高密度接続が可能で
あるという特徴を存しているが、加熱を必要とするため
に、使用する基板材料が耐熱性の点で限定され、耐熱温
度の低いポリエステル基板には適用できず、■、ＣＤデ
イスプレー等へ直接チップ実装するのが困難であるとい
う問題点があった。(Problems to be Solved by the Invention) As described above, according to the flimb chip connection method, -
It has the feature of being able to connect all the electrodes in a single bracket, enabling high-density connections, but since it requires heating, the substrate material used is limited in terms of heat resistance, and the heat resistance temperature is limited. It cannot be applied to polyester substrates with a low carbon content, and there is a problem that it is difficult to directly mount a chip on a CD display or the like.
本発明は、以上述べたフリップチップ接続を行う際に加
熱を必要とするという問題点を除去するために、半導体
素子と基板の！種間の接続を、従来の溶融金属を用いる
方法に代えて、電気化学的に析出する、無電解メッキに
よる金属で接合することにより、数１０°Ｃの低温で半
導体素子の接続を確寞に、しかも容易に行い得る半導体
素子の接続方法を提供することを目的とする。The present invention solves the above-mentioned problem of requiring heating when performing flip-chip bonding, and aims to improve bonding between semiconductor elements and substrates. Instead of the conventional method of using molten metal, we use electroless plating to make connections between species, which allows us to reliably connect semiconductor elements at a low temperature of several tens of degrees Celsius. It is an object of the present invention to provide a method for connecting semiconductor elements that can be easily performed.
（課題を解決するための手段）
本発明は、上記したように、半導体素子のフリップチッ
プ実装方法において、半導体素子の電極と基板の電極を
バンブ電極を介在させて接合させ、両ＮＦＩｉを無電解
メツキにより接続させるようにしたものである。(Means for Solving the Problems) As described above, in the flip-chip mounting method of a semiconductor element, the present invention connects the electrode of the semiconductor element and the electrode of the substrate with a bump electrode interposed, and electrolessly connects both NFIi. The connection is made by plating.
（作用）
本発明によれば、半導体素子の接続方法において、半導
体素子のバンブ電極と、その接続を行う基板電極の表面
に無電解メツキが析出する金属を形成し、半導体素子と
基板の位置合わせを行った後に、無電解メツキ液に浸漬
して、バンブ電極と基板電極とを析出金属で接合する。(Function) According to the present invention, in a method for connecting a semiconductor element, metal on which electroless plating is deposited is formed on the bump electrode of the semiconductor element and the surface of the substrate electrode to which the connection is made, and the semiconductor element and the substrate are aligned. After performing this, the bump electrode and the substrate electrode are bonded with the deposited metal by immersion in an electroless plating solution.
従って、接続温度は１００°Ｃ以下の低温で行うことが
でき、耐熱性の低い基板材料を使用する場合にもその電
極の接続を行うことができる。Therefore, the connection can be made at a low temperature of 100° C. or less, and even when a substrate material with low heat resistance is used, the electrodes can be connected.
（実施例）
以下、本発明の実施例について図面を参照しながら詳細
に説明する。(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.
第１６は本発明による半導体素子の基板への接続工程断
面図である。16 is a sectional view showing a process of connecting a semiconductor element to a substrate according to the present invention.
まず、第１図（ａ）に示すように、半導体素子１１のＡ
１１ｉ極１２には、ｃｔｌバンプ電極１３がＣｒを密着
金属として電気メツキ法により３０μｍの厚さで形成さ
れている。このＣ，ｕバンブ電極１３には、選択的にＰ
ｄ膜１４を１００人蒸着し、Ｃｕバンプ電極１３以外：
はバノノヘーシゴン膜であるＳｉ３Ｎ４膜１５が形成さ
れている。First, as shown in FIG. 1(a), A of the semiconductor element 11 is
On the 11i pole 12, a CTL bump electrode 13 is formed with a thickness of 30 μm by electroplating using Cr as an adhesive metal. This C, U bump electrode 13 is selectively provided with P.
d film 14 was deposited by 100 people, except for the Cu bump electrode 13:
A Si3N4 film 15, which is a Banonoheshigon film, is formed.
一方、基板１６においては、その基板電極１７上にもＰ
ｄ１ｌＸ１８が１００人葵着してあり、Ｃｕハンフ゛電
極１３と接続する箇所を除いて、エポキシ系のメ。On the other hand, in the substrate 16, P is also on the substrate electrode 17.
100 d1l
キレシスト１９が形成されている。A chirecyst 19 is formed.
次に、第１図（ｂ）に示すように、これらの半導体素子
１１と基板Ｉ６の位置合わせを行い、Ｃｕバンプ電極１
３を基板電極１７上に位置させ、半導体素子１１を基板
１６に押圧しながら４０”Ｃの無電解銅メツキ１（日本
ンエーリングプリントガント８２０：商品名）に浸漬す
る。この時、無電解銅メツキ液は半導体素子１１と基板
１６との間隙で良く液交換できるよう攪拌する。４５分
間メツキを施した後、水洗、乾燥を行う。Next, as shown in FIG. 1(b), these semiconductor elements 11 and the substrate I6 are aligned, and the Cu bump electrodes 1
3 is placed on the substrate electrode 17, and the semiconductor element 11 is immersed in 40"C electroless copper plating 1 (Japan Ehling Print Gant 820: trade name) while pressing the semiconductor element 11 against the substrate 16. At this time, the electroless copper plating 1 The copper plating solution is stirred in the gap between the semiconductor element 11 and the substrate 16 so that the solution can be exchanged well.After plating for 45 minutes, washing and drying are performed.
すると、第１図（ｃ）に示すように、厚さ３μｍの無電
解Ｃｕメツキ皮膜２０が析出され、総べてのＣｕバンブ
電極１３と基板ｉＩｔ掻１７を接合して電気的に接続す
ることができる。Then, as shown in FIG. 1(c), an electroless Cu plating film 20 with a thickness of 3 μm is deposited, and all the Cu bump electrodes 13 and the substrate iIt scraper 17 are bonded and electrically connected. I can do it.
上記実施例では密着によるＰｄを無電解メツキの核とし
て使用したが、５ｎＣｆｆｉ□、ＰｄＣ１！の溶液によ
る感受化、活性化処理を用いても同様の効果が期待でき
、また、無電解メツキが直接析出する金属であれば、前
述の感受化、活性化処理を省略してもよい。In the above example, Pd in close contact was used as the nucleus for electroless plating, but 5nCffi□, PdC1! A similar effect can be expected by using sensitization and activation treatment using a solution of 1. If the metal is one on which electroless plating is directly deposited, the above-mentioned sensitization and activation treatment may be omitted.
また、無電解メツキ液も本実施例ではＣｕを用いたが、
これに限定されるものではなく、層付けできるものであ
ればＮｉ、Ａｕ等も使用することができる。更に、バン
ブ電極も半導体素子側でなく基板側もしくは両方に形成
するようにしてもよい。In addition, although Cu was used as the electroless plating solution in this example,
The material is not limited to this, and Ni, Au, etc. can also be used as long as they can be layered. Furthermore, the bump electrode may also be formed not on the semiconductor element side but on the substrate side or both.
なお、本発明は上記実施例に限定されるものではなく、
本発明の趣旨に基づいて種々の変形が可能であり、これ
らを本発明の範囲から排除するものではない。Note that the present invention is not limited to the above embodiments,
Various modifications are possible based on the spirit of the present invention, and these are not excluded from the scope of the present invention.
（発明の効果）
以上、詳細に説明したように、本発明によれば、半導体
素子と基板間の電極を無電解メツキにより接続するよう
にしたので、接続温度は１００℃以下の低温で行うこと
ができ、耐熱性の低い基板であっても、その電極の接続
を確実にしかも容易に行うことができる。(Effects of the Invention) As described above in detail, according to the present invention, the electrodes between the semiconductor element and the substrate are connected by electroless plating, so the connection temperature can be as low as 100°C or lower. This makes it possible to connect the electrodes reliably and easily even with substrates with low heat resistance.
第１図は本発明の実施例を示す半導体素子の基板への接
続工程断面図、第２図は従来の半導体素子の接続方法の
一例を示す半田バンブを用いたフリンプチノプ実装工程
断面図である。
１１・・・半導体素子、１２・・・へ！電極、１３・・
・Ｃｕハンフｉｆ 極、１４．１８・・・Ｐｄ膜、１５
・・・パノシヘーノヨン膜、１６・・・基板、１７・・
・基板電極、１９・・・メツキレシスト、２０・・・無
電解Ｃｕメッキ皮膜。
特許出願人 沖電気工業株式会社
代理人 弁理士 清 水 守（外２名）第
図FIG. 1 is a cross-sectional view of a process of connecting a semiconductor element to a substrate according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view of a process of mounting a flimp tip using solder bumps, showing an example of a conventional method of connecting a semiconductor element. 11... Semiconductor element, 12... to! Electrode, 13...
・Cu Hanf if pole, 14.18...Pd film, 15
... Panoshihenoyon film, 16... Substrate, 17...
- Substrate electrode, 19... Metsuki resist, 20... Electroless Cu plating film. Patent applicant: Oki Electric Industry Co., Ltd. Agent: Patent attorney: Mamoru Shimizu (2 others) Fig.
Claims (1)
在させて接合させ、 （ｂ）前記半導体素子の電極と基板の電極を無電解メッ
キにより接続させることを特徴とする半導体素子の接続
方法。[Claims] In a flip-chip mounting method for a semiconductor element, (a) an electrode of the semiconductor element and an electrode of a substrate are bonded with a bump electrode interposed therebetween; (b) an electrode of the semiconductor element and an electrode of the substrate are bonded to each other with a bump electrode interposed therebetween; A method for connecting semiconductor elements, characterized by connecting them by electrolytic plating.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2266506A JPH04144143A (en) | 1990-10-05 | 1990-10-05 | Connection of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2266506A JPH04144143A (en) | 1990-10-05 | 1990-10-05 | Connection of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04144143A true JPH04144143A (en) | 1992-05-18 |
Family
ID=17431861
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2266506A Pending JPH04144143A (en) | 1990-10-05 | 1990-10-05 | Connection of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04144143A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0592938A1 (en) * | 1992-10-16 | 1994-04-20 | AMEG Additive Metallisierung- Eentwicklungs und Anwendungsgesellschaft mbH | Process for mounting and contacting electronic components on an insulating support |
| US8334594B2 (en) | 2009-10-14 | 2012-12-18 | Advanced Semiconductor Engineering, Inc. | Chip having a metal pillar structure |
| US8552553B2 (en) | 2009-10-14 | 2013-10-08 | Advanced Semiconductor Engineering, Inc. | Semiconductor device |
| US8686568B2 (en) | 2012-09-27 | 2014-04-01 | Advanced Semiconductor Engineering, Inc. | Semiconductor package substrates having layered circuit segments, and related methods |
| US8698307B2 (en) | 2010-09-27 | 2014-04-15 | Advanced Semiconductor Engineering, Inc. | Semiconductor package with integrated metal pillars and manufacturing methods thereof |
| US8884443B2 (en) | 2012-07-05 | 2014-11-11 | Advanced Semiconductor Engineering, Inc. | Substrate for semiconductor package and process for manufacturing |
-
1990
- 1990-10-05 JP JP2266506A patent/JPH04144143A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0592938A1 (en) * | 1992-10-16 | 1994-04-20 | AMEG Additive Metallisierung- Eentwicklungs und Anwendungsgesellschaft mbH | Process for mounting and contacting electronic components on an insulating support |
| US8334594B2 (en) | 2009-10-14 | 2012-12-18 | Advanced Semiconductor Engineering, Inc. | Chip having a metal pillar structure |
| US8552553B2 (en) | 2009-10-14 | 2013-10-08 | Advanced Semiconductor Engineering, Inc. | Semiconductor device |
| US8698307B2 (en) | 2010-09-27 | 2014-04-15 | Advanced Semiconductor Engineering, Inc. | Semiconductor package with integrated metal pillars and manufacturing methods thereof |
| US8884443B2 (en) | 2012-07-05 | 2014-11-11 | Advanced Semiconductor Engineering, Inc. | Substrate for semiconductor package and process for manufacturing |
| US9224707B2 (en) | 2012-07-05 | 2015-12-29 | Advanced Semiconductor Engineering, Inc. | Substrate for semiconductor package and process for manufacturing |
| US9437532B2 (en) | 2012-07-05 | 2016-09-06 | Advanced Semiconductor Engineering, Inc. | Substrate for semiconductor package and process for manufacturing |
| US8686568B2 (en) | 2012-09-27 | 2014-04-01 | Advanced Semiconductor Engineering, Inc. | Semiconductor package substrates having layered circuit segments, and related methods |
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| JPS63312830A (en) | Press-bonding method for noble metal foil to substrate | |
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