JPH0414265A - Semiconductor storage device and its manufacture - Google Patents

Abstract

PURPOSE:To surely write and read data by forming diffusion layers in the region between two gate electrodes and both side regions, stretching a conducting film turning to a floating gate on the gate electrode of a selection transistor, and forming a control gate electrode on the conducting film via an insulating film. CONSTITUTION:Photo resist 18 is left on two gate electrodes and in the region between them; by using said resit as a mask, two polycrystalline silicon films 15, 17 and a third SiO2 film 16 are patterned. Thereby the first polycrystalline silicon film 15 which is electrically connected with a first gate electrode 4 through a contact hole 14 is formed as far as a region covering a second gate electrode. Diffusion layers 6, 7 are applied to the source and the drain of a memory transistor T1. The first gate electrode 4 and the first polycrystalline silicon film 15 are used as the floating gate FG of the memory transistor T1. A second polycrystalline silicon film formed above the first polycrystalline silicon film 15 is used as a control gate electrode CG.

Description

[Detailed Description of the Invention] [Summary] Regarding a semiconductor memory device in which data can be electrically rewritten and a method for manufacturing the same, the present invention relates to a semiconductor memory device in which data can be electrically rewritten and a manufacturing method thereof, which aims at miniaturizing cells and increasing the coupling ratio between a floating gate electrode and a control gate electrode. The first and second gate electrodes are formed on the semiconductor layer via an insulating film, and the regions between the first and second gate electrodes and the regions on both sides are formed in a self-aligned manner. an insulating film that covers the first and second gate electrodes and the diffusion layer, and an insulating film between the first and second gate electrodes that is thinner than the insulating film. the formed tunnel insulating film; a first conductive film formed on the insulating film in contact with the first gate electrode; and a first conductive film formed along the first conductive film with the insulating film in between. and a second conductive film.

[Industrial Field of Application] The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly to a semiconductor memory device in which electrically rewritable data can be written and a method of manufacturing the same.

(Prior art) As a memory element in which data can be electrically rewritten,
OT OX (Floating gate tun
nel oxide) cells are known.

This FLOTOX cell is composed of a memory transistor Tm and a selection transistor Ts as illustrated in FIG. ,c
, a floating gate electrode e attached thereon via a first insulating film d, and a control gate electrode g formed thereon with a second insulating film f interposed therebetween. By the way, the pole e of the floating gate is
It is formed to a size that reaches above one of the diffusion layers C, and in that region, the floating gate electrode e is formed in the diffusion layer C.
It protrudes to the side, and the underlying insulating film d is thinned to become a tunnel insulating film, so that carriers move between the diffusion layer C and the floating gate electrode fie due to the tunnel effect. has been done.

The selection transistor Ts also includes two diffusion layers iJ provided at intervals on the surface layer of the semiconductor substrate a, and a word line formed between these diffusion layers i and j with an insulating film d interposed therebetween. One diffusion layer i is formed adjacent to the diffusion layer C under the tunnel insulating film.

Note that q indicates an insulating film for element isolation, and r indicates a cover film.

The equivalent circuit of a FLOTOX cell having such a configuration is shown in FIG.

In the process of forming this FLOTOX cell, as illustrated in FIG. 4(a), first, a first insulating film d is laminated on a semiconductor substrate a on which two diffusion layers of a memory transistor Tm are formed. After that, the insulating film d on one of the diffusion layers C is thinned to form a tunnel insulating film, a first conductive film is formed on this, and a second insulating film is formed on this. membrane f
and a second conductive film U are sequentially laminated (FIG. 4(b)).

After this, four films d, t, f, u are formed on the semiconductor substrate a.
By patterning two diffusion layers, c
a first region α extending from between the regions onto one of the diffusion layers C;
These films are left in the second region β that is set at intervals from now on (FIG. 4(C)).

Next, using the film extending from the first insulating film d to the second conductive film U existing in the second region β as a mask, impurity ions are implanted into the semiconductor substrate a on both sides thereof, and the impurity ions are diffused. Diffusion layer i for the selection transistor Ts in a self-aligned manner by
j (Fig. 4(d)).

In this way, the diffusion layers S, c of the memory transistor Tm
The first and second conductive films t#t and u formed thereon are used as floating gates e1 and control gates g, respectively, and the first and second conductive films t#t in other regions are used as floating gates e1 and control gates g, respectively.
, u are short-circuited through a contact hole (not disclosed) and used as the word line gate electrode I of the selection transistor Ts.

Incidentally, the reason why the diffusion layer bC of the memory transistor Tm is formed first is that because one of the diffusion layers C is covered by the floating gate e due to its structure, it is necessary to form this in advance. In this case, it is possible to form the other diffusion layer in a self-aligned manner, but if this is done, the gap between the two diffusion layers will change due to misalignment of the mask, resulting in a channel length. is not constant, resulting in an inconvenience that the characteristics of the transistor are not constant.

[Problem to be solved by the invention]

Therefore, when forming a FLOTOX cell through such a process, a margin is required to connect the diffusion layer C of the memory transistor Tm and the diffusion layer 1 of the selection transistor Ts, taking into consideration the positional deviation of the word line gate electrode 1. In addition, it is necessary to form the diffusion layer C located below wide enough to take into account the deviation of the insulating film, which increases the area of the cell and makes it difficult to increase the density. There is a problem that it cannot be rotated.

Moreover, since the floating gate e and control gate g formed by such a process are made of flat films, the coupling capacitance between them decreases as the cell becomes finer, making it difficult to write and read data. An additional disadvantage is that errors are more likely to occur.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems.It is therefore an object of the present invention to provide a method for manufacturing a semiconductor device that can miniaturize cells and increase the coupling ratio between a floating gate electrode and a control gate electrode. With the goal.

[Means to solve the problem]

The above-mentioned problem is solved by the first and second gate electrodes 4.5 formed on the semiconductor layer l via the insulating film 3 and the first and second gate electrodes 4.5, as illustrated in FIG. Three diffusion layers 6 to 8 formed in a self-aligned manner in the region between the second gate electrode 4.5 and the regions on both sides, and the first and second gate electrodes 4.5 and the diffusion layers 6 to 8. 8 and the insulating film 9 between the first and second gate electrodes 4.5,
A thick insulating film 13 formed thinner than the insulating film 9
, a first conductive film 15 formed on the insulating film 9 in contact with the first gate electrode 4, and an insulating film 16.
and a second conductive film F formed along the first conductive film [5], or as illustrated in FIG. 2(e), The first conductive film 15.23 is formed to have a comb-like cross section, and the second conductive film 117.26 is formed to have a comb-like cross section, so that the first conductive film 15.23 is covered with an insulating film 9.16. 21.24, or as illustrated in FIG. 1, a first gate electrode 4 constituting a floating gate FC of a memory transistor T and a selection transistor a step of forming the second gate electrode 5 constituting the gate of T2 on the semiconductor layer 1 via the insulating film 3; and a step of forming the second gate electrode 5 constituting the gate of T2, and
．． By press-injecting impurity ions into the semiconductor layer using 5 as a mask, the first and second gate electrodes 4.5
A step of forming three diffusion layers 6 to 8 in the region between them and regions on both sides, a step of laminating an insulating film 9 over the entire region, and a step of forming the insulating film 9 in the region between the first and second gate electrodes 4.5. After forming a tunnel insulating film 13 by thinning the existing insulating film 9 and forming a contact hole 14 in the insulating film 9 on the first gate electrode 4, the contact hole 1 is formed.
4 and on the insulating film 9, the floating gate)
A step of forming the first conductive film 15 which becomes the FC, and a step of forming the second conductive film 17 which becomes the control gate of the memory transistor through the insulating film 16.
This is achieved by a method of manufacturing a semiconductor memory device, which includes a step of forming the semiconductor memory device along the steps of FIG.

[For production]

According to the invention 1.3, the first gate electrode 4 used for the floating gate FG of the memory transistor T1 and the second gate electrode 8ji5 used for the gate of the selection transistor T2 are formed on the semiconductor layer 1, Diffusion layers 6 to 8 are formed in a self-aligned manner in a region between these two gate electrodes 4.5 and regions on both sides, and a conductive film 15 that becomes a floating gate FC is formed on the gate electrode 5 of the selection transistor T2. A control gate electrode 17 is formed on the insulating film 16 with an insulating film 16 interposed therebetween.

When writing data in a FLOTOX cell formed by such a memory transistor T or selection transistor T2, a power supply voltage is applied to the first diffusion layer 6 under the tunnel oxide film 13 in the memory transistor T1. Then, when the potential of the second diffusion layer 7 and the control gate electrode CG is made higher by a predetermined value, the charge of the first diffusion layer 6 is transferred to the tunnel oxide film 13 due to the tunnel effect.
The electrons accumulated in the floating gate electrode FC are emitted to the first diffusion layer through the first diffusion layer.

When erasing the memory, a predetermined voltage is applied to the control gate electrode CG, and the potential of the first diffusion layer 6 is lowered to a predetermined value, and the tunnel oxide film 13 is applied to the following gate electrode FG. Electrons are injected from the first diffusion layer 6 through the first diffusion layer 6.

In this case, the first conductive film 15 constituting the floating gate electrode FC is the insulating film 1 covering the second gate electrode 5.
6, the area can be increased accordingly, and when the area facing the control gate electrode CG is increased, the coupling capacitance stored by these increases, the coupling ratio increases, and data writing , reading can be performed reliably.

Moreover, since the diffusion layers 6 to 8 of the memory transistor T and the selection transistor T2 are formed in a self-aligned manner,
There is no need to consider the alignment accuracy with the first and second gate electrodes 4.5, and the area of the cell is reduced accordingly.

In this case, since the coupling ratio can be made sufficiently large as described above, it becomes possible to cope with miniaturization of cells.

Further, according to the second invention, since the control gate electrode CG and the floating gate electrode FC of the memory transistor T are formed to have a comb-shaped cross section and are opposed to each other in a non-contact state, the opposing area The coupling capacity can be increased by increasing the FLOTOX
Even if the cells are further miniaturized, the coupling ratio will not decrease.

〔Example〕

Therefore, the details of the present invention will be explained below based on the drawings.

(a) Description of First Embodiment of the Present Invention FIG. 1 is a sectional view showing the steps of forming a device according to the first embodiment of the present invention.

Reference numeral 1 in the figure indicates a P-type semiconductor substrate made of silicon, and the surface of the region surrounded by the element isolation insulating film 2 on the semiconductor substrate 1 has a thickness of about 200 to 1,000. A SiO□ film 3 is formed, and two gate electrodes 4.5 made of doped silicon are formed on the SiO□ film 3 with an interval of about 1 to 3 μm. Impurity ions are implanted into the semiconductor substrate 1 on both sides of the electrode 4.5 using the gate electrode 4.5 as a mask, and N° type diffusion layers 6.7.8 are formed in a self-aligned manner. (Figure 1(a)).

In such a state, first, the second SiO□
After laminating the film 9 to a thickness of about 300 to 1,000 layers, a photoresist 10 is applied, exposed and developed to create a pattern between the two gate electrodes 4.50 along the gate electrode 4.5. A window 11 with a width of about 1 μm is formed (first
Figure (b)).

Then, the SiO□ film 9 exposed through the window 11 and the S below it.
The iO□ film 3 is etched with hydrofluoric acid (IF) and Si
Form an opening 12 in the O□ film 3.9 (Fig. 1(C))
.

Next, after the photoresist 10 is ashed, the opening 12 is
By thermally oxidizing the exposed surface of the semiconductor substrate 1, a tunnel oxide film 13 made of 5i02 is formed on the surface to a thickness of about 100 mm (FIG. 1(d)).

Furthermore, a second SiO□
The film 9 is patterned to form a contact hole 14 on the first gate electrode 4 (FIG. 1(e)).

After this, the first polycrystalline silicon film 15 containing impurities such as phosphorus is deposited at 1,000 to 4,000 by CVD method.
A third 5iOz film 16 and a second polycrystalline silicon film 17 containing impurities are grown on this film to a thickness of 1,000 to 4000 μm each by CVD.
,000 people thick (first round (f)).

Next, a photoresist 18 is applied, exposed and developed to leave a photoresist 18 in the area between the two gate electrodes 4.5, and using this as a mask, reactive ion etching is performed. , the two polycrystalline silicon films 15 and 17 and the third SiO□ film 16 are patterned (first [iJ(g)).

As a result, the second polycrystalline silicon film 15, which is electrically connected to the first gate electrode 4 through the contact hole 14, is formed up to the region covering the second gate electrode.

After that, the whole will be covered with a cover W1.19 such as PSG.

In the FLOTOX cell formed in this way, the diffusion layers 6.7 formed on both sides of the first gate electrode 4 are used as the source and drain of the memory transistor T. The electrode 4 and the first polycrystalline silicon film 15 connected thereto are connected to a memory transistor T,
Furthermore, the second polycrystalline silicon film provided above the first polycrystalline silicon film 15 is used as the control gate electrode CG.

Further, the second gate electrode 5 is used as the word line gate electrode WG of the selection transistor T2, and the diffusion layers 6.8 on both sides thereof are used as the lower two sources and drains of the selection transistor.

Next, the operation of this FLOTOX cell will be explained.

In the FLOTOX cell formed by the above method, when writing data, voltage vpp is applied to the first diffusion layer 6 under the oxide film 13 in the memory transistor T1. When the potential of the second diffusion layer 7 and the control gate electrode CG is increased by a predetermined value, the electrons of the floating gate electrode F are emitted into the first diffusion layer 6 through the tunnel oxide film 13 due to the tunnel effect. That will happen.

In addition, when erasing the memory, the voltage V22 is applied to the control gate electrode CG, the potential of the first diffusion layer 6 is lowered to a predetermined value, and the tunnel oxide film 13 is passed through the following gate electrode FC. Electrons are injected from the first diffusion layer 6.

In this case, since the first polycrystalline silicon film 15 constituting the floating gate electrode FG extends to a region covering the second gate electrode 5, the area facing the control gate electrode CG thereon is Since the coupling capacitance stored by these increases, the coupling ratio increases and data writing and subsequent output can be performed reliably.

Moreover, since the diffusion layers 6 to 8 of the memory transistor T1 and the selection transistor T2 are formed in a self-aligned manner,
There is no need to consider alignment accuracy with the gate electrode 4.5, and the area of the cell is reduced accordingly. In this case, since the coupling ratio can be made sufficiently large as described above, it becomes possible to correspond to miniaturization.

(b) Description of the second embodiment of the present invention In the embodiments described above, the control gate electrode CG and the following gate electrode FG were formed in a single layer and faced each other, but as shown in FIG. The structure can be modified to increase capacity.

FIG. 2 is a sectional view showing the process of forming a device according to a second embodiment of the present invention.

First, from the state shown in FIG. 1(e), a first polycrystalline silicon film 15 containing impurities is laminated and patterned by photolithography to form two gate electrodes 4.5 and tunnel oxide. The first polycrystalline silicon film 15 is left in the region spanning the film 13 and is connected to the first gate electrode 4 through the contact hole 14. Then, a third SiO□ film 16 and a second polycrystalline silicon film 17 containing impurities are sequentially laminated thereon (FIG. 2(a)).

After this, the second polycrystalline silicon film 17 is patterned in the same manner as the first polycrystalline silicon film 15, and is left in the region covering the second gate electrode 5 and tunnel oxide film 13. Then, a fourth 5i (h film 21) is laminated on the entire surface (second step (b)).

Thereafter, a second contact hole 22 is formed on the first gate electrode 4 by patterning the third and fourth SiO□ films 16.21, and then a third contact hole 22 containing impurities is formed on the first gate electrode 4. A crystalline solicon film 23 is laminated, and this film 2
3 is connected to the first polycrystalline silicon film 15 through the second contact hole 22 (second stage (C)).

Next, the third polycrystalline silicon film 23 is patterned,
Third polycrystalline silicon film 23 is left in a region covering first gate electrode 4 and tunnel oxide M13.

Furthermore, after laminating the fifth SiO□ film 24 on top of this,
The fourth and fifth 5iO7 films 21 and 24 are patterned to form contact holes 2 in the area above the second gate electrode 5.
5 is formed, and then a fourth polycrystalline silicon film 26 containing impurities is laminated thereon, and this is patterned to remain in the region spanning the first and second gate electrodes 4.5.

After this, the entire structure is covered with a cover film (not shown).

According to this, the FL surrounded by the element isolation insulating film 2
In the OTOX cell formation region, the control gate electrode CG and floating gate electrode FG of the memory transistor T1 are formed to have a comb-shaped cross section and are opposed to each other in a non-contact state, so that the opposing area becomes large. The coupling capacitance is increased compared to the device of the first embodiment, and the coupling ratio does not decrease even if the FLOTOX cell is further miniaturized.

[Effects of the Invention] According to the invention 1.3, the first gate electrode used for the floating gate of the memory transistor and the second gate electrode used for the gate of the selection transistor are formed on the semiconductor layer. A diffusion layer is formed in a self-aligned manner in the region between the two gate electrodes and the regions on both sides, and a conductive film that will become a floating gate is extended over the gate electrode of the selection transistor, and an insulating film is formed on it. Since the control gate electrode is formed through the gate electrode, the area of the first R electric film constituting the floating gate electrode is increased because it is formed on the insulating film that covers the second gate electrode. By doing so, the area facing the control gate electrode can be increased, and since the coupling capacitance stored by these increases, the coupling ratio becomes larger, making it possible to write and read data reliably. .

Moreover, since the diffusion layers of the memory transistor and selection transistor are formed in a self-aligned manner, there is no need to consider alignment accuracy with the first and second gate electrodes, and the area of the cell can be reduced accordingly. It becomes possible to do so. Furthermore, as described above, since the areas of the following gate and the control gate can be increased to make the coupling ratio sufficiently large, it becomes possible to correspond to miniaturization of cells.

Further, according to the second invention, the control gate electrode and the floating gate upper electrode of the memory transistor are formed to have a comb-shaped cross section and are opposed to each other in a non-contact state, so that the opposing area can be increased. When the FLOTOχ cell is further miniaturized, the reduction in the coupling ratio can be suppressed.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing the forming process of a device according to the first embodiment of the present invention, FIG. 2 is a cross-sectional view showing the forming process of a device according to the second embodiment of the present invention, and FIG. FIG. 4 is a cross-sectional view showing an example of a method of forming a conventional device, and FIG. 5 is an equivalent circuit diagram of a FLOTOX cell. (Explanation of symbols) 1...Semiconductor substrate (semiconductor N), 3.9.16.2J, 24...SiO□ film (insulating film)
, 4.5... Gate electrode, 6.7.8... Diffusion layer, 13... Tunnel oxide film (tunnel insulating film), 14.
22.25...Contact hole, 15.17.23
．． 26... Polycrystalline silicon film (conductive film), FG...
Floating gate electrode, CG...control gate 'Rh, T1...memory transistor, T2...selection transistor. Applicant Fujitsu Limited

Claims (3)

[Claims] (1) First and second gate electrodes formed on the semiconductor layer via an insulating film, and self-aligned gate electrodes formed in a region between and on both sides of the first and second gate electrodes. three diffusion layers; an insulating film covering the first and second gate electrodes and the diffusion layer; and an insulating film formed between the first and second gate electrodes to be thinner than the insulating film. a first conductive film formed on the insulating film in contact with the first gate electrode; and a first conductive film formed along the first conductive film with the insulating film in between. A semiconductor memory device comprising a second conductive film. (2) In claim 1, the first conductive film is formed to have a comb-like cross-section, and the second conductive film is formed to have a comb-like cross-section and faces the first conductive film with an insulating film interposed therebetween. A semiconductor memory device characterized by: (3) forming a first gate electrode constituting the floating gate of the memory transistor and a second gate electrode constituting the gate of the selection transistor on the semiconductor layer via an insulating film; and forming three diffusion layers in a region between the first and second gate electrodes and regions on both sides by implanting impurity ions into the semiconductor layer using the second gate electrode as a mask; forming a tunnel insulating film by thinning the insulating film existing in the region between the first and second gate electrodes; and forming a tunnel insulating film on the first gate electrode. after forming a contact hole in the insulating film, forming a first conductive film that will become the floating gate inside the contact hole and on the insulating film; and a second conductive film that will become the control gate of the memory transistor. A method for manufacturing a semiconductor memory device, comprising the step of forming a conductive film along the first conductive film with an insulating film interposed therebetween.